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mskvortsov/Long.log

Created January 12, 2017 16:14
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Long.log
****** START compiling Test:LongId(long):long (MethodHash=0f9627fe)
Generating code for Unix arm
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 02 ldarg.0
IL_0001 2a ret
Set preferred register for V00 to [r0]
Additional preferred register for V00 from [r0] to [r0-r1]
Arg #0 passed in register(s) r0,r1
; Initial local variable assignments
;
; V00 arg0 long
*************** In compInitDebuggingInfo() for Test:LongId(long):long
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 1
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 002h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Test:LongId(long):long
Jump targets:
none
New Basic Block BB01 [000951B4] created.
BB01 [000..002)
IL Code Size,Instr 2, 2, Basic Block count 1, Local Variable Num,Ref count 1, 1 for method Test:LongId(long):long
OPTIONS: opts.MinOpts() == false
Basic block list for 'Test:LongId(long):long'
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return)
-------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Test:LongId(long):long
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Test:LongId(long):long'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ret
[000003] ------------- ▌ stmtExpr void (IL 0x000... ???)
[000002] ------------- └──▌ return long
[000001] ------------- └──▌ lclVar long V00 arg0
New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** In fgInline()
*************** After fgInline()
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
***** BB01, stmt 1
[000003] ------------- ▌ stmtExpr void (IL 0x000...0x001)
[000002] ------------- └──▌ return long
[000001] ------------- └──▌ lclVar long V00 arg0
-------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
**************** Inline Tree
Inlines into 06000001 Test:LongId(long):long
Budget: initialTime=66, finalTime=66, initialBudget=660, currentBudget=660
Budget: initialSize=176, finalSize=176
*************** After fgAddInternal()
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i
-------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgPromoteStructs()
*************** In fgMarkAddressExposedLocals()
*************** In fgMorphBlocks()
Morphing BB01 of 'Test:LongId(long):long'
fgMorphTree BB01, stmt 1 (before)
[000002] ------------- ▌ return long
[000001] ------------- └──▌ lclVar long V00 arg0
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i
-------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
*************** In fgComputePreds()
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i
-------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeEdgeWeights()
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
fgComputeEdgeWeights() was able to compute exact edge weights for all of the 0 edges, using 1 passes.
*************** In fgCreateFunclets()
After fgCreateFunclets()
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In optOptimizeLayout()
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
After computing reachability:
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
*************** In Allocate Objects
Trees before Allocate Objects
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
***** BB01, stmt 1
[000003] ------------- ▌ stmtExpr void (IL 0x000...0x001)
[000002] -----+------- └──▌ return long
[000001] -----+------- └──▌ lclVar long V00 arg0
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Allocate Objects
Trees after Allocate Objects
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
***** BB01, stmt 1
[000003] ------------- ▌ stmtExpr void (IL 0x000...0x001)
[000002] -----+------- └──▌ return long
[000001] -----+------- └──▌ lclVar long V00 arg0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optOptimizeLoops()
*************** In fgDebugCheckBBlist
*************** In optCloneLoops()
*************** In lvaMarkLocalVars()
lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
*** marking local variables in block BB01 (weight= 1 )
[000003] ------------- ▌ stmtExpr void (IL 0x000...0x001)
[000002] -----+------- └──▌ return long
[000001] -----+------- └──▌ lclVar long V00 arg0
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
*************** In optAddCopies()
refCnt table for 'LongId':
V00 arg0 [ long]: refCnt = 3, refCntWtd = 3 pref [r0-r1]
V01 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
The biggest BB has 2 tree nodes
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
***** BB01, stmt 1
( 4, 3) [000003] ------------- ▌ stmtExpr void (IL 0x000...0x001)
N002 ( 4, 3) [000002] ------------- └──▌ return long
N001 ( 3, 2) [000001] ------------- └──▌ lclVar long V00 arg0
-------------------------------------------------------------------------------------------------------------------
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 2.
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
*************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...)
*************** In SsaBuilder::InsertPhiFunctions()
*************** In fgLocalVarLiveness()
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00}
DEF(0)={ }
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00}
OUT(0)={ }
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
***** BB01, stmt 1
( 4, 3) [000003] ------------- ▌ stmtExpr void (IL 0x000...0x001)
N002 ( 4, 3) [000002] ------------- └──▌ return long
N001 ( 3, 2) [000001] ------------- └──▌ lclVar long V00 arg0 u:2 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In optEarlyProp()
*************** In fgValueNumber()
Heap Initial Value in BB01 is: $c0
The SSA definition for heap (#2) at start of BB01 is $c0 {InitVal($41)}
***** BB01, stmt 1 (before)
N002 ( 4, 3) [000002] ------------- ▌ return long
N001 ( 3, 2) [000001] ------------- └──▌ lclVar long V00 arg0 u:2 (last use)
N001 [000001] lclVar V00 arg0 u:2 (last use) => $80 {InitVal($40)}
N002 [000002] return => $100 {100}
***** BB01, stmt 1 (after)
N002 ( 4, 3) [000002] ------------- ▌ return long $100
N001 ( 3, 2) [000001] ------------- └──▌ lclVar long V00 arg0 u:2 (last use) $80
finish(BB01).
*************** In optVnCopyProp()
*************** In SsaBuilder::ComputeDominators(Compiler*, ...)
Copy Assertion for BB01
Live vars: {V00} => {}
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
***** BB01, stmt 1
( 4, 3) [000003] ------------- ▌ stmtExpr void (IL 0x000...0x001)
N002 ( 4, 3) [000002] ------------- └──▌ return long $100
N001 ( 3, 2) [000001] ------------- └──▌ lclVar long V00 arg0 u:2 (last use) $80
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
*************** In optAssertionPropMain()
Blocks/Trees at start of phase
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
***** BB01, stmt 1
( 4, 3) [000003] ------------- ▌ stmtExpr void (IL 0x000...0x001)
N002 ( 4, 3) [000002] ------------- └──▌ return long $100
N001 ( 3, 2) [000001] ------------- └──▌ lclVar long V00 arg0 u:2 (last use) $80
-------------------------------------------------------------------------------------------------------------------
*************** In OptimizeRangeChecks()
Blocks/trees before phase
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
***** BB01, stmt 1
( 4, 3) [000003] ------------- ▌ stmtExpr void (IL 0x000...0x001)
N002 ( 4, 3) [000002] ------------- └──▌ return long $100
N001 ( 3, 2) [000001] ------------- └──▌ lclVar long V00 arg0 u:2 (last use) $80
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
***** BB01, stmt 1
( 4, 3) [000003] ------------- ▌ stmtExpr void (IL 0x000...0x001)
N002 ( 4, 3) [000002] ------------- └──▌ return long $100
N001 ( 3, 2) [000001] ------------- └──▌ lclVar long V00 arg0 u:2 (last use) $80
-------------------------------------------------------------------------------------------------------------------
*************** Exiting IR Rationalize
Trees after IR Rationalize
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
( 4, 3) [000003] ------------- il_offset void IL offset: 0
N001 ( 3, 2) [000001] ------------- t1 = lclVar long V00 arg0 u:2 (last use) $80
┌──▌ t1 long
N002 ( 4, 3) [000002] ------------- ▌ return long $100
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckBBlist
*************** In lvaAssignFrameOffsets(PRE_REGALLOC_FRAME_LAYOUT)
Assign V00 arg0, size=8, stkOffs=-0x50
; Pre-RegAlloc local variable assignments
;
; V00 arg0 [V00,T00] ( 3, 3 ) long -> [sp+0x08]
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [sp+0x00]
*************** In Lowering
Trees before Lowering
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
( 4, 3) [000003] ------------- il_offset void IL offset: 0
N001 ( 3, 2) [000001] ------------- t1 = lclVar long V00 arg0 u:2 (last use) $80
┌──▌ t1 long
N002 ( 4, 3) [000002] ------------- ▌ return long $100
-------------------------------------------------------------------------------------------------------------------
Promoting long local V00:
lvaGrabTemp returning 2 (V02 rat0) (a long lifetime temp) called for field V00.lo (fldOffset=0x0).
lvaGrabTemp returning 3 (V03 rat1) (a long lifetime temp) called for field V00.hi (fldOffset=0x4).
lvaTable after lvaPromoteLongVars
; Pre-RegAlloc local variable assignments
;
; V00 arg0 [V00,T00] ( 3, 3 ) long -> [sp+0x08]
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [sp+0x00]
;* V02 rat0 [V02 ] ( 0, 0 ) int -> zero-ref V00.lo(offs=0x00)
;* V03 rat1 [V03 ] ( 0, 0 ) int -> zero-ref V00.hi(offs=0x04)
Decomposing TYP_LONG tree. BEFORE:
N001 ( 3, 2) [000001] ------------- t1 = lclVar long (P) V00 arg0 u:2
▌ int V00.hi (offs=0x00) -> V02 rat0
▌ int V00.hi (offs=0x04) -> V03 rat1 $80
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 4, refCntWtd = 4
New refCnts for V03: refCnt = 1, refCntWtd = 1
Decomposing TYP_LONG tree. AFTER:
N001 ( 3, 2) [000001] ------------- t1 = lclVar int V02 rat0 $80
[000006] ------------- t6 = lclVar int V03 rat1
┌──▌ t1 int
├──▌ t6 int
[000007] ------------- t7 = ▌ gt_long long
Decomposing TYP_LONG tree. BEFORE:
N001 ( 3, 2) [000001] ------------- t1 = lclVar int V02 rat0 $80
[000006] ------------- t6 = lclVar int V03 rat1
┌──▌ t1 int
├──▌ t6 int
[000007] ------------- t7 = ▌ gt_long long
┌──▌ t7 long
N002 ( 4, 3) [000002] ------------- ▌ return long $100
Decomposing TYP_LONG tree. AFTER:
N001 ( 3, 2) [000001] ------------- t1 = lclVar int V02 rat0 $80
[000006] ------------- t6 = lclVar int V03 rat1
┌──▌ t1 int
├──▌ t6 int
[000007] ------------- t7 = ▌ gt_long long
┌──▌ t7 long
N002 ( 4, 3) [000002] ------------- ▌ return long $100
lowering GT_RETURN
N002 ( 4, 3) [000002] ------------- ▌ return long $100
============Lower has completed modifying nodes, proceeding to initialize LSRA TreeNodeInfo structs...
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
( 4, 3) [000003] ------------- il_offset void IL offset: 0
N001 ( 3, 2) [000001] ------------- t1 = lclVar int V02 rat0 $80
[000006] ------------- t6 = lclVar int V03 rat1
┌──▌ t1 int
├──▌ t6 int
[000007] ------------- t7 = ▌ gt_long long
┌──▌ t7 long
N002 ( 4, 3) [000002] ------------- ▌ return long $100
-------------------------------------------------------------------------------------------------------------------
*************** In fgLocalVarLiveness()
; Pre-RegAlloc local variable assignments
;
; V00 arg0 [V00,T00] ( 4, 4 ) long -> [sp+0x08]
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [sp+0x00]
; V02 rat0 [V02 ] ( 1, 1 ) int -> [sp+0x00] V00.lo(offs=0x00)
; V03 rat1 [V03 ] ( 1, 1 ) int -> [sp+0x00] V00.hi(offs=0x04)
In fgLocalVarLivenessInit, sorting locals
refCnt table for 'LongId':
V00 arg0 [ long]: refCnt = 4, refCntWtd = 4 pref [r0-r1]
V01 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
V02 rat0 [ int]: refCnt = 1, refCntWtd = 1
V03 rat1 [ int]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={}
DEF(0)={}
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (0)={}
OUT(0)={}
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Liveness pass finished after lowering, IR:
lvasortagain = 0
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
( 4, 3) [000003] ------------- il_offset void IL offset: 0
N001 ( 3, 2) [000001] ------------- t1 = lclVar int V02 rat0 $80
[000006] ------------- t6 = lclVar int V03 rat1
┌──▌ t1 int
├──▌ t6 int
[000007] ------------- t7 = ▌ gt_long long
┌──▌ t7 long
N002 ( 4, 3) [000002] ------------- ▌ return long $100
-------------------------------------------------------------------------------------------------------------------
LSRA Block Sequence: BB01( 1 )
TreeNodeInfoInit for: N003 ( 4, 3) [000003] ------------- ▌ il_offset void IL offset: 0 REG NA
TreeNodeInfoInit for: N005 ( 3, 2) [000001] ------------- ▌ lclVar int V02 rat0 REG NA $80
TreeNodeInfoInit for: N007 (???,???) [000006] ------------- ▌ lclVar int V03 rat1 REG NA
TreeNodeInfoInit for: N009 (???,???) [000007] ------------- ▌ gt_long long REG NA
TreeNodeInfoInit for: N011 ( 4, 3) [000002] ------------- ▌ return long REG NA $100
-----------------------------
TREE NODE INFO DUMP
-----------------------------
N003 ( 4, 3) [000003] ------------- ▌ il_offset void IL offset: 0 REG NA
+<TreeNodeInfo @ 3 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N005 ( 3, 2) [000001] ------------- ▌ lclVar int V02 rat0 REG NA $80
+<TreeNodeInfo @ 5 1=0 0i 0f src=[r0] int=[allInt] dst=[allInt] I>
N007 (???,???) [000006] ------------- ▌ lclVar int V03 rat1 REG NA
+<TreeNodeInfo @ 7 1=0 0i 0f src=[r1] int=[allInt] dst=[allInt] I>
N009 (???,???) [000007] ------------- ▌ gt_long long REG NA
+<TreeNodeInfo @ 9 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N011 ( 4, 3) [000002] ------------- ▌ return long REG NA $100
+<TreeNodeInfo @ 11 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
*************** Exiting Lowering
Trees after Lowering
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
N003 ( 4, 3) [000003] ------------- il_offset void IL offset: 0 REG NA
N005 ( 3, 2) [000001] ------------- t1 = lclVar int V02 rat0 REG NA $80
N007 (???,???) [000006] ------------- t6 = lclVar int V03 rat1 REG NA
┌──▌ t1 int
├──▌ t6 int
N009 (???,???) [000007] ------------- t7 = ▌ gt_long long REG NA
┌──▌ t7 long
N011 ( 4, 3) [000002] ------------- ▌ return long REG NA $100
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In doLinearScan
Trees before linear scan register allocator (LSRA)
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
N003 ( 4, 3) [000003] ------------- il_offset void IL offset: 0 REG NA
N005 ( 3, 2) [000001] ------------- t1 = lclVar int V02 rat0 REG NA $80
N007 (???,???) [000006] ------------- t6 = lclVar int V03 rat1 REG NA
┌──▌ t1 int
├──▌ t6 int
N009 (???,???) [000007] ------------- t7 = ▌ gt_long long REG NA
┌──▌ t7 long
N011 ( 4, 3) [000002] ------------- ▌ return long REG NA $100
-------------------------------------------------------------------------------------------------------------------
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{}
{}
{}
{}
Interval 0: RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {} physReg:NA Preferences=[allInt]
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
lvaTable after IdentifyCandidates
; Pre-RegAlloc local variable assignments
;
; V00 arg0 [V00 ] ( 4, 4 ) long -> [sp+0x08]
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [sp+0x00]
; V02 rat0 [V02 ] ( 1, 1 ) int -> [sp+0x00] V00.lo(offs=0x00)
; V03 rat1 [V03 ] ( 1, 1 ) int -> [sp+0x00] V00.hi(offs=0x04)
TUPLE STYLE DUMP BEFORE LSRA
BB01 [000..002) (return), preds={} succs={}
=====
N003. il_offset IL offset: 0 REG NA
N005. t5* = V02 MEM
N007. t7 = V03 MEM
N009. gt_long
N011. return ; t5*,t7
buildIntervals second part ========
Int arg V00 in reg r0
NEW BLOCK BB01
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]>
at start of tree, map contains: { }
N003. il_offset IL offset: 0 REG NA
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { }
N005. t5* = V02 MEM
consume=0 produce=1
t5 = op
Def candidates [allInt], Use candidates [r0]
Interval 4: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #1 @6 RefTypeDef <Ivl:4> LCL_VAR BB01 regmask=[allInt]>
<RefPosition #1 @6 RefTypeDef <Ivl:4> LCL_VAR BB01 regmask=[allInt]>
at start of tree, map contains: { N005. lclVar -> (6.N005) }
N007. t7 = V03 MEM
consume=0 produce=1
t7 = op
Def candidates [allInt], Use candidates [r1]
Interval 5: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #2 @8 RefTypeDef <Ivl:5> LCL_VAR BB01 regmask=[allInt]>
<RefPosition #2 @8 RefTypeDef <Ivl:5> LCL_VAR BB01 regmask=[allInt]>
at start of tree, map contains: { N007. lclVar -> (8.N007); N005. lclVar -> (6.N005) }
N009. gt_long
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { N009. gt_long -> (6.N005, 8.N007) }
N011. return
consume=2 produce=0
op
t6 <RefPosition #3 @11 RefTypeFixedReg <Reg:r0 > BB01 regmask=[r0]>
<RefPosition #4 @11 RefTypeUse <Ivl:4> BB01 regmask=[r0] fixed>
t8 <RefPosition #5 @11 RefTypeFixedReg <Reg:r1 > BB01 regmask=[r1]>
<RefPosition #6 @11 RefTypeUse <Ivl:5> BB01 regmask=[r1] fixed>
Def candidates [allInt], Use candidates [allInt]
CALCULATING LAST USES for block 1, liveout={}
==============================
use: {}
def: {}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: (V01) RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: (V02) (struct) RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: (V03) (struct) RefPositions {} physReg:NA Preferences=[allInt]
Interval 4: RefPositions {#1@6 #4@11} physReg:NA Preferences=[r0]
Interval 5: RefPositions {#2@8 #6@11} physReg:NA Preferences=[r1]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]>
<RefPosition #1 @6 ->#4 RefTypeDef <Ivl:4> LCL_VAR BB01 regmask=[r0]>
<RefPosition #2 @8 ->#6 RefTypeDef <Ivl:5> LCL_VAR BB01 regmask=[r1]>
<RefPosition #3 @11 RefTypeFixedReg <Reg:r0 > BB01 regmask=[r0]>
<RefPosition #4 @11 RefTypeUse <Ivl:4> BB01 regmask=[r0] last fixed>
<RefPosition #5 @11 RefTypeFixedReg <Reg:r1 > BB01 regmask=[r1]>
<RefPosition #6 @11 RefTypeUse <Ivl:5> BB01 regmask=[r1] last fixed>
-----------------
-----------------
-----------------
-----------------
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [000..002) (return), preds={} succs={}
=====
N003. il_offset IL offset: 0 REG NA
N005. V02 MEM
Def:<I4>(#1)
N007. V03 MEM
Def:<I5>(#2)
N009. gt_long
N011. return
Use:<I4>(#4) Fixed:r0(#3) *
Use:<I5>(#6) Fixed:r1(#5) *
Linear scan intervals after buildIntervals:
Interval 0: (V00) RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: (V01) RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: (V02) (struct) RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: (V03) (struct) RefPositions {} physReg:NA Preferences=[allInt]
Interval 4: RefPositions {#1@6 #4@11} physReg:NA Preferences=[r0]
Interval 5: RefPositions {#2@8 #6@11} physReg:NA Preferences=[r1]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: (V01) RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: (V02) (struct) RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: (V03) (struct) RefPositions {} physReg:NA Preferences=[allInt]
Interval 4: RefPositions {#1@6 #4@11} physReg:NA Preferences=[r0]
Interval 5: RefPositions {#2@8 #6@11} physReg:NA Preferences=[r1]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]>
<RefPosition #1 @6 ->#4 RefTypeDef <Ivl:4> LCL_VAR BB01 regmask=[r0]>
<RefPosition #2 @8 ->#6 RefTypeDef <Ivl:5> LCL_VAR BB01 regmask=[r1]>
<RefPosition #3 @11 RefTypeFixedReg <Reg:r0 > BB01 regmask=[r0]>
<RefPosition #4 @11 RefTypeUse <Ivl:4> BB01 regmask=[r0] last fixed>
<RefPosition #5 @11 RefTypeFixedReg <Reg:r1 > BB01 regmask=[r1]>
<RefPosition #6 @11 RefTypeUse <Ivl:5> BB01 regmask=[r1] last fixed>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00
--- V01
--- V02
--- V03
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which
may increase during allocation, in which case additional columns will appear. Registers which are
not marked modified have ---- in their column.
─────────────────────────────┼────┤
LocRP#Name Type Action Reg │r0 │
─────────────────────────────┼────┤
│----│
0.#0 BB1 PredBB0 │----│
6.#1 I4 Def Alloc r0 │I4 a│
8.#2 I5 Def Alloc r1 │I4 a│I5 a│
11.#3 r0 Fixd Keep r0 │I4 a│I5 a│
11.#4 I4 Use * Keep r0 │I4 a│I5 a│
11.#5 r1 Fixd Keep r1 │I4 a│I5 a│
11.#6 I5 Use * Keep r1 │ │ │
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]>
<RefPosition #1 @6 ->#4 RefTypeDef <Ivl:4> LCL_VAR BB01 regmask=[r0]>
<RefPosition #2 @8 ->#6 RefTypeDef <Ivl:5> LCL_VAR BB01 regmask=[r1]>
<RefPosition #3 @11 RefTypeFixedReg <Reg:r0 > BB01 regmask=[r0]>
<RefPosition #4 @11 RefTypeUse <Ivl:4> BB01 regmask=[r0] last fixed>
<RefPosition #5 @11 RefTypeFixedReg <Reg:r1 > BB01 regmask=[r1]>
<RefPosition #6 @11 RefTypeUse <Ivl:5> BB01 regmask=[r1] last fixed>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00
--- V01
--- V02
--- V03
Active intervals at end of allocation:
------------------------
WRITING BACK ASSIGNMENTS
------------------------
BB01 [000..002) (return), preds={} succs={}
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]>
current : <RefPosition #1 @6 ->#4 RefTypeDef <Ivl:4> LCL_VAR BB01 regmask=[r0]>
N005. t5* = V02 MEM
curr = 6 mapped = 5
current : <RefPosition #2 @8 ->#6 RefTypeDef <Ivl:5> LCL_VAR BB01 regmask=[r1]>
N007. t7 = V03 MEM
curr = 8 mapped = 7
current : <RefPosition #3 @11 RefTypeFixedReg <Reg:r0 > BB01 regmask=[r0]>
current : <RefPosition #4 @11 RefTypeUse <Ivl:4> BB01 regmask=[r0] last fixed>
No tree node to write back to
current : <RefPosition #5 @11 RefTypeFixedReg <Reg:r1 > BB01 regmask=[r1]>
current : <RefPosition #6 @11 RefTypeUse <Ivl:5> BB01 regmask=[r1] last fixed>
No tree node to write back to
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {}
Has NoCritical Edges
Prior to Resolution
BB01 use def in out
{}
{}
{}
{}
Var=Reg beg of BB01: none
Var=Reg end of BB01: none
RESOLVING EDGES
Trees after linear scan register allocator (LSRA)
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..002) (return), preds={} succs={}
N003 ( 4, 3) [000003] ------------- il_offset void IL offset: 0 REG NA
N005 ( 3, 2) [000001] ------------- t1 = lclVar int V02 rat0 REG r0 $80
N007 (???,???) [000006] ------------- t6 = lclVar int V03 rat1 REG r1
┌──▌ t1 int
├──▌ t6 int
N009 (???,???) [000007] ------------- t7 = ▌ gt_long long REG NA
┌──▌ t7 long
N011 ( 4, 3) [000002] ------------- ▌ return long REG NA $100
-------------------------------------------------------------------------------------------------------------------
Final allocation
─────────────────────────────┼────┼────┤
LocRP#Name Type Action Reg │r0 │r1 │
─────────────────────────────┼────┼────┤
0.#0 BB1 PredBB0 │ │ │
6.#1 I4 Def Alloc r0 │I4 a│ │
8.#2 I5 Def Alloc r1 │I4 a│I5 a│
11.#3 r0 Fixd Keep r0 │I4 a│I5 a│
11.#4 I4 Use * Keep r0 │I4 i│I5 a│
11.#5 r1 Fixd Keep r1 │ │I5 a│
11.#6 I5 Use * Keep r1 │ │I5 i│
Recording the maximum number of concurrent spills:
<UNDEF>: 0
void: 0
bool: 0
byte: 0
ubyte: 0
char: 0
short: 0
ushort: 0
int: 0
uint: 0
long: 0
ulong: 0
float: 0
double: 0
ref: 0
byref: 0
array: 0
struct: 0
blk: 0
lclBlk: 0
pointer: 0
function: 0
unknown: 0
----------
LSRA Stats
----------
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [000..002) (return), preds={} succs={}
=====
N003. il_offset IL offset: 0 REG NA
N005. r0* = V02 MEM
N007. r1 = V03 MEM
N009. gt_long
N011. return ; r0*,r1
Var=Reg end of BB01: none
*************** In genGenerateCode()
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [000951B4] 1 1 [000..002) (return) i label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
<none>
Modified regs: [r0-r1]
Callee-saved registers pushed: 2 [r11 lr]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V00 arg0, size=8, stkOffs=-0x10
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 4, 4 ) long -> [sp+0x00]
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [sp+0x00]
; V02 rat0 [V02 ] ( 1, 1 ) int -> [sp+0x18] V00.lo(offs=0x00)
; V03 rat1 [V03 ] ( 1, 1 ) int -> [sp+0x1C] V00.hi(offs=0x04)
;
; Lcl frame size = 8
=============== Generating BB01 [000..002) (return), preds={} succs={} flags=0x00000000.40030020: i label target LIR
BB01 IN (0)={}
OUT(0)={}
Recording Var Locations at start of BB01
<none>
Liveness not changing: 00000000 {}
Live regs: (unchanged) 0000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M55297_BB01:
Label: IG02, GCvars=00000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB01, IL range [000..002)
Scope info: open scopes =
<none>
Added IP mapping: 0x0000 STACK_EMPTY (G_M55297_IG02,ins#0,ofs#0) label
Generating: N003 ( 4, 3) [000003] ------------- ▌ il_offset void IL offset: 0 REG NA
Generating: N005 ( 3, 2) [000001] ------------- ▌ lclVar int V02 rat0 REG r0 $80
IN0001: ldr r0, [sp+0x18]
Generating: N007 (???,???) [000006] ------------- ▌ lclVar int V03 rat1 REG r1
IN0002: ldr r1, [sp+0x1c]
Generating: N009 (???,???) [000007] ------------- ▌ gt_long long REG NA
Generating: N011 ( 4, 3) [000002] ------------- ▌ return long REG NA $100
Scope info: end block BB01, IL range [000..002)
Scope info: ending scope, LVnum=0 [000..002)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M55297_IG02,ins#2,ofs#4) label
Reserving epilog IG for block BB01
G_M55297_IG02: ; offs=000000H, funclet=00
*************** After placeholder IG creation
G_M55297_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=0000 {} <-- Prolog IG
G_M55297_IG02: ; offs=000000H, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
G_M55297_IG03: ; epilog placeholder, next placeholder=<END>, BB=000951B4H (BB01), epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
Liveness not changing: 00000000 {}
# compCycleEstimate = 4, compSizeEstimate = 3 Test:LongId(long):long
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 4, 4 ) long -> [sp+0x00]
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [sp+0x00]
; V02 rat0 [V02 ] ( 1, 1 ) int -> [sp+0x18] V00.lo(offs=0x00)
; V03 rat1 [V03 ] ( 1, 1 ) int -> [sp+0x1C] V00.hi(offs=0x04)
;
; Lcl frame size = 8
*************** Before prolog / epilog generation
G_M55297_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=0000 {} <-- Prolog IG
G_M55297_IG02: ; offs=000000H, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
G_M55297_IG03: ; epilog placeholder, next placeholder=<END>, BB=000951B4H (BB01), epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
Recording Var Locations at start of BB01
<none>
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M55297_IG01,ins#0,ofs#0) label
__prolog:
IN0003: push {r2,r3,r11,lr}
IN0004: add r11, sp, 8
*************** In genFnPrologCalleeRegArgs() for int regs
IN0005: str r0, [sp]
IN0006: str r1, [sp+0x04]
*************** In genEnregisterIncomingStackArgs()
G_M55297_IG01: ; offs=000000H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=00000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {}
IN0007: pop {r2,r3,r11,pc}
G_M55297_IG03: ; offs=000004H, funclet=00
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M55297_IG01: ; func=00, offs=000000H, size=000CH, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M55297_IG02: ; offs=00000CH, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
G_M55297_IG03: ; offs=000010H, size=0004H, epilog, nogc, emitadd
*************** In emitJumpDistBind()
Hot code size = 0x14 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x8)
*************** In emitEndCodeGen()
***************************************************************************
Instructions as they come out of the scheduler
G_M55297_IG01: ; func=00, offs=000000H, size=000CH, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0003: 000000 E92D 480C push {r2,r3,r11,lr}
IN0004: 000004 F10D 0B08 add r11, sp, 8
IN0005: 000008 9000 str r0, [sp]
IN0006: 00000A 9101 str r1, [sp+0x04]
G_M55297_IG02: ; func=00, offs=00000CH, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
IN0001: 00000C 9806 ldr r0, [sp+0x18]
IN0002: 00000E 9907 ldr r1, [sp+0x1c]
G_M55297_IG03: ; func=00, offs=000010H, size=0004H, epilog, nogc, emitadd
IN0007: 000010 E8BD 880C pop {r2,r3,r11,pc}
Allocated method code size = 20 , actual size = 20
*************** After end code gen, before unwindEmit()
G_M55297_IG01: ; func=00, offs=000000H, size=000CH, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0003: 000000 push {r2,r3,r11,lr}
IN0004: 000004 add r11, sp, 8
IN0005: 000008 str r0, [sp]
IN0006: 00000A str r1, [sp+0x04]
G_M55297_IG02: ; offs=00000CH, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
IN0001: 00000C ldr r0, [sp+0x18]
IN0002: 00000E ldr r1, [sp+0x1c]
G_M55297_IG03: ; offs=000010H, size=0004H, epilog, nogc, emitadd
IN0007: 000010 pop {r2,r3,r11,pc}
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x000014 (not in unwind data)
Code Words : 1
Epilog Count : 0
F bit : 0
E bit : 1
X bit : 0
Vers : 0
Function Length : 10 (0x0000a) Actual length = 20 (0x000014)
--- One epilog, unwind codes at 0
---- Unwind codes ----
---- Epilog start at index 0 ----
A8 0C pop {r2,r3,r11,lr} ; opsize 32
FF end
FF end
allocUnwindInfo(pHotCode=0xB510F460, pColdCode=0x00000000, startOffset=0x0, endOffset=0x14, unwindSize=0x8, pUnwindBlock=0x0009608A, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 3
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x0000000C ( STACK_EMPTY )
IL offs EPILOG : 0x00000010 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 1
*************** Variable debug info
1 vars
0( UNKNOWN) : From 00000000h to 0000000Ch, in r0
*************** In gcInfoBlockHdrSave()
Set code length to 20.
Set ReturnKind to Scalar.
Set stack base register to r11.
Set Outgoing stack arg area size to 0.
Defining 0 call sites:
Allocations for Test:LongId(long):long (MethodHash=0f9627fe)
count: 183, size: 22428, max = 2560
allocateMemory: 65536, nraUsed: 34056
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 0 | 0.00%
ASTNode | 816 | 3.64%
InstDesc | 2280 | 10.17%
ImpStack | 0 | 0.00%
BasicBlock | 388 | 1.73%
fgArgInfo | 0 | 0.00%
fgArgInfoPtrArr | 0 | 0.00%
FlowList | 0 | 0.00%
TreeStatementList | 0 | 0.00%
SiScope | 44 | 0.20%
FlatFPStateX87 | 0 | 0.00%
DominatorMemory | 32 | 0.14%
LSRA | 2716 | 12.11%
LSRA_Interval | 336 | 1.50%
LSRA_RefPosition | 392 | 1.75%
Reachability | 8 | 0.04%
SSA | 180 | 0.80%
ValueNumber | 4140 | 18.46%
LvaTable | 1560 | 6.96%
UnwindInfo | 16 | 0.07%
hashBv | 20 | 0.09%
bitset | 64 | 0.29%
FixedBitVect | 0 | 0.00%
AsIAllocator | 5916 | 26.38%
IndirAssignMap | 0 | 0.00%
FieldSeqStore | 0 | 0.00%
ZeroOffsetFieldMap | 0 | 0.00%
ArrayInfoMap | 0 | 0.00%
HeapPhiArg | 0 | 0.00%
CSE | 512 | 2.28%
GC | 912 | 4.07%
CorSig | 0 | 0.00%
Inlining | 56 | 0.25%
ArrayStack | 0 | 0.00%
DebugInfo | 88 | 0.39%
DebugOnly | 1764 | 7.87%
Codegen | 0 | 0.00%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 188 | 0.84%
****** DONE compiling Test:LongId(long):long
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