mtklein

#include <stdio.h>
#include <stdlib.h>
#include <assert.h>

#define NOINLINE __attribute__((noinline))

NOINLINE static int paeth(int a, int b, int c) {
    int p = a+b-c,
        pa = abs(p-a),
        pb = abs(p-b),

mtklein

// srcover.h
#include <stdint.h>
void srcover_bgra_8888(uint32_t*, const uint32_t*, int);

// srcover.c
static uint32_t srcover1_bgra_8888(uint32_t dst, uint32_t src) {
    uint8_t da = dst >> 24,
            dr = dst >> 16,
            dg = dst >>  8,
            db = dst >>  0;

mtklein

# Boilerplate.
cmake_minimum_required (VERSION 3.1)   # First version with CMAKE_CXX_STANDARD.
project (skimake)
set (CMAKE_CXX_STANDARD 11)

# Default to Release mode.  We're mainly targeting Skia users, not Skia developers.
if (NOT CMAKE_BUILD_TYPE)
    set (CMAKE_BUILD_TYPE Release)
endif ()

mtklein

Sk4x: native 4x32-bit SIMD vector types for Skia

SIMD == single-instruction multiple-data
    Sk4f ~=  vec4, __m128 , float32x4_t, float[4]
    Sk4i ~= ivec4, __m128i,   int32x4_t,   int[4]

Compile time choice, with a serial implementation as fallback.
Most Sk4x methods compile to a single SIMD instruction.

Instruction sets we normally have guaranteed today:

mtklein

#!/bin/sh

set -e

BRANCH=$(git branch | grep \* | cut -d" "  -f 2)
CLEAN=${CLEAN-clean}
SAMPLES=100

if [ $BRANCH == $CLEAN ]; then
    echo "Comparing $BRANCH to itself."

mtklein

diff --git a/src/core/SkBlitter.cpp b/src/core/SkBlitter.cpp
index 7012cf3..1ab8d15 100644
--- a/src/core/SkBlitter.cpp
+++ b/src/core/SkBlitter.cpp
@@ -33,11 +33,31 @@ void SkBlitter::blitH(int x, int y, int width) {
     SkDEBUGFAIL("unimplemented");
 }
 
-void SkBlitter::blitAntiH(int x, int y, const SkAlpha antialias[],
-                          const int16_t runs[]) {

mtklein

00096d14 <_ZN9arch_neonL8memset_TIN6simdpp9arch_neon8uint32x4EjEEvPT0_S4_j>:
   96d14:	e92d 0ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp}
   96d18:	2a03      	cmp	r2, #3
   96d1a:	b08c      	sub	sp, #48	; 0x30
   96d1c:	4607      	mov	r7, r0
   96d1e:	9103      	str	r1, [sp, #12]
   96d20:	9201      	str	r2, [sp, #4]
   96d22:	f240 80c6 	bls.w	96eb2 <_ZN9arch_neonL8memset_TIN6simdpp9arch_neon8uint32x4EjEEvPT0_S4_j+0x19e>
   96d26:	0702      	lsls	r2, r0, #28
   96d28:	4603      	mov	r3, r0