Lチカ with CycloneIV @ FPGAスタートアップ講座第5回

sample001.v

//module name must be set the same one as Project Name.
//module name must be set with alphabet, not only number.
module sample (out,clk);

//signal input and output of module
input clk;
output out;
//set 25bit variable. [24][23][22]...[3][2][1][0] as "count"
reg[24:0]count;

assign out = count[24];

//posedge -> positive signal
//negedge -> negative signal
always @(posedge(clk)) begin
	count = count + 1;
end

//50MHz -> 20ns / count
//2^25 = 3.4*10^7 times counts.
// 3.4*10^7 * 20ns = 0.67 s ??

endmodule

sample002.v

module sample (led1,led2,clk,btn);

input clk;
input btn;
output led1;
output led2;
reg[24:0]count;

assign led1 = count[24];
assign led2 = btn;

always @(posedge(clk)) begin
	if(btn == 0) count <= count + 1;
end

endmodule

verilogHDLコードをコンパイル→PinPlannnerで各inputとoutputをassign→pinanalysis

Lチカできなかったのにコメント消したら動いたキレそう