omap5-emif.c

struct __attribute__((packed,aligned(4))) Ratios11 {
	u32 d0r0 : 11;
	u32 d0r1 : 11;
	u32 d1r0 : 11;
	u32 d1r1 : 11;
	u32 d2r0 : 11;
	u32 d2r1 : 11;
	u32 d3r0 : 11;
	u32 d3r1 : 11;
};

struct __attribute__((packed,aligned(4))) Ratios10 {
	u32 d0r0 : 10;
	u32 d0r1 : 10;
	u32 d1r0 : 10;
	u32 d1r1 : 10;
	u32 d2r0 : 10;
	u32 d2r1 : 10;
	u32 d3r0 : 10;
	u32 d3r1 : 10;
};

struct PhyStatus {
/*140*/	struct {
		u32 c01	: 1;
		u32 c2	: 1;
		u32 d0	: 1;
		u32 d1	: 1;
		u32 d2	: 1;
		u32 d3	: 1;
	} locked;

	// <undocumented>
	// <guess quality="decent">
/*144*/	struct __attribute__((packed,aligned(4))) {
		u32 c01 : 9;
		u32 c2 : 9;
		u32    : 0;

		u32 d0 : 9;
		u32 d1 : 9;
		u32 d2 : 9;
		u32 d3 : 9;
	} dll_value;
	/* </guess> */
/*150*/	u32 status_5;
/*154*/	u32 status_6;
/*158*/	u32 status_7;
	/* </undocumented> */

/*15c*/	Ratios10 rd_dqs;  /* status  8-10 ~ control  5- 7 */
/*168*/	Ratios11 fifo_we; /* status 11-13 ~ control  2- 4 */
/*174*/	Ratios10 wr_data; /* status 14-16 ~ control  8-10 */
/*180*/	Ratios10 wr_dqs;  /* status 17-19 ~ control 11-13 */

/*18c*/	struct __attribute__((packed,aligned(4))) {
		/* read capture fifo reset error counters */
		u32 fifo_rst_d0 : 4;
		u32 fifo_rst_d1 : 4;
		u32 fifo_rst_d2 : 4;
		u32 fifo_rst_d3 : 4;
		/* sticky errors */
		u32 dll_d0  : 1;
		u32 dll_d1  : 1;
		u32 dll_d2  : 1;
		u32 dll_d3  : 1;
		u32 dll_c01 : 1;
		u32 dll_c2  : 1;
		u32 fifo_we_misalign	: 4;
		u32 rdlvl_fail		: 4;  // read data eye training error
		u32 wrlvl_fail		: 4;  // write leveling error
		u32 gatelvl_fail	: 4;  // read dqs gate training error
	} err;
};

// NOTE: this is not a direct map of the phy control registers, instead this
// and its shadow copy are interleaved every 4 bytes.
//
// The offsets listed below are the real register offsets however.
//
struct PhyControl {
/*200*/	struct {
		u32 c0 : 10;
		u32 c1 : 10;
		u32 c2 : 10;
	} cmd;

/*208*/	Ratios11 fifo_we;	/* control  2- 4 ~ status 11-13 */
/*220*/	Ratios10 rd_dqs;	/* control  5- 7 ~ status  8-10 */
/*238*/	Ratios10 wr_data;	/* control  8-10 ~ status 14-16 */
/*250*/	Ratios10 wr_dqs;	/* control 11-13 ~ status 17-19 */

	// set raw delays (dll unlocked mode), broadcast to all phys/ranks.
	// max value is 0x1ff ?
/*268*/	struct __attribute__((packed,aligned(4))) {
		uint cmd	: 12;
		uint fifo_we	: 12;
		uint rd_dqs	: 12;
		uint wr_data	: 12;
		uint wr_dqs	: 12;
	} delay;

	// "Offset value from write dqs to write dq during write leveling."
	// "Don't care in DDR3 mode due to the leveling."
/*278*/	struct {
		uint d0 : 7;
		uint d1 : 7;
		uint d2 : 7;
		uint d3 : 7;
	} dq_offset;

/*280*/	struct {
		bool use_rank0_delays	: 1;  // ( for all ranks)
		bool gatelvl_init_mode	: 1;
	};

	// "The recommended setting is half cycle less than total delay
	// required on fifo_we_in to align to DQS at PHY."
/*288*/	Ratios11 gatelvl_init;
	// "The recommended setting is half cycle less than total skew between
	// CLK and DQS at the DDR.
/*2a0*/	Ratios10 wrlvl_init;

/*2b8*/	struct {
		uint gatelvl	: 4;
		uint wrlvl	: 4;

		bool clear_fifo_we_misalign	: 1;
		bool clear_phy_mdll_unlock_err	: 1;
		bool clear_read_fifo_errors	: 1;
	};
};