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mwkmwkmwk/bug2824.ys

Created June 11, 2021 10:16
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bug2824.ys
read_verilog -icells << EOT
module top(input I, output O);
$pmux #(.WIDTH(1), .S_WIDTH(2)) m (.S({I, 1'b0}), .A(1'b0), .B({I, 1'b0}), .Y(O));
endmodule
EOT
equiv_opt -assert opt_muxtree
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