dffes.v

module \$dffes (CLK, RST, EN, D, Q); 

parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1; 
parameter RST_POLARITY = 1'b1;
parameter RST_VALUE = 0;
          
input CLK, RST, EN;           
input [WIDTH-1:0] D;     
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_rst = RST == RST_POLARITY;                  
                                                     
always @(posedge pos_clk) begin
  if (EN == EN_POLARITY) begin
    if (pos_rst)
      Q <= RST_VALUE;
    else
      Q <= D;
  end
end

endmodule