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mwrnd/MNV303212A-ADLT_mlxreg_Register_Listing.txt

Last active August 24, 2023 03:50
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MNV303212A-ADLT mlxreg Register Listing
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MNV303212A-ADLT_mlxreg_Register_Listing.txt
sudo mst start
sudo mst status
sudo flint -d /dev/mst/mt4119_pciconf0 q
sudo ./mlxup --version
sudo ./mlxup -d /dev/mst/mt4119_pciconf0
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_regs | cut -d " " -f 1 | grep "^[A-Z]" | grep -v "Available" | xargs -t -L 1 -I{} sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg {}
sudo flint -d /dev/mst/mt4119_pciconf0 q
Image type: FS4
FW Version: 16.28.2006
FW Release Date: 15.9.2020
Product Version: 16.28.2006
Rom Info: type=UEFI version=14.21.17 cpu=AMD64
type=PXE version=3.6.102 cpu=AMD64
Description: UID GuidsNumber
Base GUID: c0dec0dec0dec0de 12
Orig Base GUID: N/A 12
Base MAC: c0dec0dec0de 12
Orig Base MAC: N/A 12
Image VSD: N/A
Device VSD: N/A
PSID: MT_0000000158
Security Attributes: N/A
sudo ./mlxup --version
SelfExtractor 1.0, mft 4.15.2-5, built on Oct 19 2020, 09:50:05. Git SHA Hash: 761328c
mlxup 1.0, mft 4.15.2-5, built on Oct 19 2020, 09:53:16. Git SHA Hash: 761328c
sudo ./mlxup -d /dev/mst/mt4119_pciconf0
Querying Mellanox devices firmware ...
Device #1:
----------
Device Type: ConnectX5
Part Number: MNV303212A-ADL_Ax_Bx
Description: Innova-2 Flex for Application Acceleration; ConnectX-5 Eth Adapter dual Port SFP 25GbE; Xilinx KU15P; PCI4.0 x8; HHHL; active cooling tall bracket; ROHS R6
PSID: MT_0000000158
PCI Device Name: /dev/mst/mt4119_pciconf0
Base GUID: c0dec0dec0dec0de
Base MAC: c0dec0dec0de
Versions: Current Available
FW 16.28.2006 16.28.2006
PXE 3.6.0102 3.6.0102
UEFI 14.21.0017 14.21.0017
Status: Up to date
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CHLMM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================
switch_prio | 0x00000000 | 8 | 4 | INDEX
hlt_table_pointer | 0x00000010 | 0 | 8 | RW
==============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CHLTM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
traffic_class | 0x00000004 | 0 | 8 | INDEX
hlt_table_pointer | 0x00000010 | 0 | 8 | RW
==============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CHLTR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
hlt_table_index | 0x00000000 | 0 | 8 | INDEX
high_latency_thr | 0x00000008 | 0 | 20 | RW
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CNCT
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
prio | 0x00000000 | 8 | 3 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
re | 0x00000004 | 14 | 1 | WO
ee | 0x00000004 | 15 | 1 | WO
r | 0x00000004 | 30 | 1 | RW
e | 0x00000004 | 31 | 1 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CNMC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================
prio | 0x00000000 | 8 | 3 | RW
=================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CPCS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================================
tclass | 0x00000000 | 8 | 3 | INDEX
cpmhoe | 0x00000004 | 28 | 1 | WO
cpsbe | 0x00000004 | 29 | 1 | WO
log2_cpwe | 0x00000004 | 30 | 1 | WO
cpqspe | 0x00000004 | 31 | 1 | WO
cpqsp | 0x00000008 | 0 | 32 | RW
log2_cpw | 0x0000000c | 0 | 32 | RW
cp_sample_base | 0x00000010 | 0 | 32 | RW
cp_min_header_octets | 0x00000014 | 0 | 32 | RW
=================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CPID
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
prio | 0x00000000 | 8 | 3 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
cpid_high | 0x00000004 | 0 | 32 | RO
cpid_low | 0x00000008 | 0 | 32 | RO
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CPQE
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
============================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
marking_percent | 0x00000008 | 16 | 7 | RW
============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CWCAM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
======================================================================================
access_reg_group | 0x00000000 | 0 | 8 | INDEX
feature_group | 0x00000000 | 16 | 8 | INDEX
cw_access_reg_cap_mask[0] | 0x00000008 | 0 | 32 | RO
cw_access_reg_cap_mask[1] | 0x0000000c | 0 | 32 | RO
cw_access_reg_cap_mask[2] | 0x00000010 | 0 | 32 | RO
cw_access_reg_cap_mask[3] | 0x00000014 | 0 | 32 | RO
feature_cap_mask[0] | 0x00000028 | 0 | 32 | RO
feature_cap_mask[1] | 0x0000002c | 0 | 32 | RO
feature_cap_mask[2] | 0x00000030 | 0 | 32 | RO
feature_cap_mask[3] | 0x00000034 | 0 | 32 | RO
======================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CWGCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
aqs_time | 0x00000000 | 0 | 8 | RW
aqs_weight | 0x00000000 | 8 | 4 | RW
scd | 0x00000000 | 16 | 1 | RW
en | 0x00000000 | 24 | 4 | RW
cece | 0x00000004 | 0 | 1 | RW
mece | 0x00000004 | 1 | 1 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CWPP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
pool | 0x00000000 | 0 | 4 | INDEX
profile1_min | 0x00000008 | 0 | 20 | RW
profile1_max | 0x0000000c | 0 | 20 | RW
profile1_percent | 0x0000000c | 24 | 7 | RW
profile2_min | 0x00000010 | 0 | 20 | RW
profile2_max | 0x00000014 | 0 | 20 | RW
profile2_percent | 0x00000014 | 24 | 7 | RW
profile3_min | 0x00000018 | 0 | 20 | RW
profile3_max | 0x0000001c | 0 | 20 | RW
profile3_percent | 0x0000001c | 24 | 7 | RW
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CWTP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
traffic_class | 0x00000020 | 0 | 8 | INDEX
mode | 0x00000024 | 24 | 1 | RW
profile1_min | 0x00000028 | 0 | 20 | RW
profile1_max | 0x0000002c | 0 | 20 | RW
profile1_percent | 0x0000002c | 24 | 7 | RW
profile2_min | 0x00000030 | 0 | 20 | RW
profile2_max | 0x00000034 | 0 | 20 | RW
profile2_percent | 0x00000034 | 24 | 7 | RW
profile3_min | 0x00000038 | 0 | 20 | RW
profile3_max | 0x0000003c | 0 | 20 | RW
profile3_percent | 0x0000003c | 24 | 7 | RW
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg CWTPM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==========================================================================
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
traffic_class | 0x00000020 | 0 | 8 | INDEX
ee | 0x00000024 | 0 | 1 | RW
ew | 0x00000024 | 1 | 1 | RW
==========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg DCBX_APPLICATION
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=========================================================================
port_number | 0x00000000 | 16 | 8 | INDEX
num_app_prio | 0x00000004 | 0 | 6 | RO
protocol_id | 0x00000010 | 0 | 16 | RO
sel | 0x00000010 | 16 | 3 | RO
priority | 0x00000010 | 21 | 3 | RO
=========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg DCBX_PARAM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================================
max_application_table_size | 0x00000000 | 0 | 6 | RO
port_number | 0x00000000 | 16 | 8 | INDEX
dcbx_standby_cap | 0x00000000 | 29 | 1 | RO
dcbx_ieee_cap | 0x00000000 | 30 | 1 | RO
dcbx_cee_cap | 0x00000000 | 31 | 1 | RO
version_admin | 0x00000004 | 0 | 3 | RW
version_oper | 0x00000004 | 8 | 3 | RO
num_of_tc_admin | 0x00000008 | 0 | 4 | RW
num_of_tc_oper | 0x00000008 | 8 | 4 | RO
pfc_cap_admin | 0x00000008 | 16 | 4 | RW
pfc_cap_oper | 0x00000008 | 24 | 4 | RO
willing_admin | 0x00000008 | 31 | 1 | RW
remote_num_of_tc | 0x0000000c | 0 | 4 | RO
remote_pfc_cap | 0x0000000c | 24 | 4 | RO
remote_willing | 0x0000000c | 31 | 1 | RO
error | 0x00000010 | 0 | 8 | RO
=======================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg FORE
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
============================================================================
fan_under_limit | 0x00000000 | 16 | 10 | RO
fan_over_limit | 0x00000004 | 16 | 10 | RO
============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg HCA_CAP_ENCAP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================
cmd_data_offset | 0x00000000 | 16 | 16 | INDEX
cmd_data_mask[0] | 0x00000010 | 0 | 32 | INDEX
cmd_data_mask[1] | 0x00000014 | 0 | 32 | INDEX
cmd_data_mask[2] | 0x00000018 | 0 | 32 | INDEX
cmd_data_mask[3] | 0x0000001c | 0 | 32 | INDEX
cmd_data_value[0] | 0x00000020 | 0 | 32 | RW
cmd_data_value[1] | 0x00000024 | 0 | 32 | RW
cmd_data_value[2] | 0x00000028 | 0 | 32 | RW
cmd_data_value[3] | 0x0000002c | 0 | 32 | RW
cmd_header[0] | 0x00000040 | 0 | 32 | RW
cmd_header[1] | 0x00000044 | 0 | 32 | RW
cmd_header[2] | 0x00000048 | 0 | 32 | RW
cmd_header[3] | 0x0000004c | 0 | 32 | RW
==============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg HOST_ENDIANNESS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================
he | 0x00000000 | 31 | 1 | RW
===============================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MCC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================================
instruction | 0x00000000 | 0 | 8 | RW
activation_delay_sec | 0x00000000 | 8 | 8 | RW
time_elapsed_since_last_cmd | 0x00000000 | 16 | 12 | RO
component_index | 0x00000004 | 0 | 16 | INDEX
update_handle | 0x00000008 | 0 | 24 | RW
auto_update | 0x00000008 | 31 | 1 | WO
control_state | 0x0000000c | 0 | 4 | RO
error_code | 0x0000000c | 8 | 8 | RO
control_progress | 0x0000000c | 16 | 7 | RO
handle_owner_host_id | 0x0000000c | 24 | 4 | RO
handle_owner_type | 0x0000000c | 28 | 4 | RO
component_size | 0x00000010 | 0 | 32 | WO
device_type | 0x00000014 | 0 | 8 | INDEX
device_index | 0x00000014 | 16 | 12 | INDEX
device_index_size | 0x00000018 | 0 | 12 | RW
rejected_device_index | 0x00000018 | 16 | 12 | RO
========================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MCDA
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==========================================================================
update_handle | 0x00000000 | 0 | 24 | RW
offset | 0x00000004 | 0 | 32 | RW
size | 0x00000008 | 0 | 16 | RW
data[0] | 0x00000010 | 0 | 32 | RW
data[1] | 0x00000014 | 0 | 32 | RW
data[2] | 0x00000018 | 0 | 32 | RW
data[3] | 0x0000001c | 0 | 32 | RW
data[4] | 0x00000020 | 0 | 32 | RW
data[5] | 0x00000024 | 0 | 32 | RW
data[6] | 0x00000028 | 0 | 32 | RW
data[7] | 0x0000002c | 0 | 32 | RW
data[8] | 0x00000030 | 0 | 32 | RW
data[9] | 0x00000034 | 0 | 32 | RW
data[10] | 0x00000038 | 0 | 32 | RW
data[11] | 0x0000003c | 0 | 32 | RW
data[12] | 0x00000040 | 0 | 32 | RW
data[13] | 0x00000044 | 0 | 32 | RW
data[14] | 0x00000048 | 0 | 32 | RW
data[15] | 0x0000004c | 0 | 32 | RW
data[16] | 0x00000050 | 0 | 32 | RW
data[17] | 0x00000054 | 0 | 32 | RW
data[18] | 0x00000058 | 0 | 32 | RW
data[19] | 0x0000005c | 0 | 32 | RW
data[20] | 0x00000060 | 0 | 32 | RW
data[21] | 0x00000064 | 0 | 32 | RW
data[22] | 0x00000068 | 0 | 32 | RW
data[23] | 0x0000006c | 0 | 32 | RW
data[24] | 0x00000070 | 0 | 32 | RW
data[25] | 0x00000074 | 0 | 32 | RW
data[26] | 0x00000078 | 0 | 32 | RW
data[27] | 0x0000007c | 0 | 32 | RW
data[28] | 0x00000080 | 0 | 32 | RW
data[29] | 0x00000084 | 0 | 32 | RW
data[30] | 0x00000088 | 0 | 32 | RW
data[31] | 0x0000008c | 0 | 32 | RW
==========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MCDD
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================================
update_handle | 0x00000000 | 0 | 24 | RW
offset | 0x00000004 | 0 | 32 | RW
size | 0x00000008 | 0 | 16 | RW
data_page_phys_addr_msb | 0x00000010 | 0 | 32 | RW
data_page_phys_addr_lsb | 0x00000014 | 0 | 32 | RW
mailbox_page_phys_addr_msb | 0x00000018 | 0 | 32 | RW
mailbox_page_phys_addr_lsb | 0x0000001c | 0 | 32 | RW
=======================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MCIA
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================================
status | 0x00000000 | 0 | 8 | RO
slot_index | 0x00000000 | 12 | 4 | INDEX
module | 0x00000000 | 16 | 8 | INDEX
l | 0x00000000 | 31 | 1 | RW
device_address | 0x00000004 | 0 | 16 | INDEX
page_number | 0x00000004 | 16 | 8 | INDEX
i2c_device_address | 0x00000004 | 24 | 8 | INDEX
size | 0x00000008 | 0 | 16 | INDEX
bank_number | 0x00000008 | 16 | 8 | INDEX
dword[0] | 0x00000010 | 0 | 32 | RW
dword[1] | 0x00000014 | 0 | 32 | RW
dword[2] | 0x00000018 | 0 | 32 | RW
dword[3] | 0x0000001c | 0 | 32 | RW
dword[4] | 0x00000020 | 0 | 32 | RW
dword[5] | 0x00000024 | 0 | 32 | RW
dword[6] | 0x00000028 | 0 | 32 | RW
dword[7] | 0x0000002c | 0 | 32 | RW
dword[8] | 0x00000030 | 0 | 32 | RW
dword[9] | 0x00000034 | 0 | 32 | RW
dword[10] | 0x00000038 | 0 | 32 | RW
dword[11] | 0x0000003c | 0 | 32 | RW
dword[12] | 0x00000040 | 0 | 32 | RW
dword[13] | 0x00000044 | 0 | 32 | RW
dword[14] | 0x00000048 | 0 | 32 | RW
dword[15] | 0x0000004c | 0 | 32 | RW
dword[16] | 0x00000050 | 0 | 32 | RW
dword[17] | 0x00000054 | 0 | 32 | RW
dword[18] | 0x00000058 | 0 | 32 | RW
dword[19] | 0x0000005c | 0 | 32 | RW
dword[20] | 0x00000060 | 0 | 32 | RW
dword[21] | 0x00000064 | 0 | 32 | RW
dword[22] | 0x00000068 | 0 | 32 | RW
dword[23] | 0x0000006c | 0 | 32 | RW
dword[24] | 0x00000070 | 0 | 32 | RW
dword[25] | 0x00000074 | 0 | 32 | RW
dword[26] | 0x00000078 | 0 | 32 | RW
dword[27] | 0x0000007c | 0 | 32 | RW
dword[28] | 0x00000080 | 0 | 32 | RW
dword[29] | 0x00000084 | 0 | 32 | RW
dword[30] | 0x00000088 | 0 | 32 | RW
dword[31] | 0x0000008c | 0 | 32 | RW
===============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MCION
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================================
slot_index | 0x00000000 | 12 | 4 | INDEX
module | 0x00000000 | 16 | 8 | INDEX
module_status_bits | 0x00000004 | 0 | 16 | RO
===============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MCPP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===================================================================================
enoc | 0x00000000 | 30 | 1 | RW
ent | 0x00000000 | 31 | 1 | RW
hysteresis_temperature | 0x00000004 | 0 | 8 | RW
warning_temperature | 0x00000004 | 16 | 8 | RW
wsoc | 0x00000008 | 30 | 1 | RW
wst | 0x00000008 | 31 | 1 | RW
yellow_state_rate | 0x0000000c | 0 | 8 | RW
red_state_rate | 0x0000000c | 16 | 8 | RW
===================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MCQI
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==========================================================================================
component_index | 0x00000000 | 0 | 16 | INDEX
device_index | 0x00000000 | 16 | 12 | INDEX
read_pending_component | 0x00000000 | 31 | 1 | INDEX
device_type | 0x00000004 | 0 | 8 | INDEX
info_type | 0x00000008 | 0 | 5 | RW
info_size | 0x0000000c | 0 | 32 | RO
offset | 0x00000010 | 0 | 32 | RW
data_size | 0x00000014 | 0 | 16 | RW
supported_info_bitmask | 0x00000018 | 0 | 32 | RO
component_size | 0x0000001c | 0 | 32 | RO
max_component_size | 0x00000020 | 0 | 32 | RO
mcda_max_write_size | 0x00000024 | 0 | 16 | RO
log_mcda_word_size | 0x00000024 | 28 | 4 | RO
match_base_guid_mac | 0x00000028 | 26 | 1 | RW
check_user_timestamp | 0x00000028 | 27 | 1 | RW
match_psid | 0x00000028 | 28 | 1 | RW
match_chip_id | 0x00000028 | 29 | 1 | RW
rd_en | 0x00000028 | 31 | 1 | RO
version_string_length | 0x00000018 | 0 | 8 | RW
user_defined_time_valid | 0x00000018 | 28 | 1 | RW
build_time_valid | 0x00000018 | 29 | 1 | RW
version | 0x0000001c | 0 | 32 | RW
hi | 0x00000020 | 0 | 32 | RW
lo | 0x00000024 | 0 | 32 | RW
hi | 0x00000028 | 0 | 32 | RW
lo | 0x0000002c | 0 | 32 | RW
build_tool_version | 0x00000030 | 0 | 32 | RW
version_string[3] | 0x00000038 | 0 | 8 | RW
version_string[2] | 0x00000038 | 8 | 8 | RW
version_string[1] | 0x00000038 | 16 | 8 | RW
version_string[0] | 0x00000038 | 24 | 8 | RW
version_string[7] | 0x0000003c | 0 | 8 | RW
version_string[6] | 0x0000003c | 8 | 8 | RW
version_string[5] | 0x0000003c | 16 | 8 | RW
version_string[4] | 0x0000003c | 24 | 8 | RW
version_string[11] | 0x00000040 | 0 | 8 | RW
version_string[10] | 0x00000040 | 8 | 8 | RW
version_string[9] | 0x00000040 | 16 | 8 | RW
version_string[8] | 0x00000040 | 24 | 8 | RW
version_string[15] | 0x00000044 | 0 | 8 | RW
version_string[14] | 0x00000044 | 8 | 8 | RW
version_string[13] | 0x00000044 | 16 | 8 | RW
version_string[12] | 0x00000044 | 24 | 8 | RW
version_string[19] | 0x00000048 | 0 | 8 | RW
version_string[18] | 0x00000048 | 8 | 8 | RW
version_string[17] | 0x00000048 | 16 | 8 | RW
version_string[16] | 0x00000048 | 24 | 8 | RW
version_string[23] | 0x0000004c | 0 | 8 | RW
version_string[22] | 0x0000004c | 8 | 8 | RW
version_string[21] | 0x0000004c | 16 | 8 | RW
version_string[20] | 0x0000004c | 24 | 8 | RW
version_string[27] | 0x00000050 | 0 | 8 | RW
version_string[26] | 0x00000050 | 8 | 8 | RW
version_string[25] | 0x00000050 | 16 | 8 | RW
version_string[24] | 0x00000050 | 24 | 8 | RW
version_string[31] | 0x00000054 | 0 | 8 | RW
version_string[30] | 0x00000054 | 8 | 8 | RW
version_string[29] | 0x00000054 | 16 | 8 | RW
version_string[28] | 0x00000054 | 24 | 8 | RW
version_string[35] | 0x00000058 | 0 | 8 | RW
version_string[34] | 0x00000058 | 8 | 8 | RW
version_string[33] | 0x00000058 | 16 | 8 | RW
version_string[32] | 0x00000058 | 24 | 8 | RW
version_string[39] | 0x0000005c | 0 | 8 | RW
version_string[38] | 0x0000005c | 8 | 8 | RW
version_string[37] | 0x0000005c | 16 | 8 | RW
version_string[36] | 0x0000005c | 24 | 8 | RW
version_string[43] | 0x00000060 | 0 | 8 | RW
version_string[42] | 0x00000060 | 8 | 8 | RW
version_string[41] | 0x00000060 | 16 | 8 | RW
version_string[40] | 0x00000060 | 24 | 8 | RW
version_string[47] | 0x00000064 | 0 | 8 | RW
version_string[46] | 0x00000064 | 8 | 8 | RW
version_string[45] | 0x00000064 | 16 | 8 | RW
version_string[44] | 0x00000064 | 24 | 8 | RW
version_string[51] | 0x00000068 | 0 | 8 | RW
version_string[50] | 0x00000068 | 8 | 8 | RW
version_string[49] | 0x00000068 | 16 | 8 | RW
version_string[48] | 0x00000068 | 24 | 8 | RW
version_string[55] | 0x0000006c | 0 | 8 | RW
version_string[54] | 0x0000006c | 8 | 8 | RW
version_string[53] | 0x0000006c | 16 | 8 | RW
version_string[52] | 0x0000006c | 24 | 8 | RW
version_string[59] | 0x00000070 | 0 | 8 | RW
version_string[58] | 0x00000070 | 8 | 8 | RW
version_string[57] | 0x00000070 | 16 | 8 | RW
version_string[56] | 0x00000070 | 24 | 8 | RW
version_string[63] | 0x00000074 | 0 | 8 | RW
version_string[62] | 0x00000074 | 8 | 8 | RW
version_string[61] | 0x00000074 | 16 | 8 | RW
version_string[60] | 0x00000074 | 24 | 8 | RW
version_string[67] | 0x00000078 | 0 | 8 | RW
version_string[66] | 0x00000078 | 8 | 8 | RW
version_string[65] | 0x00000078 | 16 | 8 | RW
version_string[64] | 0x00000078 | 24 | 8 | RW
version_string[71] | 0x0000007c | 0 | 8 | RW
version_string[70] | 0x0000007c | 8 | 8 | RW
version_string[69] | 0x0000007c | 16 | 8 | RW
version_string[68] | 0x0000007c | 24 | 8 | RW
version_string[75] | 0x00000080 | 0 | 8 | RW
version_string[74] | 0x00000080 | 8 | 8 | RW
version_string[73] | 0x00000080 | 16 | 8 | RW
version_string[72] | 0x00000080 | 24 | 8 | RW
version_string[79] | 0x00000084 | 0 | 8 | RW
version_string[78] | 0x00000084 | 8 | 8 | RW
version_string[77] | 0x00000084 | 16 | 8 | RW
version_string[76] | 0x00000084 | 24 | 8 | RW
version_string[83] | 0x00000088 | 0 | 8 | RW
version_string[82] | 0x00000088 | 8 | 8 | RW
version_string[81] | 0x00000088 | 16 | 8 | RW
version_string[80] | 0x00000088 | 24 | 8 | RW
version_string[87] | 0x0000008c | 0 | 8 | RW
version_string[86] | 0x0000008c | 8 | 8 | RW
version_string[85] | 0x0000008c | 16 | 8 | RW
version_string[84] | 0x0000008c | 24 | 8 | RW
version_string[91] | 0x00000090 | 0 | 8 | RW
version_string[90] | 0x00000090 | 8 | 8 | RW
version_string[89] | 0x00000090 | 16 | 8 | RW
version_string[88] | 0x00000090 | 24 | 8 | RW
all_hosts_sync | 0x00000018 | 0 | 1 | RO
auto_activate | 0x00000018 | 1 | 1 | RO
pending_fw_reset | 0x00000018 | 2 | 1 | RO
pending_server_reboot | 0x00000018 | 3 | 1 | RO
pending_server_dc_power_cycle | 0x00000018 | 4 | 1 | RO
pending_server_ac_power_cycle | 0x00000018 | 5 | 1 | RO
self_activation | 0x00000018 | 6 | 1 | RO
fw_image_status_bitmap | 0x00000018 | 0 | 8 | RO
fw_image_info_bitmap | 0x00000018 | 16 | 8 | RO
image_a_minor | 0x0000001c | 0 | 8 | RO
image_a_major | 0x0000001c | 8 | 8 | RO
image_a_subminor | 0x00000020 | 0 | 16 | RO
image_b_minor | 0x00000024 | 0 | 8 | RO
image_b_major | 0x00000024 | 8 | 8 | RO
image_b_subminor | 0x00000028 | 0 | 16 | RO
factory_image_minor | 0x0000002c | 0 | 8 | RO
factory_image_major | 0x0000002c | 8 | 8 | RO
factory_image_subminor | 0x00000030 | 0 | 16 | RO
management_interface_protocol | 0x00000034 | 0 | 6 | RO
activation_type | 0x00000034 | 10 | 4 | RO
vendor_sn | 0x00000038 | 0 | 16 | RO
==========================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MCQS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================================
component_index | 0x00000000 | 0 | 16 | INDEX
device_index | 0x00000000 | 16 | 12 | INDEX
last_index_flag | 0x00000000 | 31 | 1 | RO
identifier | 0x00000004 | 0 | 16 | RO
component_update_state | 0x00000008 | 0 | 4 | RO
component_status | 0x00000008 | 4 | 5 | RO
progress | 0x00000008 | 9 | 7 | RO
device_type | 0x0000000c | 0 | 8 | INDEX
last_update_state_changer_host_id | 0x0000000c | 24 | 4 | RO
last_update_state_changer_type | 0x0000000c | 28 | 4 | RO
==============================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MDCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================
device_type | 0x00000000 | 0 | 8 | INDEX
slot_index | 0x00000000 | 16 | 4 | INDEX
device_index | 0x00000004 | 0 | 12 | INDEX
xm_status | 0x00000010 | 20 | 4 | RO
xm_major | 0x00000014 | 0 | 16 | RO
xm_minor | 0x00000018 | 0 | 16 | RO
xm_build_id | 0x0000001c | 0 | 16 | RO
xm_expected_major | 0x00000020 | 0 | 16 | RO
xm_expected_minor | 0x00000024 | 0 | 16 | RO
==============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MDFCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===================================================================================
device_type | 0x00000000 | 0 | 8 | INDEX
device_index | 0x00000004 | 0 | 12 | INDEX
all | 0x00000004 | 31 | 1 | INDEX
first_fw_status_device | 0x0000000c | 0 | 12 | RO
fw_status | 0x0000000c | 20 | 4 | RO
expected_fw_version | 0x00000010 | 0 | 32 | RO
fw_version | 0x00000014 | 0 | 32 | RO
build_id | 0x00000018 | 0 | 16 | RO
major | 0x0000001c | 0 | 8 | RO
minor | 0x00000020 | 0 | 8 | RO
error_id | 0x00000024 | 11 | 5 | RO
===================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MDIR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=========================================================================
device_id[0] | 0x00000000 | 0 | 32 | RO
device_id[1] | 0x00000004 | 0 | 32 | RO
device_id[2] | 0x00000008 | 0 | 32 | RO
device_id[3] | 0x0000000c | 0 | 32 | RO
device_id[4] | 0x00000010 | 0 | 32 | RO
device_id[5] | 0x00000014 | 0 | 32 | RO
device_id[6] | 0x00000018 | 0 | 32 | RO
device_id[7] | 0x0000001c | 0 | 32 | RO
=========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MDRCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=========================================================================
device_type | 0x00000000 | 0 | 8 | INDEX
device_index | 0x00000004 | 0 | 12 | INDEX
all | 0x00000004 | 31 | 1 | INDEX
rst_op | 0x0000000c | 0 | 3 | RW
rst_status | 0x0000000c | 16 | 4 | RO
=========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MDSR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
============================================================================
status | 0x00000000 | 0 | 4 | RO
additional_info | 0x00000000 | 8 | 6 | RO
end | 0x00000004 | 31 | 1 | WO
============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MERR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==========================================================================
ent_type | 0x00000000 | 0 | 4 | INDEX
current_index | 0x00000000 | 16 | 8 | INDEX
target_index | 0x00000004 | 0 | 8 | RW
==========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MFBA
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================
fs | 0x00000000 | 4 | 2 | INDEX
add_cap_32b | 0x00000000 | 31 | 1 | RO
size | 0x00000004 | 0 | 9 | WO
address | 0x00000008 | 0 | 32 | INDEX
data[0] | 0x0000000c | 0 | 32 | RW
data[1] | 0x00000010 | 0 | 32 | RW
data[2] | 0x00000014 | 0 | 32 | RW
data[3] | 0x00000018 | 0 | 32 | RW
data[4] | 0x0000001c | 0 | 32 | RW
data[5] | 0x00000020 | 0 | 32 | RW
data[6] | 0x00000024 | 0 | 32 | RW
data[7] | 0x00000028 | 0 | 32 | RW
data[8] | 0x0000002c | 0 | 32 | RW
data[9] | 0x00000030 | 0 | 32 | RW
data[10] | 0x00000034 | 0 | 32 | RW
data[11] | 0x00000038 | 0 | 32 | RW
data[12] | 0x0000003c | 0 | 32 | RW
data[13] | 0x00000040 | 0 | 32 | RW
data[14] | 0x00000044 | 0 | 32 | RW
data[15] | 0x00000048 | 0 | 32 | RW
data[16] | 0x0000004c | 0 | 32 | RW
data[17] | 0x00000050 | 0 | 32 | RW
data[18] | 0x00000054 | 0 | 32 | RW
data[19] | 0x00000058 | 0 | 32 | RW
data[20] | 0x0000005c | 0 | 32 | RW
data[21] | 0x00000060 | 0 | 32 | RW
data[22] | 0x00000064 | 0 | 32 | RW
data[23] | 0x00000068 | 0 | 32 | RW
data[24] | 0x0000006c | 0 | 32 | RW
data[25] | 0x00000070 | 0 | 32 | RW
data[26] | 0x00000074 | 0 | 32 | RW
data[27] | 0x00000078 | 0 | 32 | RW
data[28] | 0x0000007c | 0 | 32 | RW
data[29] | 0x00000080 | 0 | 32 | RW
data[30] | 0x00000084 | 0 | 32 | RW
data[31] | 0x00000088 | 0 | 32 | RW
data[32] | 0x0000008c | 0 | 32 | RW
data[33] | 0x00000090 | 0 | 32 | RW
data[34] | 0x00000094 | 0 | 32 | RW
data[35] | 0x00000098 | 0 | 32 | RW
data[36] | 0x0000009c | 0 | 32 | RW
data[37] | 0x000000a0 | 0 | 32 | RW
data[38] | 0x000000a4 | 0 | 32 | RW
data[39] | 0x000000a8 | 0 | 32 | RW
data[40] | 0x000000ac | 0 | 32 | RW
data[41] | 0x000000b0 | 0 | 32 | RW
data[42] | 0x000000b4 | 0 | 32 | RW
data[43] | 0x000000b8 | 0 | 32 | RW
data[44] | 0x000000bc | 0 | 32 | RW
data[45] | 0x000000c0 | 0 | 32 | RW
data[46] | 0x000000c4 | 0 | 32 | RW
data[47] | 0x000000c8 | 0 | 32 | RW
data[48] | 0x000000cc | 0 | 32 | RW
data[49] | 0x000000d0 | 0 | 32 | RW
data[50] | 0x000000d4 | 0 | 32 | RW
data[51] | 0x000000d8 | 0 | 32 | RW
data[52] | 0x000000dc | 0 | 32 | RW
data[53] | 0x000000e0 | 0 | 32 | RW
data[54] | 0x000000e4 | 0 | 32 | RW
data[55] | 0x000000e8 | 0 | 32 | RW
data[56] | 0x000000ec | 0 | 32 | RW
data[57] | 0x000000f0 | 0 | 32 | RW
data[58] | 0x000000f4 | 0 | 32 | RW
data[59] | 0x000000f8 | 0 | 32 | RW
data[60] | 0x000000fc | 0 | 32 | RW
data[61] | 0x00000100 | 0 | 32 | RW
data[62] | 0x00000104 | 0 | 32 | RW
data[63] | 0x00000108 | 0 | 32 | RW
========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MFBE
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
============================================================================
fs | 0x00000000 | 4 | 2 | INDEX
bulk_64kb_erase | 0x00000000 | 29 | 1 | WO
bulk_32kb_erase | 0x00000000 | 30 | 1 | WO
add_cap_32b | 0x00000000 | 31 | 1 | RO
address | 0x00000008 | 0 | 32 | INDEX
============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MFCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==========================================================================
pwm_frequency | 0x00000000 | 0 | 7 | RW
pwm_active | 0x00000004 | 0 | 5 | RO
tacho_active | 0x00000004 | 16 | 10 | RO
==========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MFM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
index | 0x00000000 | 0 | 4 | INDEX
memory_high | 0x00000008 | 0 | 32 | RW
memory_low | 0x0000000c | 0 | 32 | RW
memory_mask_high | 0x00000010 | 0 | 32 | WO
memory_mask_low | 0x00000014 | 0 | 32 | WO
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MFMC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
====================================================================================
fs | 0x00000000 | 4 | 2 | INDEX
wrp_block_count | 0x00000004 | 0 | 8 | RW
block_size | 0x00000004 | 16 | 2 | RW
wrp_en | 0x00000004 | 31 | 1 | RW
sub_sector_protect_size | 0x00000008 | 0 | 6 | RO
sector_protect_size | 0x00000008 | 8 | 6 | RO
quad_en | 0x00000010 | 24 | 1 | RW
dummy_clock_cycles | 0x00000018 | 0 | 4 | RW
====================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MFNR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
fan_index | 0x00000000 | 0 | 5 | INDEX
serial_number[0] | 0x00000004 | 0 | 32 | RO
serial_number[1] | 0x00000008 | 0 | 32 | RO
serial_number[2] | 0x0000000c | 0 | 32 | RO
serial_number[3] | 0x00000010 | 0 | 32 | RO
serial_number[4] | 0x00000014 | 0 | 32 | RO
serial_number[5] | 0x00000018 | 0 | 32 | RO
part_number[0] | 0x0000001c | 0 | 32 | RO
part_number[1] | 0x00000020 | 0 | 32 | RO
part_number[2] | 0x00000024 | 0 | 32 | RO
part_number[3] | 0x00000028 | 0 | 32 | RO
part_number[4] | 0x0000002c | 0 | 32 | RO
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MFPA
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================================
fs | 0x00000000 | 4 | 2 | INDEX
add_cap_32b | 0x00000000 | 31 | 1 | RO
boot_address | 0x00000004 | 0 | 32 | RW
flash_num | 0x00000010 | 0 | 4 | RO
sub_sector_wrp_en | 0x00000010 | 16 | 1 | RO
sector_wrp_en | 0x00000010 | 17 | 1 | RO
bulk_64kb_erase_en | 0x00000010 | 29 | 1 | RO
bulk_32kb_erase_en | 0x00000010 | 30 | 1 | RO
wip | 0x00000010 | 31 | 1 | RO
jedec_id | 0x00000014 | 0 | 24 | RO
sector_size | 0x00000018 | 0 | 10 | RO
block_alignment | 0x00000018 | 16 | 8 | RO
block_size | 0x00000018 | 24 | 8 | RO
capability_mask | 0x0000001c | 0 | 32 | RO
===============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MFRL
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=========================================================================================
reset_level | 0x00000004 | 0 | 8 | RW
reset_type | 0x00000004 | 8 | 8 | RO
rst_type_sel | 0x00000004 | 24 | 3 | RW
pci_sync_for_fw_update_resp | 0x00000004 | 27 | 2 | WO
pci_sync_for_fw_update_start | 0x00000004 | 29 | 1 | WO
=========================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MFSC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================
pwm | 0x00000000 | 24 | 3 | INDEX
pwm_duty_cycle | 0x00000004 | 0 | 8 | RW
===========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MFSL
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=====================================================================
ie | 0x00000000 | 0 | 1 | RW
ee | 0x00000000 | 2 | 2 | RW
tacho | 0x00000000 | 24 | 4 | INDEX
tach_min | 0x00000004 | 0 | 16 | RW
tach_max | 0x00000008 | 0 | 16 | RW
=====================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MFSM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==================================================================
n | 0x00000000 | 0 | 2 | RW
tacho | 0x00000000 | 24 | 4 | INDEX
rpm | 0x00000004 | 0 | 16 | RO
==================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MGCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================
segment | 0x00000000 | 0 | 8 | RW
segments_count | 0x00000000 | 8 | 8 | RO
GPIO_data_in | 0x00000004 | 0 | 32 | RO
GPIO_data_out | 0x00000008 | 0 | 32 | RO
GPIO_set | 0x0000000c | 0 | 32 | WO
GPIO_clear | 0x00000010 | 0 | 32 | WO
GPIO_access_en | 0x00000014 | 0 | 32 | RO
direction | 0x00000018 | 0 | 32 | RO
drive_type | 0x0000001c | 0 | 32 | RO
===========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MGIR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=========================================================================================
device_id | 0x00000000 | 0 | 16 | RO
device_hw_revision | 0x00000000 | 16 | 16 | RO
pvs | 0x00000004 | 0 | 5 | RO
num_ports | 0x00000004 | 16 | 8 | RO
hw_dev_id | 0x00000008 | 0 | 16 | RO
manufacturing_base_mac_47_32 | 0x00000010 | 0 | 16 | RO
manufacturing_base_mac_31_0 | 0x00000014 | 0 | 32 | RO
uptime | 0x0000001c | 0 | 32 | RO
sub_minor | 0x00000020 | 0 | 8 | RO
minor | 0x00000020 | 8 | 8 | RO
major | 0x00000020 | 16 | 8 | RO
secured | 0x00000020 | 24 | 1 | RO
signed_fw | 0x00000020 | 25 | 1 | RO
debug | 0x00000020 | 26 | 1 | RO
dev | 0x00000020 | 27 | 1 | RO
string_tlv | 0x00000020 | 28 | 1 | RO
build_id | 0x00000024 | 0 | 32 | RO
year | 0x00000028 | 0 | 16 | RO
day | 0x00000028 | 16 | 8 | RO
month | 0x00000028 | 24 | 8 | RO
hour | 0x0000002c | 0 | 16 | RO
psid[3] | 0x00000030 | 0 | 8 | RO
psid[2] | 0x00000030 | 8 | 8 | RO
psid[1] | 0x00000030 | 16 | 8 | RO
psid[0] | 0x00000030 | 24 | 8 | RO
psid[7] | 0x00000034 | 0 | 8 | RO
psid[6] | 0x00000034 | 8 | 8 | RO
psid[5] | 0x00000034 | 16 | 8 | RO
psid[4] | 0x00000034 | 24 | 8 | RO
psid[11] | 0x00000038 | 0 | 8 | RO
psid[10] | 0x00000038 | 8 | 8 | RO
psid[9] | 0x00000038 | 16 | 8 | RO
psid[8] | 0x00000038 | 24 | 8 | RO
psid[15] | 0x0000003c | 0 | 8 | RO
psid[14] | 0x0000003c | 8 | 8 | RO
psid[13] | 0x0000003c | 16 | 8 | RO
psid[12] | 0x0000003c | 24 | 8 | RO
ini_file_version | 0x00000040 | 0 | 32 | RO
extended_major | 0x00000044 | 0 | 32 | RO
extended_minor | 0x00000048 | 0 | 32 | RO
extended_sub_minor | 0x0000004c | 0 | 32 | RO
isfu_major | 0x00000050 | 0 | 16 | RO
life_cycle | 0x00000054 | 0 | 2 | RO
sec_boot | 0x00000054 | 2 | 1 | RO
sub_minor | 0x00000060 | 0 | 8 | RO
minor | 0x00000060 | 8 | 8 | RO
major | 0x00000060 | 16 | 8 | RO
rom3_type | 0x00000064 | 0 | 4 | RO
rom3_arch | 0x00000064 | 4 | 4 | RO
rom2_type | 0x00000064 | 8 | 4 | RO
rom2_arch | 0x00000064 | 12 | 4 | RO
rom1_type | 0x00000064 | 16 | 4 | RO
rom1_arch | 0x00000064 | 20 | 4 | RO
rom0_type | 0x00000064 | 24 | 4 | RO
rom0_arch | 0x00000064 | 28 | 4 | RO
build | 0x00000068 | 0 | 16 | RO
minor | 0x00000068 | 16 | 8 | RO
major | 0x00000068 | 24 | 8 | RO
build | 0x0000006c | 0 | 16 | RO
minor | 0x0000006c | 16 | 8 | RO
major | 0x0000006c | 24 | 8 | RO
build | 0x00000070 | 0 | 16 | RO
minor | 0x00000070 | 16 | 8 | RO
major | 0x00000070 | 24 | 8 | RO
build | 0x00000074 | 0 | 16 | RO
minor | 0x00000074 | 16 | 8 | RO
major | 0x00000074 | 24 | 8 | RO
=========================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MGNLE
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================
le_pointer | 0x00000000 | 0 | 32 | INDEX
lost_events | 0x00000004 | 24 | 4 | RO
synced_time | 0x00000004 | 31 | 1 | RO
time_h | 0x00000008 | 0 | 32 | RO
time_l | 0x0000000c | 0 | 32 | RO
length | 0x00000010 | 0 | 9 | RW
writer_host_id | 0x00000010 | 9 | 3 | RO
version | 0x00000010 | 12 | 4 | RW
writer_id | 0x00000010 | 16 | 5 | RO
access_mode | 0x00000010 | 22 | 2 | INDEX
type_index | 0x00000014 | 0 | 24 | INDEX
type_class | 0x00000014 | 24 | 8 | INDEX
log_data | 0x0000001c | 0 | 32 | RO
===========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MGPIR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================
num_of_devices | 0x00000000 | 0 | 8 | RO
devices_per_flash | 0x00000000 | 16 | 8 | RO
device_type | 0x00000000 | 24 | 4 | RO
slot_index | 0x00000000 | 28 | 4 | INDEX
num_of_modules | 0x00000004 | 0 | 8 | RO
num_of_slots | 0x00000004 | 8 | 8 | RO
==============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MHMPR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
================================================================
upm | 0x00000000 | 0 | 1 | RW
================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MHSR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===================================================================
health | 0x00000000 | 0 | 4 | WO
===================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MIRC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================
status_code | 0x00000000 | 0 | 8 | RO
========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MJTAG
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=====================================================================================
size | 0x00000000 | 0 | 8 | WO
sequence_number | 0x00000000 | 24 | 4 | WO
cmd | 0x00000000 | 30 | 2 | RW
jtag_transaction_set[3] | 0x00000004 | 0 | 8 | RW
jtag_transaction_set[2] | 0x00000004 | 8 | 8 | RW
jtag_transaction_set[1] | 0x00000004 | 16 | 8 | RW
jtag_transaction_set[0] | 0x00000004 | 24 | 8 | RW
jtag_transaction_set[7] | 0x00000008 | 0 | 8 | RW
jtag_transaction_set[6] | 0x00000008 | 8 | 8 | RW
jtag_transaction_set[5] | 0x00000008 | 16 | 8 | RW
jtag_transaction_set[4] | 0x00000008 | 24 | 8 | RW
jtag_transaction_set[11] | 0x0000000c | 0 | 8 | RW
jtag_transaction_set[10] | 0x0000000c | 8 | 8 | RW
jtag_transaction_set[9] | 0x0000000c | 16 | 8 | RW
jtag_transaction_set[8] | 0x0000000c | 24 | 8 | RW
jtag_transaction_set[15] | 0x00000010 | 0 | 8 | RW
jtag_transaction_set[14] | 0x00000010 | 8 | 8 | RW
jtag_transaction_set[13] | 0x00000010 | 16 | 8 | RW
jtag_transaction_set[12] | 0x00000010 | 24 | 8 | RW
jtag_transaction_set[19] | 0x00000014 | 0 | 8 | RW
jtag_transaction_set[18] | 0x00000014 | 8 | 8 | RW
jtag_transaction_set[17] | 0x00000014 | 16 | 8 | RW
jtag_transaction_set[16] | 0x00000014 | 24 | 8 | RW
jtag_transaction_set[23] | 0x00000018 | 0 | 8 | RW
jtag_transaction_set[22] | 0x00000018 | 8 | 8 | RW
jtag_transaction_set[21] | 0x00000018 | 16 | 8 | RW
jtag_transaction_set[20] | 0x00000018 | 24 | 8 | RW
jtag_transaction_set[27] | 0x0000001c | 0 | 8 | RW
jtag_transaction_set[26] | 0x0000001c | 8 | 8 | RW
jtag_transaction_set[25] | 0x0000001c | 16 | 8 | RW
jtag_transaction_set[24] | 0x0000001c | 24 | 8 | RW
jtag_transaction_set[31] | 0x00000020 | 0 | 8 | RW
jtag_transaction_set[30] | 0x00000020 | 8 | 8 | RW
jtag_transaction_set[29] | 0x00000020 | 16 | 8 | RW
jtag_transaction_set[28] | 0x00000020 | 24 | 8 | RW
jtag_transaction_set[35] | 0x00000024 | 0 | 8 | RW
jtag_transaction_set[34] | 0x00000024 | 8 | 8 | RW
jtag_transaction_set[33] | 0x00000024 | 16 | 8 | RW
jtag_transaction_set[32] | 0x00000024 | 24 | 8 | RW
jtag_transaction_set[39] | 0x00000028 | 0 | 8 | RW
jtag_transaction_set[38] | 0x00000028 | 8 | 8 | RW
jtag_transaction_set[37] | 0x00000028 | 16 | 8 | RW
jtag_transaction_set[36] | 0x00000028 | 24 | 8 | RW
jtag_transaction_set[43] | 0x0000002c | 0 | 8 | RW
jtag_transaction_set[42] | 0x0000002c | 8 | 8 | RW
jtag_transaction_set[41] | 0x0000002c | 16 | 8 | RW
jtag_transaction_set[40] | 0x0000002c | 24 | 8 | RW
=====================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MLCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==================================================================================
led_type | 0x00000000 | 0 | 4 | RW
cap_local_or_uid_only | 0x00000000 | 4 | 1 | RO
operation_cap | 0x00000000 | 5 | 1 | RO
operation | 0x00000000 | 12 | 4 | RW
local_port | 0x00000000 | 16 | 8 | RW
beacon_duration | 0x00000004 | 0 | 16 | RW
beacon_remain | 0x00000008 | 0 | 16 | RO
==================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MMIA
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
======================================================================
operation | 0x00000000 | 0 | 3 | WO
Data | 0x00000008 | 0 | 32 | RW
======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MNVDA
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
====================================================================================
length | 0x00000000 | 0 | 9 | RW
writer_host_id | 0x00000000 | 9 | 3 | RO
version | 0x00000000 | 12 | 4 | RW
writer_id | 0x00000000 | 16 | 5 | RO
access_mode | 0x00000000 | 22 | 2 | INDEX
type_index | 0x00000004 | 0 | 24 | INDEX
type_class | 0x00000004 | 24 | 8 | INDEX
configuration_item_data | 0x0000000c | 0 | 32 | RW
====================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MNVDI
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================
length | 0x00000000 | 0 | 9 | RW
writer_host_id | 0x00000000 | 9 | 3 | RO
version | 0x00000000 | 12 | 4 | RW
writer_id | 0x00000000 | 16 | 5 | RO
access_mode | 0x00000000 | 22 | 2 | INDEX
type_index | 0x00000004 | 0 | 24 | INDEX
type_class | 0x00000004 | 24 | 8 | INDEX
===========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MNVGC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================================
nvda_read_factory_settings | 0x00000000 | 0 | 1 | RO
nvda_read_current_settings | 0x00000000 | 1 | 1 | RO
priv_nv_other_host | 0x00000000 | 2 | 1 | RO
=======================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MNVGN
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
====================================================================================
nv_pointer | 0x00000000 | 0 | 32 | INDEX
length | 0x00000010 | 0 | 9 | RW
writer_host_id | 0x00000010 | 9 | 3 | RO
version | 0x00000010 | 12 | 4 | RW
writer_id | 0x00000010 | 16 | 5 | RO
access_mode | 0x00000010 | 22 | 2 | INDEX
type_index | 0x00000014 | 0 | 24 | INDEX
type_class | 0x00000014 | 24 | 8 | INDEX
configuration_item_data | 0x0000001c | 0 | 32 | RO
====================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MNVIA
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
======================================================================
target | 0x00000000 | 0 | 3 | WO
writer_id | 0x00000000 | 4 | 5 | RW
======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MNVQC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
type | 0x00000000 | 0 | 32 | INDEX
support_rd | 0x00000004 | 0 | 1 | RO
support_wr | 0x00000004 | 1 | 1 | RO
version | 0x00000004 | 4 | 4 | RO
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MPCIR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
all | 0x00000000 | 30 | 2 | OP
ports | 0x00000004 | 0 | 2 | OP
ports_stat | 0x0000000c | 0 | 2 | RO
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MPCNT
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================================
grp | 0x00000000 | 0 | 6 | INDEX
node | 0x00000000 | 8 | 8 | INDEX
pcie_index | 0x00000000 | 16 | 8 | INDEX
depth | 0x00000000 | 24 | 6 | INDEX
clr | 0x00000004 | 31 | 1 | WO
rx_errors | 0x00000010 | 0 | 32 | RO
tx_errors | 0x00000014 | 0 | 32 | RO
crc_error_dllp | 0x00000028 | 0 | 32 | RO
crc_error_tlp | 0x0000002c | 0 | 32 | RO
hi | 0x00000030 | 0 | 32 | RO
lo | 0x00000034 | 0 | 32 | RO
outbound_stalled_reads | 0x00000038 | 0 | 32 | RO
outbound_stalled_writes | 0x0000003c | 0 | 32 | RO
outbound_stalled_reads_events | 0x00000040 | 0 | 32 | RO
outbound_stalled_writes_events | 0x00000044 | 0 | 32 | RO
hi | 0x00000048 | 0 | 32 | RO
lo | 0x0000004c | 0 | 32 | RO
effective_ber_coef | 0x00000050 | 0 | 4 | RO
effective_ber_magnitude | 0x00000050 | 8 | 8 | RO
error_counter_lane0 | 0x00000010 | 0 | 32 | RO
error_counter_lane1 | 0x00000014 | 0 | 32 | RO
error_counter_lane2 | 0x00000018 | 0 | 32 | RO
error_counter_lane3 | 0x0000001c | 0 | 32 | RO
error_counter_lane4 | 0x00000020 | 0 | 32 | RO
error_counter_lane5 | 0x00000024 | 0 | 32 | RO
error_counter_lane6 | 0x00000028 | 0 | 32 | RO
error_counter_lane7 | 0x0000002c | 0 | 32 | RO
error_counter_lane8 | 0x00000030 | 0 | 32 | RO
error_counter_lane9 | 0x00000034 | 0 | 32 | RO
error_counter_lane10 | 0x00000038 | 0 | 32 | RO
error_counter_lane11 | 0x0000003c | 0 | 32 | RO
error_counter_lane12 | 0x00000040 | 0 | 32 | RO
error_counter_lane13 | 0x00000044 | 0 | 32 | RO
error_counter_lane14 | 0x00000048 | 0 | 32 | RO
error_counter_lane15 | 0x0000004c | 0 | 32 | RO
time_to_boot_image_start | 0x00000010 | 0 | 32 | RO
time_to_link_image | 0x00000014 | 0 | 32 | RO
calibration_time | 0x00000018 | 0 | 32 | RO
time_to_first_perst | 0x0000001c | 0 | 32 | RO
time_to_detect_state | 0x00000020 | 0 | 32 | RO
time_to_l0 | 0x00000024 | 0 | 32 | RO
time_to_crs_en | 0x00000028 | 0 | 32 | RO
time_to_plastic_image_start | 0x0000002c | 0 | 32 | RO
time_to_iron_image_start | 0x00000030 | 0 | 32 | RO
perst_handler | 0x00000034 | 0 | 32 | RO
times_in_l1 | 0x00000038 | 0 | 32 | RO
times_in_l23 | 0x0000003c | 0 | 32 | RO
dl_down | 0x00000040 | 0 | 32 | RO
config_cycle1usec | 0x00000044 | 0 | 32 | RO
config_cycle2to7usec | 0x00000048 | 0 | 32 | RO
config_cycle8to15usec | 0x0000004c | 0 | 32 | RO
config_cycle16to63usec | 0x00000050 | 0 | 32 | RO
config_cycle64usec | 0x00000054 | 0 | 32 | RO
correctable_err_msg_sent | 0x00000058 | 0 | 32 | RO
non_fatal_err_msg_sent | 0x0000005c | 0 | 32 | RO
fatal_err_msg_sent | 0x00000060 | 0 | 32 | RO
===========================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MPECS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==========================================================================
node | 0x00000000 | 8 | 8 | INDEX
pcie_index | 0x00000000 | 16 | 8 | INDEX
depth | 0x00000000 | 24 | 6 | INDEX
capability_id | 0x00000004 | 0 | 16 | INDEX
reg_num | 0x00000008 | 0 | 16 | INDEX
byte_enable | 0x0000000c | 0 | 4 | WO
status | 0x0000000c | 8 | 8 | RO
func_num | 0x0000000c | 16 | 8 | INDEX
ext | 0x00000010 | 0 | 2 | INDEX
data | 0x00000014 | 0 | 32 | RW
==========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MPEIN
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
====================================================================================
node | 0x00000000 | 8 | 8 | INDEX
pcie_index | 0x00000000 | 16 | 8 | INDEX
depth | 0x00000000 | 24 | 6 | INDEX
link_speed_enabled | 0x00000008 | 0 | 16 | RO
link_width_enabled | 0x00000008 | 16 | 8 | RO
link_speed_active | 0x0000000c | 0 | 16 | RO
link_width_active | 0x0000000c | 16 | 8 | RO
lane0_physical_position | 0x0000000c | 24 | 8 | RO
num_of_vfs | 0x00000010 | 0 | 16 | RO
num_of_pfs | 0x00000010 | 16 | 16 | RO
bdf0 | 0x00000014 | 16 | 16 | RO
lane_reversal | 0x00000018 | 0 | 1 | RO
port_type | 0x00000018 | 12 | 4 | RO
pwr_status | 0x00000018 | 16 | 3 | RO
max_payload_size | 0x00000018 | 24 | 4 | RO
max_read_request_size | 0x00000018 | 28 | 4 | RO
pci_power | 0x0000001c | 0 | 12 | RO
link_peer_max_speed | 0x0000001c | 16 | 16 | RO
device_status | 0x00000024 | 16 | 16 | RO
====================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MPFM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================
mode | 0x00000000 | 0 | 4 | RW
=================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MPGO
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================
set_pd | 0x00000000 | 0 | 1 | WO
hi | 0x00000008 | 0 | 32 | RW
lo | 0x0000000c | 0 | 32 | RW
pulse_duration | 0x00000010 | 0 | 10 | RW
===========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MPGR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================
fsps_admin | 0x00000000 | 0 | 4 | RW
fsps_status | 0x00000004 | 0 | 4 | RO
vsps_admin | 0x00000010 | 0 | 4 | RW
vsps_status | 0x00000014 | 0 | 4 | RO
========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MPIR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
============================================================================
host_buses | 0x00000000 | 0 | 4 | RO
node | 0x00000000 | 8 | 8 | INDEX
pcie_index | 0x00000000 | 16 | 8 | INDEX
depth | 0x00000000 | 24 | 6 | INDEX
sdm | 0x00000000 | 31 | 1 | RO
subordinate_bus | 0x00000004 | 0 | 8 | RO
secondary_bus | 0x00000004 | 8 | 8 | RO
device | 0x00000008 | 3 | 5 | RO
bus | 0x00000008 | 16 | 8 | RO
local_port | 0x00000008 | 24 | 8 | RO
slot_number | 0x0000000c | 0 | 13 | RO
num_con_devices | 0x0000000c | 16 | 8 | RO
slot_cap | 0x0000000c | 31 | 1 | RO
============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MQIS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================
info_type | 0x00000000 | 0 | 8 | INDEX
info_length | 0x00000004 | 0 | 16 | RO
read_length | 0x00000008 | 0 | 16 | RW
read_offset | 0x00000008 | 16 | 16 | INDEX
info_string[3] | 0x00000010 | 0 | 8 | RO
info_string[2] | 0x00000010 | 8 | 8 | RO
info_string[1] | 0x00000010 | 16 | 8 | RO
info_string[0] | 0x00000010 | 24 | 8 | RO
info_string[7] | 0x00000014 | 0 | 8 | RO
info_string[6] | 0x00000014 | 8 | 8 | RO
info_string[5] | 0x00000014 | 16 | 8 | RO
info_string[4] | 0x00000014 | 24 | 8 | RO
===========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MRSR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
====================================================================
command | 0x00000000 | 0 | 4 | WO
====================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MRTC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================
time_synced | 0x00000000 | 31 | 1 | RO
time_h | 0x00000008 | 0 | 32 | RW
time_l | 0x0000000c | 0 | 32 | RW
========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MSCI
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
====================================================================
index | 0x00000000 | 0 | 4 | INDEX
version | 0x00000004 | 0 | 32 | RO
====================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MSGI
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
serial_number[0] | 0x00000000 | 0 | 32 | RO
serial_number[1] | 0x00000004 | 0 | 32 | RO
serial_number[2] | 0x00000008 | 0 | 32 | RO
serial_number[3] | 0x0000000c | 0 | 32 | RO
serial_number[4] | 0x00000010 | 0 | 32 | RO
serial_number[5] | 0x00000014 | 0 | 32 | RO
part_number[0] | 0x00000020 | 0 | 32 | RO
part_number[1] | 0x00000024 | 0 | 32 | RO
part_number[2] | 0x00000028 | 0 | 32 | RO
part_number[3] | 0x0000002c | 0 | 32 | RO
part_number[4] | 0x00000030 | 0 | 32 | RO
revision | 0x00000038 | 0 | 32 | RO
product_name[0] | 0x00000040 | 0 | 32 | RO
product_name[1] | 0x00000044 | 0 | 32 | RO
product_name[2] | 0x00000048 | 0 | 32 | RO
product_name[3] | 0x0000004c | 0 | 32 | RO
product_name[4] | 0x00000050 | 0 | 32 | RO
product_name[5] | 0x00000054 | 0 | 32 | RO
product_name[6] | 0x00000058 | 0 | 32 | RO
product_name[7] | 0x0000005c | 0 | 32 | RO
product_name[8] | 0x00000060 | 0 | 32 | RO
product_name[9] | 0x00000064 | 0 | 32 | RO
product_name[10] | 0x00000068 | 0 | 32 | RO
product_name[11] | 0x0000006c | 0 | 32 | RO
product_name[12] | 0x00000070 | 0 | 32 | RO
product_name[13] | 0x00000074 | 0 | 32 | RO
product_name[14] | 0x00000078 | 0 | 32 | RO
product_name[15] | 0x0000007c | 0 | 32 | RO
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MSPS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=====================================================================
psu0[0] | 0x00000000 | 0 | 32 | RO
psu0[1] | 0x00000004 | 0 | 32 | RO
psu0[2] | 0x00000008 | 0 | 32 | RO
psu0[3] | 0x0000000c | 0 | 32 | RO
psu0[4] | 0x00000010 | 0 | 32 | RO
psu0[5] | 0x00000014 | 0 | 32 | RO
psu0[6] | 0x00000018 | 0 | 32 | RO
psu0[7] | 0x0000001c | 0 | 32 | RO
psu0[8] | 0x00000020 | 0 | 32 | RO
psu0[9] | 0x00000024 | 0 | 32 | RO
psu0[10] | 0x00000028 | 0 | 32 | RO
psu0[11] | 0x0000002c | 0 | 32 | RO
psu0[12] | 0x00000030 | 0 | 32 | RO
psu0[13] | 0x00000034 | 0 | 32 | RO
psu0[14] | 0x00000038 | 0 | 32 | RO
psu0[15] | 0x0000003c | 0 | 32 | RO
psu0[16] | 0x00000040 | 0 | 32 | RO
psu0[17] | 0x00000044 | 0 | 32 | RO
psu0[18] | 0x00000048 | 0 | 32 | RO
psu0[19] | 0x0000004c | 0 | 32 | RO
psu1[0] | 0x00000050 | 0 | 32 | RO
psu1[1] | 0x00000054 | 0 | 32 | RO
psu1[2] | 0x00000058 | 0 | 32 | RO
psu1[3] | 0x0000005c | 0 | 32 | RO
psu1[4] | 0x00000060 | 0 | 32 | RO
psu1[5] | 0x00000064 | 0 | 32 | RO
psu1[6] | 0x00000068 | 0 | 32 | RO
psu1[7] | 0x0000006c | 0 | 32 | RO
psu1[8] | 0x00000070 | 0 | 32 | RO
psu1[9] | 0x00000074 | 0 | 32 | RO
psu1[10] | 0x00000078 | 0 | 32 | RO
psu1[11] | 0x0000007c | 0 | 32 | RO
psu1[12] | 0x00000080 | 0 | 32 | RO
psu1[13] | 0x00000084 | 0 | 32 | RO
psu1[14] | 0x00000088 | 0 | 32 | RO
psu1[15] | 0x0000008c | 0 | 32 | RO
psu1[16] | 0x00000090 | 0 | 32 | RO
psu1[17] | 0x00000094 | 0 | 32 | RO
psu1[18] | 0x00000098 | 0 | 32 | RO
psu1[19] | 0x0000009c | 0 | 32 | RO
=====================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MSSIR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
======================================================================
crc | 0x00000000 | 0 | 8 | RO
bypass | 0x00000004 | 0 | 8 | RO
fatal_dft | 0x00000008 | 0 | 8 | RO
freq0 | 0x0000000c | 0 | 5 | RO
freq1 | 0x0000000c | 5 | 5 | RO
freq2 | 0x0000000c | 10 | 5 | RO
freq3 | 0x0000000c | 15 | 5 | RO
freq4 | 0x0000000c | 20 | 5 | RO
freq5 | 0x0000000c | 25 | 5 | RO
freq6 | 0x00000010 | 0 | 5 | RO
freq7 | 0x00000010 | 5 | 5 | RO
======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTBR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================
base_sensor_index | 0x00000000 | 0 | 12 | INDEX
slot_index | 0x00000000 | 16 | 4 | INDEX
num_rec | 0x00000004 | 0 | 8 | OP
temperature | 0x00000010 | 0 | 16 | RO
max_temperature | 0x00000010 | 16 | 16 | RO
temperature | 0x00000014 | 0 | 16 | RO
max_temperature | 0x00000014 | 16 | 16 | RO
==============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTCAP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=========================================================================
sensor_count | 0x00000000 | 0 | 7 | RO
slot_index | 0x00000000 | 16 | 4 | INDEX
hi | 0x00000008 | 0 | 32 | RO
lo | 0x0000000c | 0 | 32 | RO
=========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTECR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=========================================================================
sensor_count | 0x00000000 | 0 | 12 | RO
last_sensor | 0x00000000 | 16 | 12 | RO
slot_index | 0x00000004 | 28 | 4 | INDEX
sensor_map_0 | 0x00000008 | 0 | 32 | RO
=========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTEWE
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
sensor_count | 0x00000000 | 0 | 12 | RO
slot_index | 0x00000000 | 12 | 4 | INDEX
last_sensor | 0x00000000 | 16 | 12 | RO
sensor_warning_0 | 0x00000004 | 0 | 32 | RO
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTMP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=====================================================================================
sensor_index | 0x00000000 | 0 | 12 | INDEX
slot_index | 0x00000000 | 16 | 4 | INDEX
temperature | 0x00000004 | 0 | 16 | RO
max_temperature | 0x00000008 | 0 | 16 | RO
sdme | 0x00000008 | 28 | 1 | OP
weme | 0x00000008 | 29 | 1 | OP
mtr | 0x00000008 | 30 | 1 | OP
mte | 0x00000008 | 31 | 1 | RW
temperature_threshold_hi | 0x0000000c | 0 | 16 | RW
sdee | 0x0000000c | 28 | 2 | RW
tee | 0x0000000c | 30 | 2 | RW
temperature_threshold_lo | 0x00000010 | 0 | 16 | RW
sensor_name_hi | 0x00000018 | 0 | 32 | RO
sensor_name_lo | 0x0000001c | 0 | 32 | RO
=====================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTPPS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================================
cap_max_num_of_pps_out_pins | 0x00000000 | 0 | 4 | RO
cap_max_num_of_pps_in_pins | 0x00000000 | 8 | 4 | RO
cap_number_of_pps_pins | 0x00000000 | 16 | 4 | RO
cap_pin_0_mode | 0x00000008 | 0 | 4 | RO
cap_pin_1_mode | 0x00000008 | 8 | 4 | RO
cap_pin_2_mode | 0x00000008 | 16 | 4 | RO
cap_pin_3_mode | 0x00000008 | 24 | 4 | RO
cap_pin_4_mode | 0x0000000c | 0 | 4 | RO
cap_pin_5_mode | 0x0000000c | 8 | 4 | RO
cap_pin_6_mode | 0x0000000c | 16 | 4 | RO
cap_pin_7_mode | 0x0000000c | 24 | 4 | RO
field_select | 0x00000010 | 0 | 32 | WO
hi | 0x00000014 | 0 | 32 | RW
lo | 0x00000018 | 0 | 32 | RW
pin | 0x00000020 | 0 | 8 | INDEX
pin_mode | 0x00000020 | 8 | 4 | RW
pattern | 0x00000020 | 16 | 4 | RW
enable | 0x00000020 | 31 | 1 | RW
out_pulse_duration_ns | 0x00000024 | 0 | 30 | RW
hi | 0x00000028 | 0 | 32 | RW
lo | 0x0000002c | 0 | 32 | RW
out_periodic_adjustment | 0x00000030 | 0 | 16 | RW
out_pulse_duration | 0x00000030 | 16 | 16 | RW
enhanced_out_periodic_adjustment | 0x00000034 | 0 | 32 | RW
=============================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTPTP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===================================================================================
portnumber | 0x00000000 | 0 | 16 | INDEX
grandmasteridentity[3] | 0x00000008 | 0 | 8 | RW
grandmasteridentity[2] | 0x00000008 | 8 | 8 | RW
grandmasteridentity[1] | 0x00000008 | 16 | 8 | RW
grandmasteridentity[0] | 0x00000008 | 24 | 8 | RW
grandmasteridentity[7] | 0x0000000c | 0 | 8 | RW
grandmasteridentity[6] | 0x0000000c | 8 | 8 | RW
grandmasteridentity[5] | 0x0000000c | 16 | 8 | RW
grandmasteridentity[4] | 0x0000000c | 24 | 8 | RW
time_source | 0x00000014 | 0 | 8 | RW
li61 | 0x00000014 | 8 | 1 | RW
li59 | 0x00000014 | 9 | 1 | RW
utcv | 0x00000014 | 10 | 1 | RW
ptp | 0x00000014 | 11 | 1 | RW
ttra | 0x00000014 | 12 | 1 | RW
ftra | 0x00000014 | 13 | 1 | RW
current_utc_offset | 0x00000014 | 16 | 16 | RW
===================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTRC_CAP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
======================================================================================
num_string_db | 0x00000000 | 0 | 4 | RO
trc_ver | 0x00000000 | 24 | 2 | RO
trace_to_memory | 0x00000000 | 30 | 1 | RO
trace_owner | 0x00000000 | 31 | 1 | RW
num_string_trace | 0x00000004 | 16 | 8 | RO
first_string_trace | 0x00000004 | 24 | 8 | RO
log_max_trace_buffer_size | 0x00000008 | 0 | 8 | RO
string_db_base_address | 0x00000010 | 0 | 32 | RO
string_db_size | 0x00000014 | 0 | 24 | RO
string_db_base_address | 0x00000018 | 0 | 32 | RO
string_db_size | 0x0000001c | 0 | 24 | RO
string_db_base_address | 0x00000020 | 0 | 32 | RO
string_db_size | 0x00000024 | 0 | 24 | RO
string_db_base_address | 0x00000028 | 0 | 32 | RO
string_db_size | 0x0000002c | 0 | 24 | RO
string_db_base_address | 0x00000030 | 0 | 32 | RO
string_db_size | 0x00000034 | 0 | 24 | RO
string_db_base_address | 0x00000038 | 0 | 32 | RO
string_db_size | 0x0000003c | 0 | 24 | RO
string_db_base_address | 0x00000040 | 0 | 32 | RO
string_db_size | 0x00000044 | 0 | 24 | RO
string_db_base_address | 0x00000048 | 0 | 32 | RO
string_db_size | 0x0000004c | 0 | 24 | RO
======================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTRC_CONF
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==================================================================================
trace_mode | 0x00000000 | 0 | 4 | RW
log_trace_buffer_size | 0x00000004 | 0 | 8 | RW
trace_mkey | 0x00000008 | 0 | 32 | RW
==================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTRC_CTRL
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
====================================================================================
modify_field_select | 0x00000000 | 0 | 16 | WO
arm_event | 0x00000000 | 27 | 1 | WO
trace_status | 0x00000000 | 30 | 2 | RW
current_timestamp_52_32 | 0x00000008 | 0 | 21 | RO
current_timestamp_31_0 | 0x0000000c | 0 | 32 | RO
====================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTRC_STDB
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================
read_size | 0x00000000 | 0 | 24 | INDEX
string_db_index | 0x00000000 | 28 | 4 | INDEX
start_offset | 0x00000004 | 0 | 32 | INDEX
string_db_data[0] | 0x00000008 | 0 | 32 | RO
==============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTUTC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
operation | 0x00000000 | 0 | 4 | OP
time_stamp_state | 0x00000000 | 28 | 2 | RO
time_stamp_mode | 0x00000000 | 30 | 2 | RO
freq_adjustment | 0x00000004 | 0 | 32 | RW
utc_sec | 0x00000010 | 0 | 32 | WO
utc_nsec | 0x00000014 | 0 | 30 | WO
time_adjustment | 0x00000018 | 0 | 32 | WO
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MTWE
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================
sensor_warning[0] | 0x00000000 | 0 | 32 | RO
sensor_warning[1] | 0x00000004 | 0 | 32 | RO
sensor_warning[2] | 0x00000008 | 0 | 32 | RO
sensor_warning[3] | 0x0000000c | 0 | 32 | RO
==============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MVCAP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
hi | 0x00000000 | 0 | 32 | RO
lo | 0x00000004 | 0 | 32 | RO
slot_index | 0x00000008 | 0 | 4 | INDEX
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg MVCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================================
sensor_index | 0x00000000 | 0 | 7 | INDEX
slot_index | 0x00000000 | 16 | 4 | INDEX
voltage_sensor_value | 0x00000004 | 0 | 16 | RO
current_sensor_value | 0x00000008 | 0 | 16 | RO
hi | 0x00000010 | 0 | 32 | RO
lo | 0x00000014 | 0 | 32 | RO
=================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg NCFG
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================================
hi | 0x00000000 | 0 | 32 | RW
lo | 0x00000004 | 0 | 32 | RW
roce_offload_disable | 0x00000008 | 0 | 1 | RW
=================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PAOS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=========================================================================
oper_status | 0x00000000 | 0 | 4 | RO
admin_status | 0x00000000 | 8 | 4 | RW
local_port | 0x00000000 | 16 | 8 | INDEX
swid | 0x00000000 | 24 | 8 | INDEX
e | 0x00000004 | 0 | 2 | RW
fd | 0x00000004 | 8 | 1 | RW
ee | 0x00000004 | 30 | 1 | WO
ase | 0x00000004 | 31 | 1 | WO
=========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PBMC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
xoff_refresh | 0x00000004 | 0 | 16 | RW
xoff_timer_value | 0x00000004 | 16 | 16 | RW
port_buffer_size | 0x00000008 | 0 | 16 | RO
fullness_threshold | 0x00000008 | 16 | 7 | RW
size | 0x0000000c | 0 | 16 | RW
epsb | 0x0000000c | 24 | 1 | RW
lossy | 0x0000000c | 25 | 1 | RW
xon_threshold | 0x00000010 | 0 | 16 | RW
xoff_threshold | 0x00000010 | 16 | 16 | RW
size | 0x00000014 | 0 | 16 | RW
epsb | 0x00000014 | 24 | 1 | RW
lossy | 0x00000014 | 25 | 1 | RW
xon_threshold | 0x00000018 | 0 | 16 | RW
xoff_threshold | 0x00000018 | 16 | 16 | RW
size | 0x0000001c | 0 | 16 | RW
epsb | 0x0000001c | 24 | 1 | RW
lossy | 0x0000001c | 25 | 1 | RW
xon_threshold | 0x00000020 | 0 | 16 | RW
xoff_threshold | 0x00000020 | 16 | 16 | RW
size | 0x00000024 | 0 | 16 | RW
epsb | 0x00000024 | 24 | 1 | RW
lossy | 0x00000024 | 25 | 1 | RW
xon_threshold | 0x00000028 | 0 | 16 | RW
xoff_threshold | 0x00000028 | 16 | 16 | RW
size | 0x0000002c | 0 | 16 | RW
epsb | 0x0000002c | 24 | 1 | RW
lossy | 0x0000002c | 25 | 1 | RW
xon_threshold | 0x00000030 | 0 | 16 | RW
xoff_threshold | 0x00000030 | 16 | 16 | RW
size | 0x00000034 | 0 | 16 | RW
epsb | 0x00000034 | 24 | 1 | RW
lossy | 0x00000034 | 25 | 1 | RW
xon_threshold | 0x00000038 | 0 | 16 | RW
xoff_threshold | 0x00000038 | 16 | 16 | RW
size | 0x0000003c | 0 | 16 | RW
epsb | 0x0000003c | 24 | 1 | RW
lossy | 0x0000003c | 25 | 1 | RW
xon_threshold | 0x00000040 | 0 | 16 | RW
xoff_threshold | 0x00000040 | 16 | 16 | RW
size | 0x00000044 | 0 | 16 | RW
epsb | 0x00000044 | 24 | 1 | RW
lossy | 0x00000044 | 25 | 1 | RW
xon_threshold | 0x00000048 | 0 | 16 | RW
xoff_threshold | 0x00000048 | 16 | 16 | RW
size | 0x0000004c | 0 | 16 | RW
epsb | 0x0000004c | 24 | 1 | RW
lossy | 0x0000004c | 25 | 1 | RW
xon_threshold | 0x00000050 | 0 | 16 | RW
xoff_threshold | 0x00000050 | 16 | 16 | RW
size | 0x00000054 | 0 | 16 | RW
epsb | 0x00000054 | 24 | 1 | RW
lossy | 0x00000054 | 25 | 1 | RW
xon_threshold | 0x00000058 | 0 | 16 | RW
xoff_threshold | 0x00000058 | 16 | 16 | RW
hi | 0x0000005c | 0 | 32 | RW
lo | 0x00000060 | 0 | 32 | RW
hi | 0x00000064 | 0 | 32 | RW
lo | 0x00000068 | 0 | 32 | RW
===============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PBSR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
used_shared_headroom_buffer | 0x00000008 | 0 | 16 | RO
clear_wm | 0x00000008 | 31 | 1 | OP
watermark | 0x0000000c | 0 | 16 | RO
used_buffer | 0x00000010 | 0 | 16 | RO
watermark | 0x00000014 | 0 | 16 | RO
used_buffer | 0x00000018 | 0 | 16 | RO
watermark | 0x0000001c | 0 | 16 | RO
used_buffer | 0x00000020 | 0 | 16 | RO
watermark | 0x00000024 | 0 | 16 | RO
used_buffer | 0x00000028 | 0 | 16 | RO
watermark | 0x0000002c | 0 | 16 | RO
used_buffer | 0x00000030 | 0 | 16 | RO
watermark | 0x00000034 | 0 | 16 | RO
used_buffer | 0x00000038 | 0 | 16 | RO
watermark | 0x0000003c | 0 | 16 | RO
used_buffer | 0x00000040 | 0 | 16 | RO
watermark | 0x00000044 | 0 | 16 | RO
used_buffer | 0x00000048 | 0 | 16 | RO
watermark | 0x0000004c | 0 | 16 | RO
used_buffer | 0x00000050 | 0 | 16 | RO
watermark | 0x00000054 | 0 | 16 | RO
used_buffer | 0x00000058 | 0 | 16 | RO
hi | 0x0000005c | 0 | 32 | RW
lo | 0x00000060 | 0 | 32 | RW
========================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PCAM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================================
access_reg_group | 0x00000000 | 0 | 8 | INDEX
feature_group | 0x00000000 | 16 | 8 | INDEX
port_access_reg_cap_mask[0] | 0x00000008 | 0 | 32 | RO
port_access_reg_cap_mask[1] | 0x0000000c | 0 | 32 | RO
port_access_reg_cap_mask[2] | 0x00000010 | 0 | 32 | RO
port_access_reg_cap_mask[3] | 0x00000014 | 0 | 32 | RO
feature_cap_mask[0] | 0x00000028 | 0 | 32 | RO
feature_cap_mask[1] | 0x0000002c | 0 | 32 | RO
feature_cap_mask[2] | 0x00000030 | 0 | 32 | RO
feature_cap_mask[3] | 0x00000034 | 0 | 32 | RO
========================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PCAP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
====================================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
cm2_en | 0x00000000 | 31 | 1 | RW
port_capability_mask[0] | 0x00000004 | 0 | 32 | RW
port_capability_mask[1] | 0x00000008 | 0 | 32 | RW
port_capability_mask[2] | 0x0000000c | 0 | 32 | RW
port_capability_mask[3] | 0x00000010 | 0 | 32 | RW
====================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PCMR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
fcs_cap | 0x00000004 | 1 | 1 | RO
rx_ts_over_crc_cap | 0x00000004 | 13 | 1 | RO
rx_fcs_drop_cap | 0x00000004 | 14 | 1 | RO
tx_fcs_recalc_cap | 0x00000004 | 15 | 1 | RO
tx_ts_over_crc_cap | 0x00000004 | 16 | 1 | RW
entropy_gre_calc_cap | 0x00000004 | 29 | 1 | RO
entropy_calc_cap | 0x00000004 | 30 | 1 | RO
force_entropy_cap | 0x00000004 | 31 | 1 | RO
fcs_chk | 0x00000008 | 1 | 1 | RW
rx_ts_over_crc | 0x00000008 | 13 | 1 | RW
rx_fcs_drop | 0x00000008 | 14 | 1 | RW
tx_fcs_recalc | 0x00000008 | 15 | 1 | RW
tx_ts_over_crc | 0x00000008 | 16 | 1 | RW
entropy_gre_calc | 0x00000008 | 29 | 1 | RW
entropy_calc | 0x00000008 | 30 | 1 | RW
force_entropy | 0x00000008 | 31 | 1 | RW
=================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PDDR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================================================
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
page_select | 0x00000004 | 0 | 8 | INDEX
module_info_ext | 0x00000004 | 29 | 2 | RW
proto_active | 0x00000008 | 20 | 4 | RO
ib_phy_fsm_state | 0x0000000c | 8 | 8 | RO
eth_an_fsm_state | 0x0000000c | 16 | 8 | RW
phy_mngr_fsm_state | 0x0000000c | 24 | 8 | RO
phy_manager_link_proto_enabled | 0x00000010 | 0 | 16 | RO
phy_manager_link_width_enabled | 0x00000010 | 16 | 16 | RO
phy_manager_link_eth_enabled | 0x00000010 | 0 | 32 | RO
core_to_phy_link_proto_enabled | 0x00000014 | 0 | 16 | RO
core_to_phy_link_width_enabled | 0x00000014 | 16 | 16 | RO
core_to_phy_link_eth_enabled | 0x00000014 | 0 | 32 | RO
cable_link_speed_cap | 0x00000018 | 0 | 16 | RO
cable_link_width_cap | 0x00000018 | 16 | 16 | RO
cable_ext_eth_proto_cap | 0x00000018 | 0 | 32 | RO
link_speed_active | 0x0000001c | 0 | 16 | RO
link_width_active | 0x0000001c | 16 | 16 | RO
link_eth_active | 0x0000001c | 0 | 32 | RO
loopback_mode | 0x00000020 | 0 | 4 | RO
fec_mode_request | 0x00000024 | 0 | 16 | RO
fec_mode_active | 0x00000024 | 16 | 16 | RO
eth_100g_fec_support | 0x00000028 | 0 | 4 | RO
eth_25g_50g_fec_support | 0x00000028 | 4 | 4 | RO
group_opcode | 0x00000008 | 0 | 16 | INDEX
monitor_opcode | 0x0000000c | 0 | 16 | RW
advanced_opcode | 0x0000000c | 0 | 16 | RW
status_message[0] | 0x00000014 | 0 | 32 | RO
status_message[1] | 0x00000018 | 0 | 32 | RO
status_message[2] | 0x0000001c | 0 | 32 | RO
status_message[3] | 0x00000020 | 0 | 32 | RO
status_message[4] | 0x00000024 | 0 | 32 | RO
status_message[5] | 0x00000028 | 0 | 32 | RO
status_message[6] | 0x0000002c | 0 | 32 | RO
status_message[7] | 0x00000030 | 0 | 32 | RO
status_message[8] | 0x00000034 | 0 | 32 | RO
status_message[9] | 0x00000038 | 0 | 32 | RO
status_message[10] | 0x0000003c | 0 | 32 | RO
status_message[11] | 0x00000040 | 0 | 32 | RO
status_message[12] | 0x00000044 | 0 | 32 | RO
status_message[13] | 0x00000048 | 0 | 32 | RO
status_message[14] | 0x0000004c | 0 | 32 | RO
status_message[15] | 0x00000050 | 0 | 32 | RO
status_message[16] | 0x00000054 | 0 | 32 | RO
status_message[17] | 0x00000058 | 0 | 32 | RO
status_message[18] | 0x0000005c | 0 | 32 | RO
status_message[19] | 0x00000060 | 0 | 32 | RO
status_message[20] | 0x00000064 | 0 | 32 | RO
status_message[21] | 0x00000068 | 0 | 32 | RO
status_message[22] | 0x0000006c | 0 | 32 | RO
status_message[23] | 0x00000070 | 0 | 32 | RO
status_message[24] | 0x00000074 | 0 | 32 | RO
status_message[25] | 0x00000078 | 0 | 32 | RO
status_message[26] | 0x0000007c | 0 | 32 | RO
status_message[27] | 0x00000080 | 0 | 32 | RO
status_message[28] | 0x00000084 | 0 | 32 | RO
status_message[29] | 0x00000088 | 0 | 32 | RO
status_message[30] | 0x0000008c | 0 | 32 | RO
status_message[31] | 0x00000090 | 0 | 32 | RO
status_message[32] | 0x00000094 | 0 | 32 | RO
status_message[33] | 0x00000098 | 0 | 32 | RO
status_message[34] | 0x0000009c | 0 | 32 | RO
status_message[35] | 0x000000a0 | 0 | 32 | RO
status_message[36] | 0x000000a4 | 0 | 32 | RO
status_message[37] | 0x000000a8 | 0 | 32 | RO
status_message[38] | 0x000000ac | 0 | 32 | RO
status_message[39] | 0x000000b0 | 0 | 32 | RO
status_message[40] | 0x000000b4 | 0 | 32 | RO
status_message[41] | 0x000000b8 | 0 | 32 | RO
status_message[42] | 0x000000bc | 0 | 32 | RO
status_message[43] | 0x000000c0 | 0 | 32 | RO
status_message[44] | 0x000000c4 | 0 | 32 | RO
status_message[45] | 0x000000c8 | 0 | 32 | RO
status_message[46] | 0x000000cc | 0 | 32 | RO
status_message[47] | 0x000000d0 | 0 | 32 | RO
status_message[48] | 0x000000d4 | 0 | 32 | RO
status_message[49] | 0x000000d8 | 0 | 32 | RO
status_message[50] | 0x000000dc | 0 | 32 | RO
status_message[51] | 0x000000e0 | 0 | 32 | RO
status_message[52] | 0x000000e4 | 0 | 32 | RO
status_message[53] | 0x000000e8 | 0 | 32 | RO
status_message[54] | 0x000000ec | 0 | 32 | RO
status_message[55] | 0x000000f0 | 0 | 32 | RO
status_message[56] | 0x000000f4 | 0 | 32 | RO
status_message[57] | 0x000000f8 | 0 | 32 | RO
status_message[58] | 0x000000fc | 0 | 32 | RO
port_notifications | 0x00000008 | 0 | 8 | RO
remote_device_type | 0x00000008 | 24 | 8 | RO
lp_ib_revision | 0x0000000c | 0 | 8 | RO
ib_revision | 0x0000000c | 8 | 8 | RO
num_of_negotiation_attempts | 0x0000000c | 16 | 16 | RO
phy_manger_disable_mask | 0x00000010 | 0 | 16 | RO
hw_link_phy_state | 0x00000010 | 24 | 8 | RO
pcs_phy_state | 0x00000014 | 0 | 32 | RO
lp_proto_enabled | 0x00000018 | 0 | 32 | RO
lp_fec_mode_request | 0x0000001c | 0 | 16 | RO
lp_fec_mode_support | 0x0000001c | 16 | 16 | RO
ib_last_link_down_reason | 0x00000020 | 0 | 32 | RO
eth_last_link_down_lane[3] | 0x00000024 | 0 | 8 | RO
eth_last_link_down_lane[2] | 0x00000024 | 8 | 8 | RO
eth_last_link_down_lane[1] | 0x00000024 | 16 | 8 | RO
eth_last_link_down_lane[0] | 0x00000024 | 24 | 8 | RO
speed_deg_db | 0x0000002c | 0 | 32 | RO
degrade_grade_lane0 | 0x00000030 | 0 | 24 | RO
degrade_grade_lane1 | 0x00000034 | 0 | 24 | RO
degrade_grade_lane2 | 0x00000038 | 0 | 24 | RO
degrade_grade_lane3 | 0x0000003c | 0 | 24 | RO
kr_startup_fsm_lane[3] | 0x00000050 | 0 | 8 | RO
kr_startup_fsm_lane[2] | 0x00000050 | 8 | 8 | RO
kr_startup_fsm_lane[1] | 0x00000050 | 16 | 8 | RO
kr_startup_fsm_lane[0] | 0x00000050 | 24 | 8 | RO
eth_an_debug_indication | 0x00000058 | 0 | 32 | RO
ib_phy_fsm_state_trace | 0x0000005c | 0 | 16 | RO
kr_startup_debug_indications[1] | 0x00000060 | 0 | 16 | RO
kr_startup_debug_indications[0] | 0x00000060 | 16 | 16 | RO
kr_startup_debug_indications[3] | 0x00000064 | 0 | 16 | RO
kr_startup_debug_indications[2] | 0x00000064 | 16 | 16 | RO
irisc_status | 0x00000070 | 0 | 4 | RO
stamping_reason | 0x00000074 | 0 | 32 | RO
kr_frame_lock_tuning_failure_events_count | 0x00000078 | 0 | 32 | RO
kr_full_tuning_failure_count | 0x0000007c | 0 | 32 | RO
ethernet_compliance_code | 0x00000008 | 0 | 8 | RW
ext_ethernet_compliance_code | 0x00000008 | 8 | 8 | RW
cable_breakout | 0x00000008 | 16 | 8 | RW
cable_technology | 0x00000008 | 24 | 8 | RW
cable_power_class | 0x0000000c | 0 | 8 | RO
cable_identifier | 0x0000000c | 8 | 8 | RO
cable_length | 0x0000000c | 16 | 8 | RO
cable_vendor | 0x0000000c | 24 | 4 | RO
cable_type | 0x0000000c | 28 | 4 | RO
cable_tx_equalization | 0x00000010 | 0 | 8 | RO
cable_rx_emphasis | 0x00000010 | 8 | 8 | RO
cable_rx_amp | 0x00000010 | 16 | 8 | RO
max_power | 0x00000010 | 24 | 8 | RO
cable_attenuation_5g | 0x00000014 | 0 | 8 | RO
cable_attenuation_7g | 0x00000014 | 8 | 8 | RO
cable_attenuation_12g | 0x00000014 | 16 | 8 | RO
cable_attenuation_25g | 0x00000014 | 24 | 8 | RO
tx_cdr_state | 0x00000018 | 0 | 8 | RO
rx_cdr_state | 0x00000018 | 8 | 8 | RO
tx_cdr_cap | 0x00000018 | 16 | 4 | RO
rx_cdr_cap | 0x00000018 | 20 | 4 | RO
cable_rx_post_emphasis | 0x00000018 | 24 | 8 | RO
vendor_name[0] | 0x0000001c | 0 | 32 | RO
vendor_name[1] | 0x00000020 | 0 | 32 | RO
vendor_name[2] | 0x00000024 | 0 | 32 | RO
vendor_name[3] | 0x00000028 | 0 | 32 | RO
vendor_pn[0] | 0x0000002c | 0 | 32 | RO
vendor_pn[1] | 0x00000030 | 0 | 32 | RO
vendor_pn[2] | 0x00000034 | 0 | 32 | RO
vendor_pn[3] | 0x00000038 | 0 | 32 | RO
vendor_rev | 0x0000003c | 0 | 32 | RO
fw_version | 0x00000040 | 0 | 32 | RO
vendor_sn[0] | 0x00000044 | 0 | 32 | RO
vendor_sn[1] | 0x00000048 | 0 | 32 | RO
vendor_sn[2] | 0x0000004c | 0 | 32 | RO
vendor_sn[3] | 0x00000050 | 0 | 32 | RO
voltage | 0x00000054 | 0 | 16 | RO
temperature | 0x00000054 | 16 | 16 | RO
rx_power_lane1 | 0x00000058 | 0 | 16 | RO
rx_power_lane0 | 0x00000058 | 16 | 16 | RO
rx_power_lane3 | 0x0000005c | 0 | 16 | RO
rx_power_lane2 | 0x0000005c | 16 | 16 | RO
rx_power_lane5 | 0x00000060 | 0 | 16 | RO
rx_power_lane4 | 0x00000060 | 16 | 16 | RO
rx_power_lane7 | 0x00000064 | 0 | 16 | RO
rx_power_lane6 | 0x00000064 | 16 | 16 | RO
tx_power_lane1 | 0x00000068 | 0 | 16 | RO
tx_power_lane0 | 0x00000068 | 16 | 16 | RO
tx_power_lane3 | 0x0000006c | 0 | 16 | RO
tx_power_lane2 | 0x0000006c | 16 | 16 | RO
tx_power_lane5 | 0x00000070 | 0 | 16 | RO
tx_power_lane4 | 0x00000070 | 16 | 16 | RO
tx_power_lane7 | 0x00000074 | 0 | 16 | RO
tx_power_lane6 | 0x00000074 | 16 | 16 | RO
tx_bias_lane1 | 0x00000078 | 0 | 16 | RO
tx_bias_lane0 | 0x00000078 | 16 | 16 | RO
tx_bias_lane3 | 0x0000007c | 0 | 16 | RO
tx_bias_lane2 | 0x0000007c | 16 | 16 | RO
tx_bias_lane5 | 0x00000080 | 0 | 16 | RO
tx_bias_lane4 | 0x00000080 | 16 | 16 | RO
tx_bias_lane7 | 0x00000084 | 0 | 16 | RO
tx_bias_lane6 | 0x00000084 | 16 | 16 | RO
temperature_low_th | 0x00000088 | 0 | 16 | RO
temperature_high_th | 0x00000088 | 16 | 16 | RO
voltage_low_th | 0x0000008c | 0 | 16 | RO
voltage_high_th | 0x0000008c | 16 | 16 | RO
rx_power_low_th | 0x00000090 | 0 | 16 | RO
rx_power_high_th | 0x00000090 | 16 | 16 | RO
tx_power_low_th | 0x00000094 | 0 | 16 | RO
tx_power_high_th | 0x00000094 | 16 | 16 | RO
tx_bias_low_th | 0x00000098 | 0 | 16 | RO
tx_bias_high_th | 0x00000098 | 16 | 16 | RO
wavelength | 0x0000009c | 0 | 16 | RO
smf_length | 0x0000009c | 16 | 10 | RO
rx_power_type | 0x0000009c | 28 | 1 | RO
module_st | 0x0000009c | 29 | 3 | RO
ib_compliance_code | 0x000000a0 | 0 | 8 | RO
active_set_media_compliance_code | 0x000000a0 | 16 | 8 | RO
active_set_host_compliance_code | 0x000000a0 | 24 | 8 | RO
ib_width | 0x000000a4 | 0 | 6 | RO
monitor_cap_mask | 0x000000a4 | 8 | 8 | RO
nbr_100 | 0x000000a4 | 16 | 8 | RO
nbr_250 | 0x000000a4 | 24 | 8 | RO
dp_st_lane7 | 0x000000a8 | 0 | 4 | RO
dp_st_lane6 | 0x000000a8 | 4 | 4 | RO
dp_st_lane5 | 0x000000a8 | 8 | 4 | RO
dp_st_lane4 | 0x000000a8 | 12 | 4 | RO
dp_st_lane3 | 0x000000a8 | 16 | 4 | RO
dp_st_lane2 | 0x000000a8 | 20 | 4 | RO
dp_st_lane1 | 0x000000a8 | 24 | 4 | RO
dp_st_lane0 | 0x000000a8 | 28 | 4 | RO
length_om5 | 0x000000ac | 0 | 8 | RO
length_om4 | 0x000000ac | 8 | 8 | RO
length_om3 | 0x000000ac | 16 | 8 | RO
length_om2 | 0x000000ac | 24 | 8 | RO
memory_map_rev | 0x000000b0 | 0 | 8 | RO
wavelength_tolerance | 0x000000b0 | 8 | 16 | RO
length_om1 | 0x000000b0 | 24 | 8 | RO
hi | 0x000000b8 | 0 | 32 | RO
lo | 0x000000bc | 0 | 32 | RO
vendor_oui | 0x000000c0 | 0 | 24 | RO
connector_type | 0x000000c0 | 24 | 8 | RO
invalid_fsm_sv | 0x00000008 | 31 | 1 | RO
protocol_check | 0x0000000c | 0 | 1 | RO
protocol_check_sv | 0x0000000c | 1 | 1 | RO
pm_fifo_full | 0x0000000c | 2 | 1 | RO
pm_fifo_full_sv | 0x0000000c | 3 | 1 | RO
mod_adapt_faild | 0x0000000c | 4 | 1 | RO
mod_adapt_faild_sv | 0x0000000c | 5 | 1 | RO
mod_config_to | 0x0000000c | 6 | 1 | RO
mod_config_to_sv | 0x0000000c | 7 | 1 | RO
mod_req_busy | 0x0000000c | 8 | 1 | RO
mod_req_busy_sv | 0x0000000c | 9 | 1 | RO
mod_req_nack | 0x0000000c | 10 | 1 | RO
mod_req_nack_sv | 0x0000000c | 11 | 1 | RO
kr_false_ready | 0x0000000c | 16 | 1 | RO
kr_false_ready_sv | 0x0000000c | 17 | 1 | RO
input_event_sv | 0x00000010 | 31 | 1 | RO
qsfp_zero_atten_sv | 0x00000014 | 1 | 1 | RO
lane_mapping | 0x00000014 | 2 | 1 | RO
lane_mapping_sv | 0x00000014 | 3 | 1 | RO
init_all_gains_bad_val_sv | 0x00000018 | 1 | 1 | RO
single_gains_bad_val | 0x00000018 | 2 | 1 | RO
single_gains_bad_val_sv | 0x00000018 | 3 | 1 | RO
mono_flow_height_sv | 0x00000018 | 5 | 1 | RO
mono_reach_high_limit | 0x00000018 | 6 | 1 | RO
mono_reach_high_limit_sv | 0x00000018 | 7 | 1 | RO
mono_reach_low_limit | 0x00000018 | 8 | 1 | RO
mono_reach_low_limit_sv | 0x00000018 | 9 | 1 | RO
clr_mask[0] | 0x00000028 | 0 | 32 | OP
clr_mask[1] | 0x0000002c | 0 | 32 | OP
clr_mask[2] | 0x00000030 | 0 | 32 | OP
clr_mask[3] | 0x00000034 | 0 | 32 | OP
clr_mask[4] | 0x00000038 | 0 | 32 | OP
clr_mask[5] | 0x0000003c | 0 | 32 | OP
clr_mask[6] | 0x00000040 | 0 | 32 | OP
clr_mask[7] | 0x00000044 | 0 | 32 | OP
invalid_port_access_sv | 0x00000008 | 31 | 1 | RO
pll_state_mask_center0 | 0x0000000c | 0 | 4 | RO
pll_state_sv_0 | 0x0000000c | 8 | 1 | RO
pll_state_mask_center1 | 0x0000000c | 16 | 4 | RO
pll_state_sv_1 | 0x0000000c | 24 | 1 | RO
varactors_calib_fail_center0 | 0x00000010 | 0 | 1 | RO
varactors_calib_fail_center0_sv | 0x00000010 | 1 | 1 | RO
varactors_calib_fail_center1 | 0x00000010 | 2 | 1 | RO
varactors_calib_fail_center1_sv | 0x00000010 | 3 | 1 | RO
logical_phy_to | 0x00000010 | 4 | 1 | RO
logical_phy_to_sv | 0x00000010 | 5 | 1 | RO
analog_phy_to | 0x00000010 | 6 | 1 | RO
analog_phy_to_sv | 0x00000010 | 7 | 1 | RO
cr_space_timeout | 0x00000010 | 16 | 1 | RO
cr_space_timeout_sv | 0x00000010 | 17 | 1 | RO
cr_space_timeout_mcm_main | 0x00000010 | 18 | 1 | RO
irisc_stuck_mask_sv | 0x00000014 | 31 | 1 | RO
pll_unlocl_mask_center0 | 0x0000001c | 0 | 4 | RO
pll_lock_sv_0 | 0x0000001c | 8 | 1 | RO
pll_unlocl_mask_center1 | 0x0000001c | 16 | 4 | RO
pll_lock_sv_1 | 0x0000001c | 24 | 1 | RO
iopl_err_center0 | 0x00000020 | 0 | 1 | RO
iopl_err_center0_sv | 0x00000020 | 1 | 1 | RO
iopl_err_center1 | 0x00000020 | 2 | 1 | RO
iopl_err_center1_sv | 0x00000020 | 3 | 1 | RO
pwr_governor_err | 0x00000020 | 16 | 1 | RO
pwr_governor_err_sv | 0x00000020 | 17 | 1 | RO
clr_mask[0] | 0x00000028 | 0 | 32 | OP
clr_mask[1] | 0x0000002c | 0 | 32 | OP
clr_mask[2] | 0x00000030 | 0 | 32 | OP
clr_mask[3] | 0x00000034 | 0 | 32 | OP
clr_mask[4] | 0x00000038 | 0 | 32 | OP
clr_mask[5] | 0x0000003c | 0 | 32 | OP
clr_mask[6] | 0x00000040 | 0 | 32 | OP
clr_mask[7] | 0x00000044 | 0 | 32 | OP
down_blame | 0x00000008 | 0 | 4 | RO
local_reason_opcode | 0x0000000c | 0 | 8 | RO
remote_reason_opcode | 0x00000010 | 0 | 8 | RO
e2e_reason_opcode | 0x00000014 | 0 | 8 | RO
ber_exp | 0x00000018 | 0 | 8 | RO
ber_mantissa | 0x00000018 | 8 | 4 | RO
last_ber_exp | 0x00000018 | 16 | 8 | RO
last_ber_mantissa | 0x00000018 | 24 | 4 | RO
max_ber_exp | 0x0000001c | 0 | 8 | RO
max_ber_mantissa | 0x0000001c | 8 | 4 | RO
min_ber_exp | 0x0000001c | 16 | 8 | RO
min_ber_mantissa | 0x0000001c | 24 | 4 | RO
num_of_ber_alarams | 0x00000020 | 0 | 16 | RO
ib_port_events | 0x00000008 | 0 | 32 | RO
etherent_port_events | 0x00000010 | 0 | 32 | RO
general_port_events | 0x00000018 | 0 | 32 | RO
up_reason_mng | 0x00000008 | 0 | 4 | RO
up_reason_drv | 0x00000008 | 8 | 4 | RO
up_reason_pwr | 0x00000008 | 16 | 4 | RO
time_to_link_up | 0x0000000c | 0 | 16 | RO
fast_link_up_status | 0x00000010 | 0 | 4 | RO
dp_fw_fault | 0x00000008 | 22 | 1 | RO
mod_fw_fault | 0x00000008 | 23 | 1 | RO
vcc_flags | 0x00000008 | 24 | 4 | RO
temp_flags | 0x00000008 | 28 | 4 | RO
tx_ad_eq_fault | 0x0000000c | 0 | 8 | RO
tx_cdr_lol | 0x0000000c | 8 | 8 | RO
tx_los | 0x0000000c | 16 | 8 | RO
tx_fault | 0x0000000c | 24 | 8 | RO
tx_power_lo_war | 0x00000010 | 0 | 8 | RO
tx_power_hi_war | 0x00000010 | 8 | 8 | RO
tx_power_lo_al | 0x00000010 | 16 | 8 | RO
tx_power_hi_al | 0x00000010 | 24 | 8 | RO
tx_bias_lo_war | 0x00000014 | 0 | 8 | RO
tx_bias_hi_war | 0x00000014 | 8 | 8 | RO
tx_bias_lo_al | 0x00000014 | 16 | 8 | RO
tx_bias_hi_al | 0x00000014 | 24 | 8 | RO
rx_cdr_lol | 0x00000018 | 16 | 8 | RO
rx_los | 0x00000018 | 24 | 8 | RO
rx_power_lo_war | 0x0000001c | 0 | 8 | RO
rx_power_hi_war | 0x0000001c | 8 | 8 | RO
rx_power_lo_al | 0x0000001c | 16 | 8 | RO
rx_power_hi_al | 0x0000001c | 24 | 8 | RO
tracer_enable | 0x00000008 | 0 | 1 | WO
reset_tracer | 0x00000008 | 1 | 1 | RW
tracer_mode | 0x00000008 | 2 | 3 | INDEX
pre_trigger_buff_mode | 0x00000008 | 5 | 3 | INDEX
trigger_cond_fsm | 0x00000008 | 8 | 5 | INDEX
trigger_cond_state_or_event | 0x00000008 | 13 | 1 | INDEX
trigger_cond_state_event_val | 0x00000008 | 14 | 7 | INDEX
trigger_active | 0x00000008 | 21 | 1 | RO
pport | 0x00000008 | 22 | 8 | INDEX
fsm_mask | 0x0000000c | 0 | 32 | INDEX
buffer_size | 0x00000010 | 0 | 12 | RO
trigger_ptr | 0x00000010 | 12 | 12 | RO
ptr_next_write | 0x00000014 | 0 | 12 | RO
ptr_log_data | 0x00000014 | 12 | 12 | RO
buffer_base_address | 0x00000018 | 0 | 32 | RO
cause_fec_rx_sync_m_reached_max0 | 0x00000008 | 0 | 8 | RO
cause_deskew_fifo_overrun | 0x00000008 | 8 | 8 | RO
cause_tx_lane_fifo_underrun_l0 | 0x00000008 | 16 | 2 | RO
cause_rs_rx_lane0_symbol_error | 0x00000008 | 18 | 2 | RO
cause_high_ser | 0x00000008 | 20 | 2 | RO
cause_as_detected_not_on_slot | 0x00000008 | 22 | 2 | RO
symbol_error_counter_lo | 0x0000000c | 0 | 32 | RO
symbol_error_counter_hi | 0x00000010 | 0 | 32 | RO
uncorrectable_block_counter_lo | 0x00000014 | 0 | 32 | RO
uncorrectable_block_counter_hi | 0x00000018 | 0 | 32 | RO
block_lock_mask_at_fail_port0 | 0x0000001c | 0 | 4 | RO
block_lock_mask_at_fail_port1 | 0x0000001c | 4 | 4 | RO
link_fail_due_align_loss | 0x0000001c | 8 | 1 | RO
link_down_counter | 0x00000020 | 0 | 32 | RO
raw_ber_magnitude | 0x00000024 | 0 | 4 | RO
raw_ber_coef | 0x00000024 | 4 | 8 | RO
effective_ber_magnitude | 0x00000024 | 12 | 4 | RO
effective_ber_coef | 0x00000024 | 16 | 8 | RO
cause_deskew_fifo_overrun | 0x00000008 | 0 | 8 | RO
cause_fec_rx_sync_m_reached_max0 | 0x00000008 | 8 | 8 | RO
cause_lane_underrun_l0 | 0x00000008 | 16 | 2 | RO
cause_push_overrun_s0 | 0x00000008 | 18 | 2 | RO
cause_usr_align_lost | 0x00000008 | 20 | 2 | RO
fec_uncorrectable_block_lane0_counter_lo | 0x0000000c | 0 | 32 | RO
fec_uncorrectable_block_lane1_counter_lo | 0x00000010 | 0 | 32 | RO
fec_uncorrectable_block_lane2_counter_lo | 0x00000014 | 0 | 32 | RO
fec_uncorrectable_block_lane3_counter_lo | 0x00000018 | 0 | 32 | RO
fec_uncorrectable_block_lane4_counter_lo | 0x0000001c | 0 | 32 | RO
fec_uncorrectable_block_lane5_counter_lo | 0x00000020 | 0 | 32 | RO
fec_uncorrectable_block_lane6_counter_lo | 0x00000024 | 0 | 32 | RO
fec_uncorrectable_block_lane7_counter_lo | 0x00000028 | 0 | 32 | RO
link_down_counter | 0x0000002c | 0 | 32 | RO
raw_ber_magnitude | 0x00000030 | 0 | 4 | RO
raw_ber_coef | 0x00000030 | 4 | 8 | RO
effective_ber_magnitude | 0x00000030 | 12 | 4 | RO
effective_ber_coef | 0x00000030 | 16 | 8 | RO
usr_get_logic_reset_toggled | 0x00000030 | 24 | 1 | RO
cause_deskew_fifo_overrun | 0x00000008 | 0 | 8 | RO
cause_fec_rx_sync_m_reached_max0 | 0x00000008 | 8 | 8 | RO
cause_credit_preemption_fifo_overrun | 0x00000008 | 16 | 2 | RO
cause_tx_lane_fifo_underrun_l0 | 0x00000008 | 18 | 2 | RO
cause_plu_tx_ports_buffer_overrun | 0x00000008 | 20 | 2 | RO
cause_port0_framer_rx_fifo_overrun0 | 0x00000008 | 22 | 1 | RO
cause_port1_framer_rx_fifo_overrun0 | 0x00000008 | 23 | 1 | RO
cause_framer_pad_dw_2_ddw_remainder_overrun_p0s0 | 0x00000008 | 24 | 1 | RO
cause_framer_pad_dw_2_ddw_remainder_overrun_p1s0 | 0x00000008 | 25 | 1 | RO
cause_ptp_fifo_overrun_p0s0 | 0x00000008 | 26 | 1 | RO
cause_ptp_fifo_overrun_p1s0 | 0x00000008 | 27 | 1 | RO
cause_mode8x_mtu_violation | 0x00000008 | 28 | 1 | RO
cause_lane_underrun_l0 | 0x00000008 | 29 | 2 | RO
cause_push_overrun_s0 | 0x0000000c | 0 | 2 | RO
cause_rx_local_fault | 0x0000000c | 2 | 2 | RO
cause_rx_remote_fault | 0x0000000c | 4 | 2 | RO
cause_rx_remote_fault_on_linkup | 0x0000000c | 6 | 2 | RO
link_goes_down_xaui_xfi | 0x0000000c | 8 | 2 | RO
cause_preamble8_fail | 0x0000000c | 10 | 2 | RO
cause_usr_align_lost | 0x0000000c | 12 | 2 | RO
symbol_error_counter_lo | 0x00000010 | 0 | 32 | RO
symbol_error_counter_hi | 0x00000014 | 0 | 32 | RO
fec_uncorrectable_block_lane0_counter_lo | 0x00000018 | 0 | 32 | RO
fec_uncorrectable_block_lane1_counter_lo | 0x0000001c | 0 | 32 | RO
fec_uncorrectable_block_lane2_counter_lo | 0x00000020 | 0 | 32 | RO
fec_uncorrectable_block_lane3_counter_lo | 0x00000024 | 0 | 32 | RO
fec_uncorrectable_block_lane4_counter_lo | 0x00000028 | 0 | 32 | RO
fec_uncorrectable_block_lane5_counter_lo | 0x0000002c | 0 | 32 | RO
fec_uncorrectable_block_lane6_counter_lo | 0x00000030 | 0 | 32 | RO
fec_uncorrectable_block_lane7_counter_lo | 0x00000034 | 0 | 32 | RO
link_down_counter | 0x00000038 | 0 | 32 | RO
raw_ber_magnitude | 0x0000003c | 0 | 4 | RO
raw_ber_coef | 0x0000003c | 4 | 8 | RO
effective_ber_magnitude | 0x0000003c | 12 | 4 | RO
effective_ber_coef | 0x0000003c | 16 | 8 | RO
usr_get_logic_reset_toggled | 0x0000003c | 24 | 1 | RO
=============================================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PFCC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
============================================================================================
shl_opr | 0x00000000 | 0 | 1 | RW
shl_cap | 0x00000000 | 1 | 1 | RO
critical_stall_mask | 0x00000000 | 2 | 1 | WO
minor_stall_mask | 0x00000000 | 3 | 1 | WO
ppan_mask_n | 0x00000000 | 4 | 1 | WO
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
set_buf_ownership | 0x00000000 | 24 | 2 | WO
buf_ownership | 0x00000000 | 26 | 2 | RO
cap_remote_admin | 0x00000000 | 28 | 1 | RO
cap_local_admin | 0x00000000 | 29 | 1 | RO
dcbx_operation_type | 0x00000000 | 30 | 2 | INDEX
prio_mask_rx | 0x00000004 | 0 | 8 | WO
prio_mask_tx | 0x00000004 | 16 | 8 | WO
ppan | 0x00000004 | 28 | 4 | RW
fctx_disabled | 0x00000008 | 8 | 1 | RO
pfctx | 0x00000008 | 16 | 8 | RW
pptx_mask_n | 0x00000008 | 29 | 1 | WO
aptx | 0x00000008 | 30 | 1 | RO
pptx | 0x00000008 | 31 | 1 | RW
pfcrx | 0x0000000c | 16 | 8 | RW
pprx_mask_n | 0x0000000c | 29 | 1 | WO
aprx | 0x0000000c | 30 | 1 | RO
pprx | 0x0000000c | 31 | 1 | RW
device_stall_critical_watermark | 0x00000010 | 0 | 16 | RW
device_stall_minor_watermark | 0x00000010 | 16 | 16 | RW
============================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PGMR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
======================================================================================
pg_sel | 0x00000000 | 0 | 1 | OP
group | 0x00000000 | 8 | 4 | INDEX
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
version | 0x00000000 | 24 | 4 | RO
status | 0x00000000 | 28 | 4 | RO
group_of_port | 0x00000004 | 4 | 4 | RW
ports_mapping_of_group[0] | 0x00000008 | 0 | 32 | RW
ports_mapping_of_group[1] | 0x0000000c | 0 | 32 | RW
ports_mapping_of_group[2] | 0x00000010 | 0 | 32 | RW
ports_mapping_of_group[3] | 0x00000014 | 0 | 32 | RW
======================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PGUID
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
sys_guid[0] | 0x00000004 | 0 | 32 | RO
sys_guid[1] | 0x00000008 | 0 | 32 | RO
sys_guid[2] | 0x0000000c | 0 | 32 | RO
sys_guid[3] | 0x00000010 | 0 | 32 | RO
node_guid[0] | 0x00000014 | 0 | 32 | RO
node_guid[1] | 0x00000018 | 0 | 32 | RO
node_guid[2] | 0x0000001c | 0 | 32 | RO
node_guid[3] | 0x00000020 | 0 | 32 | RO
port_guid[0] | 0x00000024 | 0 | 32 | RO
port_guid[1] | 0x00000028 | 0 | 32 | RO
port_guid[2] | 0x0000002c | 0 | 32 | RO
port_guid[3] | 0x00000030 | 0 | 32 | RO
allocated_guid[0] | 0x00000034 | 0 | 32 | RO
allocated_guid[1] | 0x00000038 | 0 | 32 | RO
allocated_guid[2] | 0x0000003c | 0 | 32 | RO
allocated_guid[3] | 0x00000040 | 0 | 32 | RO
==============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PMAOS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=====================================================================================
oper_status | 0x00000000 | 0 | 4 | RO
admin_status | 0x00000000 | 8 | 4 | RW
module | 0x00000000 | 16 | 8 | INDEX
slot_index | 0x00000000 | 24 | 4 | INDEX
rst | 0x00000000 | 31 | 1 | OP
e | 0x00000004 | 0 | 2 | RW
error_type | 0x00000004 | 8 | 4 | RO
operational_notification | 0x00000004 | 16 | 4 | RO
ee | 0x00000004 | 30 | 1 | WO
ase | 0x00000004 | 31 | 1 | WO
=====================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PMCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
cs_sel | 0x00000000 | 24 | 2 | INDEX
cdr_override_cntl | 0x00000004 | 0 | 2 | RW
cdr_override_value | 0x00000004 | 8 | 4 | RW
tx_disable_override_cntl | 0x00000004 | 16 | 2 | RW
tx_disable_override_value | 0x00000004 | 24 | 2 | RW
rx_amp_override_cntl | 0x00000008 | 0 | 2 | RW
rx_amp_override_value | 0x00000008 | 8 | 4 | RW
rx_los_override_cntl | 0x00000008 | 16 | 2 | RW
rx_los_override_admin | 0x00000008 | 24 | 2 | RW
rx_emp_override_cntl | 0x0000000c | 0 | 2 | RW
rx_emp_override_value | 0x0000000c | 8 | 4 | RW
tx_equ_override_cntl | 0x00000010 | 0 | 2 | RW
tx_equ_override_value | 0x00000010 | 8 | 4 | RW
tx_adaptive_override_cntrl | 0x00000010 | 24 | 2 | RW
ap_sel_override_cntrl | 0x00000018 | 0 | 2 | RW
ap_sel_override_value | 0x00000018 | 8 | 4 | RW
si_override_cntrl | 0x00000018 | 24 | 2 | RW
=======================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PMLP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================================
width | 0x00000000 | 0 | 8 | RW
local_port | 0x00000000 | 16 | 8 | INDEX
m_lane_m | 0x00000000 | 28 | 1 | OP
rxtx | 0x00000000 | 31 | 1 | RW
lane0_module_mapping | 0x00000004 | 0 | 32 | RW
lane1_module_mapping | 0x00000008 | 0 | 32 | RW
lane2_module_mapping | 0x0000000c | 0 | 32 | RW
lane3_module_mapping | 0x00000010 | 0 | 32 | RW
lane4_module_mapping | 0x00000014 | 0 | 32 | RW
lane5_module_mapping | 0x00000018 | 0 | 32 | RW
lane6_module_mapping | 0x0000001c | 0 | 32 | RW
lane7_module_mapping | 0x00000020 | 0 | 32 | RW
=================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PMMP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================================
module | 0x00000000 | 16 | 8 | INDEX
slot_index | 0x00000000 | 24 | 4 | INDEX
eeprom_override | 0x00000004 | 0 | 16 | RW
eeprom_override_mask | 0x00000004 | 16 | 16 | WO
qsfp_cable_protocol_technology[0] | 0x00000008 | 0 | 32 | RW
qsfp_cable_protocol_technology[1] | 0x0000000c | 0 | 32 | RW
qsfp_cable_protocol_technology[2] | 0x00000010 | 0 | 32 | RW
sfp_cable_protocol_technology[0] | 0x00000014 | 0 | 32 | RW
sfp_cable_protocol_technology[1] | 0x00000018 | 0 | 32 | RW
sfp_cable_protocol_technology[2] | 0x0000001c | 0 | 32 | RW
cable_length | 0x00000020 | 0 | 8 | RW
attenuation_5g | 0x00000024 | 0 | 8 | RW
attenuation_7g | 0x00000024 | 8 | 8 | RW
attenuation_12g | 0x00000024 | 16 | 8 | RW
attenuation_25g | 0x00000024 | 24 | 8 | RW
==============================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PMTU
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
max_mtu | 0x00000004 | 16 | 16 | RO
admin_mtu | 0x00000008 | 16 | 16 | RW
oper_mtu | 0x0000000c | 16 | 16 | RO
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PORT_STATE_BEHAVIOR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================================
enforce_port_state_enabled | 0x00000000 | 31 | 1 | RW
=======================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg POWER_SETTINGS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================================
power_settings_level | 0x00000000 | 0 | 8 | RW
=================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PPAD
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
============================================================================
mac_47_32 | 0x00000000 | 0 | 16 | RW
local_port | 0x00000000 | 16 | 8 | INDEX
single_base_mac | 0x00000000 | 28 | 1 | OP
mac_31_0 | 0x00000004 | 0 | 32 | RW
============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PPAOS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================================
phy_test_mode_status | 0x00000000 | 0 | 4 | RO
phy_test_mode_admin | 0x00000000 | 8 | 4 | RW
local_port | 0x00000000 | 16 | 8 | INDEX
swid | 0x00000000 | 24 | 8 | INDEX
=================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PPCNT
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================================================
grp | 0x00000000 | 0 | 6 | INDEX
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
swid | 0x00000000 | 24 | 8 | INDEX
prio_tc | 0x00000004 | 0 | 5 | INDEX
clr | 0x00000004 | 31 | 1 | OP
a_frames_transmitted_ok_high | 0x00000008 | 0 | 32 | RO
a_frames_transmitted_ok_low | 0x0000000c | 0 | 32 | RO
a_frames_received_ok_high | 0x00000010 | 0 | 32 | RO
a_frames_received_ok_low | 0x00000014 | 0 | 32 | RO
a_frame_check_sequence_errors_high | 0x00000018 | 0 | 32 | RO
a_frame_check_sequence_errors_low | 0x0000001c | 0 | 32 | RO
a_alignment_errors_high | 0x00000020 | 0 | 32 | RO
a_alignment_errors_low | 0x00000024 | 0 | 32 | RO
a_octets_transmitted_ok_high | 0x00000028 | 0 | 32 | RO
a_octets_transmitted_ok_low | 0x0000002c | 0 | 32 | RO
a_octets_received_ok_high | 0x00000030 | 0 | 32 | RO
a_octets_received_ok_low | 0x00000034 | 0 | 32 | RO
a_multicast_frames_xmitted_ok_high | 0x00000038 | 0 | 32 | RO
a_multicast_frames_xmitted_ok_low | 0x0000003c | 0 | 32 | RO
a_broadcast_frames_xmitted_ok_high | 0x00000040 | 0 | 32 | RO
a_broadcast_frames_xmitted_ok_low | 0x00000044 | 0 | 32 | RO
a_multicast_frames_received_ok_high | 0x00000048 | 0 | 32 | RO
a_multicast_frames_received_ok_low | 0x0000004c | 0 | 32 | RO
a_broadcast_frames_received_ok_high | 0x00000050 | 0 | 32 | RO
a_broadcast_frames_received_ok_low | 0x00000054 | 0 | 32 | RO
a_in_range_length_errors_high | 0x00000058 | 0 | 32 | RO
a_in_range_length_errors_low | 0x0000005c | 0 | 32 | RO
a_out_of_range_length_field_high | 0x00000060 | 0 | 32 | RO
a_out_of_range_length_field_low | 0x00000064 | 0 | 32 | RO
a_frame_too_long_errors_high | 0x00000068 | 0 | 32 | RO
a_frame_too_long_errors_low | 0x0000006c | 0 | 32 | RO
a_symbol_error_during_carrier_high | 0x00000070 | 0 | 32 | RO
a_symbol_error_during_carrier_low | 0x00000074 | 0 | 32 | RO
a_mac_control_frames_transmitted_high | 0x00000078 | 0 | 32 | RO
a_mac_control_frames_transmitted_low | 0x0000007c | 0 | 32 | RO
a_mac_control_frames_received_high | 0x00000080 | 0 | 32 | RO
a_mac_control_frames_received_low | 0x00000084 | 0 | 32 | RO
a_unsupported_opcodes_received_high | 0x00000088 | 0 | 32 | RO
a_unsupported_opcodes_received_low | 0x0000008c | 0 | 32 | RO
a_pause_mac_ctrl_frames_received_high | 0x00000090 | 0 | 32 | RO
a_pause_mac_ctrl_frames_received_low | 0x00000094 | 0 | 32 | RO
a_pause_mac_ctrl_frames_transmitted_high | 0x00000098 | 0 | 32 | RO
a_pause_mac_ctrl_frames_transmitted_low | 0x0000009c | 0 | 32 | RO
if_in_octets_high | 0x00000008 | 0 | 32 | RO
if_in_octets_low | 0x0000000c | 0 | 32 | RO
if_in_ucast_pkts_high | 0x00000010 | 0 | 32 | RO
if_in_ucast_pkts_low | 0x00000014 | 0 | 32 | RO
if_in_discards_high | 0x00000018 | 0 | 32 | RO
if_in_discards_low | 0x0000001c | 0 | 32 | RO
if_in_errors_high | 0x00000020 | 0 | 32 | RO
if_in_errors_low | 0x00000024 | 0 | 32 | RO
if_in_unknown_protos_high | 0x00000028 | 0 | 32 | RO
if_in_unknown_protos_low | 0x0000002c | 0 | 32 | RO
if_out_octets_high | 0x00000030 | 0 | 32 | RO
if_out_octets_low | 0x00000034 | 0 | 32 | RO
if_out_ucast_pkts_high | 0x00000038 | 0 | 32 | RO
if_out_ucast_pkts_low | 0x0000003c | 0 | 32 | RO
if_out_discards_high | 0x00000040 | 0 | 32 | RO
if_out_discards_low | 0x00000044 | 0 | 32 | RO
if_out_errors_high | 0x00000048 | 0 | 32 | RO
if_out_errors_low | 0x0000004c | 0 | 32 | RO
if_in_multicast_pkts_high | 0x00000050 | 0 | 32 | RO
if_in_multicast_pkts_low | 0x00000054 | 0 | 32 | RO
if_in_broadcast_pkts_high | 0x00000058 | 0 | 32 | RO
if_in_broadcast_pkts_low | 0x0000005c | 0 | 32 | RO
if_out_multicast_pkts_high | 0x00000060 | 0 | 32 | RO
if_out_multicast_pkts_low | 0x00000064 | 0 | 32 | RO
if_out_broadcast_pkts_high | 0x00000068 | 0 | 32 | RO
if_out_broadcast_pkts_low | 0x0000006c | 0 | 32 | RO
ether_stats_drop_events_high | 0x00000008 | 0 | 32 | RO
ether_stats_drop_events_low | 0x0000000c | 0 | 32 | RO
ether_stats_octets_high | 0x00000010 | 0 | 32 | RO
ether_stats_octets_low | 0x00000014 | 0 | 32 | RO
ether_stats_pkts_high | 0x00000018 | 0 | 32 | RO
ether_stats_pkts_low | 0x0000001c | 0 | 32 | RO
ether_stats_broadcast_pkts_high | 0x00000020 | 0 | 32 | RO
ether_stats_broadcast_pkts_low | 0x00000024 | 0 | 32 | RO
ether_stats_multicast_pkts_high | 0x00000028 | 0 | 32 | RO
ether_stats_multicast_pkts_low | 0x0000002c | 0 | 32 | RO
ether_stats_crc_align_errors_high | 0x00000030 | 0 | 32 | RO
ether_stats_crc_align_errors_low | 0x00000034 | 0 | 32 | RO
ether_stats_undersize_pkts_high | 0x00000038 | 0 | 32 | RO
ether_stats_undersize_pkts_low | 0x0000003c | 0 | 32 | RO
ether_stats_oversize_pkts_high | 0x00000040 | 0 | 32 | RO
ether_stats_oversize_pkts_low | 0x00000044 | 0 | 32 | RO
ether_stats_fragments_high | 0x00000048 | 0 | 32 | RO
ether_stats_fragments_low | 0x0000004c | 0 | 32 | RO
ether_stats_jabbers_high | 0x00000050 | 0 | 32 | RO
ether_stats_jabbers_low | 0x00000054 | 0 | 32 | RO
ether_stats_collisions_high | 0x00000058 | 0 | 32 | RO
ether_stats_collisions_low | 0x0000005c | 0 | 32 | RO
ether_stats_pkts64octets_high | 0x00000060 | 0 | 32 | RO
ether_stats_pkts64octets_low | 0x00000064 | 0 | 32 | RO
ether_stats_pkts65to127octets_high | 0x00000068 | 0 | 32 | RO
ether_stats_pkts65to127octets_low | 0x0000006c | 0 | 32 | RO
ether_stats_pkts128to255octets_high | 0x00000070 | 0 | 32 | RO
ether_stats_pkts128to255octets_low | 0x00000074 | 0 | 32 | RO
ether_stats_pkts256to511octets_high | 0x00000078 | 0 | 32 | RO
ether_stats_pkts256to511octets_low | 0x0000007c | 0 | 32 | RO
ether_stats_pkts512to1023octets_high | 0x00000080 | 0 | 32 | RO
ether_stats_pkts512to1023octets_low | 0x00000084 | 0 | 32 | RO
ether_stats_pkts1024to1518octets_high | 0x00000088 | 0 | 32 | RO
ether_stats_pkts1024to1518octets_low | 0x0000008c | 0 | 32 | RO
ether_stats_pkts1519to2047octets_high | 0x00000090 | 0 | 32 | RO
ether_stats_pkts1519to2047octets_low | 0x00000094 | 0 | 32 | RO
ether_stats_pkts2048to4095octets_high | 0x00000098 | 0 | 32 | RO
ether_stats_pkts2048to4095octets_low | 0x0000009c | 0 | 32 | RO
ether_stats_pkts4096to8191octets_high | 0x000000a0 | 0 | 32 | RO
ether_stats_pkts4096to8191octets_low | 0x000000a4 | 0 | 32 | RO
ether_stats_pkts8192to10239octets_high | 0x000000a8 | 0 | 32 | RO
ether_stats_pkts8192to10239octets_low | 0x000000ac | 0 | 32 | RO
dot3stats_alignment_errors_high | 0x00000008 | 0 | 32 | RW
dot3stats_alignment_errors_low | 0x0000000c | 0 | 32 | RW
dot3stats_fcs_errors_high | 0x00000010 | 0 | 32 | RW
dot3stats_fcs_errors_low | 0x00000014 | 0 | 32 | RW
dot3stats_single_collision_frames_high | 0x00000018 | 0 | 32 | RW
dot3stats_single_collision_frames_low | 0x0000001c | 0 | 32 | RW
dot3stats_multiple_collision_frames_high | 0x00000020 | 0 | 32 | RW
dot3stats_multiple_collision_frames_low | 0x00000024 | 0 | 32 | RW
dot3stats_sqe_test_errors_high | 0x00000028 | 0 | 32 | RW
dot3stats_sqe_test_errors_low | 0x0000002c | 0 | 32 | RW
dot3stats_deferred_transmissions_high | 0x00000030 | 0 | 32 | RW
dot3stats_deferred_transmissions_low | 0x00000034 | 0 | 32 | RW
dot3stats_late_collisions_high | 0x00000038 | 0 | 32 | RW
dot3stats_late_collisions_low | 0x0000003c | 0 | 32 | RW
dot3stats_excessive_collisions_high | 0x00000040 | 0 | 32 | RW
dot3stats_excessive_collisions_low | 0x00000044 | 0 | 32 | RW
dot3stats_internal_mac_transmit_errors_high | 0x00000048 | 0 | 32 | RW
dot3stats_internal_mac_transmit_errors_low | 0x0000004c | 0 | 32 | RW
dot3stats_carrier_sense_errors_high | 0x00000050 | 0 | 32 | RW
dot3stats_carrier_sense_errors_low | 0x00000054 | 0 | 32 | RW
dot3stats_frame_too_longs_high | 0x00000058 | 0 | 32 | RW
dot3stats_frame_too_longs_low | 0x0000005c | 0 | 32 | RW
dot3stats_internal_mac_receive_errors_high | 0x00000060 | 0 | 32 | RW
dot3stats_internal_mac_receive_errors_low | 0x00000064 | 0 | 32 | RW
dot3stats_symbol_errors_high | 0x00000068 | 0 | 32 | RW
dot3stats_symbol_errors_low | 0x0000006c | 0 | 32 | RW
dot3control_in_unknown_opcodes_high | 0x00000070 | 0 | 32 | RW
dot3control_in_unknown_opcodes_low | 0x00000074 | 0 | 32 | RW
dot3in_pause_frames_high | 0x00000078 | 0 | 32 | RW
dot3in_pause_frames_low | 0x0000007c | 0 | 32 | RW
dot3out_pause_frames_high | 0x00000080 | 0 | 32 | RW
dot3out_pause_frames_low | 0x00000084 | 0 | 32 | RW
port_transmit_wait_high | 0x00000008 | 0 | 32 | RO
port_transmit_wait_low | 0x0000000c | 0 | 32 | RO
ecn_marked_high | 0x00000010 | 0 | 32 | RO
ecn_marked_low | 0x00000014 | 0 | 32 | RO
no_buffer_discard_mc_high | 0x00000018 | 0 | 32 | RO
no_buffer_discard_mc_low | 0x0000001c | 0 | 32 | RO
rx_ebp_high | 0x00000020 | 0 | 32 | RO
rx_ebp_low | 0x00000024 | 0 | 32 | RO
tx_ebp_high | 0x00000028 | 0 | 32 | RO
tx_ebp_low | 0x0000002c | 0 | 32 | RO
rx_buffer_almost_full_high | 0x00000030 | 0 | 32 | RO
rx_buffer_almost_full_low | 0x00000034 | 0 | 32 | RO
rx_buffer_full_high | 0x00000038 | 0 | 32 | RO
rx_buffer_full_low | 0x0000003c | 0 | 32 | RO
rx_icrc_encapsulated_high | 0x00000040 | 0 | 32 | RO
rx_icrc_encapsulated_low | 0x00000044 | 0 | 32 | RO
tx_stats_pkts64octets_high | 0x00000058 | 0 | 32 | RO
tx_stats_pkts64octets_low | 0x0000005c | 0 | 32 | RO
tx_stats_pkts65to127octets_high | 0x00000060 | 0 | 32 | RO
tx_stats_pkts65to127octets_low | 0x00000064 | 0 | 32 | RO
tx_stats_pkts128to255octets_high | 0x00000068 | 0 | 32 | RO
tx_stats_pkts128to255octets_low | 0x0000006c | 0 | 32 | RO
tx_stats_pkts256to511octets_high | 0x00000070 | 0 | 32 | RO
tx_stats_pkts256to511octets_low | 0x00000074 | 0 | 32 | RO
tx_stats_pkts512to1023octets_high | 0x00000078 | 0 | 32 | RO
tx_stats_pkts512to1023octets_low | 0x0000007c | 0 | 32 | RO
tx_stats_pkts1024to1518octets_high | 0x00000080 | 0 | 32 | RO
tx_stats_pkts1024to1518octets_low | 0x00000084 | 0 | 32 | RO
tx_stats_pkts1519to2047octets_high | 0x00000088 | 0 | 32 | RO
tx_stats_pkts1519to2047octets_low | 0x0000008c | 0 | 32 | RO
tx_stats_pkts2048to4095octets_high | 0x00000090 | 0 | 32 | RO
tx_stats_pkts2048to4095octets_low | 0x00000094 | 0 | 32 | RO
tx_stats_pkts4096to8191octets_high | 0x00000098 | 0 | 32 | RO
tx_stats_pkts4096to8191octets_low | 0x0000009c | 0 | 32 | RO
tx_stats_pkts8192to10239octets_high | 0x000000a0 | 0 | 32 | RO
tx_stats_pkts8192to10239octets_low | 0x000000a4 | 0 | 32 | RO
ingress_general_high | 0x00000008 | 0 | 32 | RO
ingress_general_low | 0x0000000c | 0 | 32 | RO
ingress_policy_engine_high | 0x00000010 | 0 | 32 | RO
ingress_policy_engine_low | 0x00000014 | 0 | 32 | RO
ingress_vlan_membership_high | 0x00000018 | 0 | 32 | RO
ingress_vlan_membership_low | 0x0000001c | 0 | 32 | RO
ingress_tag_frame_type_high | 0x00000020 | 0 | 32 | RO
ingress_tag_frame_type_low | 0x00000024 | 0 | 32 | RO
egress_vlan_membership_high | 0x00000028 | 0 | 32 | RO
egress_vlan_membership_low | 0x0000002c | 0 | 32 | RO
loopback_filter_high | 0x00000030 | 0 | 32 | RO
loopback_filter_low | 0x00000034 | 0 | 32 | RO
egress_general_high | 0x00000038 | 0 | 32 | RO
egress_general_low | 0x0000003c | 0 | 32 | RO
egress_hoq_high | 0x00000048 | 0 | 32 | RO
egress_hoq_low | 0x0000004c | 0 | 32 | RO
port_isolation_high | 0x00000050 | 0 | 32 | RO
port_isolation_low | 0x00000054 | 0 | 32 | RO
egress_policy_engine_high | 0x00000058 | 0 | 32 | RO
egress_policy_engine_low | 0x0000005c | 0 | 32 | RO
ingress_tx_link_down_high | 0x00000060 | 0 | 32 | RO
ingress_tx_link_down_low | 0x00000064 | 0 | 32 | RO
egress_stp_filter_high | 0x00000068 | 0 | 32 | RO
egress_stp_filter_low | 0x0000006c | 0 | 32 | RO
egress_hoq_stall_high | 0x00000070 | 0 | 32 | RO
egress_hoq_stall_low | 0x00000074 | 0 | 32 | RO
egress_sll_high | 0x00000078 | 0 | 32 | RO
egress_sll_low | 0x0000007c | 0 | 32 | RO
ingress_discard_all_high | 0x00000080 | 0 | 32 | RO
ingress_discard_all_low | 0x00000084 | 0 | 32 | RO
llr_rx_cells_high | 0x00000008 | 0 | 32 | RO
llr_rx_cells_low | 0x0000000c | 0 | 32 | RO
llr_rx_error_high | 0x00000010 | 0 | 32 | RO
llr_rx_error_low | 0x00000014 | 0 | 32 | RO
llr_rx_crc_error_high | 0x00000018 | 0 | 32 | RO
llr_rx_crc_error_low | 0x0000001c | 0 | 32 | RO
llr_tx_cells_high | 0x00000020 | 0 | 32 | RO
llr_tx_cells_low | 0x00000024 | 0 | 32 | RO
llr_tx_ret_cells_high | 0x00000028 | 0 | 32 | RO
llr_tx_ret_cells_low | 0x0000002c | 0 | 32 | RO
llr_tx_ret_events_high | 0x00000030 | 0 | 32 | RO
llr_tx_ret_events_low | 0x00000034 | 0 | 32 | RO
rx_octets_high | 0x00000008 | 0 | 32 | RO
rx_octets_low | 0x0000000c | 0 | 32 | RO
rx_frames_high | 0x00000028 | 0 | 32 | RO
rx_frames_low | 0x0000002c | 0 | 32 | RO
tx_octets_high | 0x00000030 | 0 | 32 | RO
tx_octets_low | 0x00000034 | 0 | 32 | RO
tx_frames_high | 0x00000050 | 0 | 32 | RO
tx_frames_low | 0x00000054 | 0 | 32 | RO
rx_pause_high | 0x00000058 | 0 | 32 | RO
rx_pause_low | 0x0000005c | 0 | 32 | RO
rx_pause_duration_high | 0x00000060 | 0 | 32 | RO
rx_pause_duration_low | 0x00000064 | 0 | 32 | RO
tx_pause_high | 0x00000068 | 0 | 32 | RO
tx_pause_low | 0x0000006c | 0 | 32 | RO
tx_pause_duration_high | 0x00000070 | 0 | 32 | RO
tx_pause_duration_low | 0x00000074 | 0 | 32 | RO
rx_pause_transition_high | 0x00000078 | 0 | 32 | RO
rx_pause_transition_low | 0x0000007c | 0 | 32 | RO
rx_discards_high | 0x00000080 | 0 | 32 | RO
rx_discards_low | 0x00000084 | 0 | 32 | RO
device_stall_minor_watermark_cnt_high | 0x00000088 | 0 | 32 | RO
device_stall_minor_watermark_cnt_low | 0x0000008c | 0 | 32 | RO
device_stall_critical_watermark_cnt_high | 0x00000090 | 0 | 32 | RO
device_stall_critical_watermark_cnt_low | 0x00000094 | 0 | 32 | RO
transmit_queue_high | 0x00000008 | 0 | 32 | RO
transmit_queue_low | 0x0000000c | 0 | 32 | RO
no_buffer_discard_uc_high | 0x00000010 | 0 | 32 | RO
no_buffer_discard_uc_low | 0x00000014 | 0 | 32 | RO
time_since_last_clear_high | 0x00000008 | 0 | 32 | RO
time_since_last_clear_low | 0x0000000c | 0 | 32 | RO
symbol_errors_high | 0x00000010 | 0 | 32 | RO
symbol_errors_low | 0x00000014 | 0 | 32 | RO
sync_headers_errors_high | 0x00000018 | 0 | 32 | RO
sync_headers_errors_low | 0x0000001c | 0 | 32 | RO
edpl_bip_errors_lane0_high | 0x00000020 | 0 | 32 | RO
edpl_bip_errors_lane0_low | 0x00000024 | 0 | 32 | RO
edpl_bip_errors_lane1_high | 0x00000028 | 0 | 32 | RO
edpl_bip_errors_lane1_low | 0x0000002c | 0 | 32 | RO
edpl_bip_errors_lane2_high | 0x00000030 | 0 | 32 | RO
edpl_bip_errors_lane2_low | 0x00000034 | 0 | 32 | RO
edpl_bip_errors_lane3_high | 0x00000038 | 0 | 32 | RO
edpl_bip_errors_lane3_low | 0x0000003c | 0 | 32 | RO
fc_fec_corrected_blocks_lane0_high | 0x00000040 | 0 | 32 | RO
fc_fec_corrected_blocks_lane0_low | 0x00000044 | 0 | 32 | RO
fc_fec_corrected_blocks_lane1_high | 0x00000048 | 0 | 32 | RO
fc_fec_corrected_blocks_lane1_low | 0x0000004c | 0 | 32 | RO
fc_fec_corrected_blocks_lane2_high | 0x00000050 | 0 | 32 | RO
fc_fec_corrected_blocks_lane2_low | 0x00000054 | 0 | 32 | RO
fc_fec_corrected_blocks_lane3_high | 0x00000058 | 0 | 32 | RO
fc_fec_corrected_blocks_lane3_low | 0x0000005c | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane0_high | 0x00000060 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane0_low | 0x00000064 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane1_high | 0x00000068 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane1_low | 0x0000006c | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane2_high | 0x00000070 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane2_low | 0x00000074 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane3_high | 0x00000078 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane3_low | 0x0000007c | 0 | 32 | RO
rs_fec_corrected_blocks_high | 0x00000080 | 0 | 32 | RO
rs_fec_corrected_blocks_low | 0x00000084 | 0 | 32 | RO
rs_fec_uncorrectable_blocks_high | 0x00000088 | 0 | 32 | RO
rs_fec_uncorrectable_blocks_low | 0x0000008c | 0 | 32 | RO
rs_fec_no_errors_blocks_high | 0x00000090 | 0 | 32 | RO
rs_fec_no_errors_blocks_low | 0x00000094 | 0 | 32 | RO
rs_fec_corrected_symbols_total_high | 0x000000a0 | 0 | 32 | RO
rs_fec_corrected_symbols_total_low | 0x000000a4 | 0 | 32 | RO
rs_fec_corrected_symbols_lane0_high | 0x000000a8 | 0 | 32 | RO
rs_fec_corrected_symbols_lane0_low | 0x000000ac | 0 | 32 | RO
rs_fec_corrected_symbols_lane1_high | 0x000000b0 | 0 | 32 | RO
rs_fec_corrected_symbols_lane1_low | 0x000000b4 | 0 | 32 | RO
rs_fec_corrected_symbols_lane2_high | 0x000000b8 | 0 | 32 | RO
rs_fec_corrected_symbols_lane2_low | 0x000000bc | 0 | 32 | RO
rs_fec_corrected_symbols_lane3_high | 0x000000c0 | 0 | 32 | RO
rs_fec_corrected_symbols_lane3_low | 0x000000c4 | 0 | 32 | RO
link_down_events | 0x000000c8 | 0 | 32 | RO
successful_recovery_events | 0x000000cc | 0 | 32 | RO
wred_discard_high | 0x00000008 | 0 | 32 | RO
wred_discard_low | 0x0000000c | 0 | 32 | RO
ecn_marked_tc_high | 0x00000010 | 0 | 32 | RO
ecn_marked_tc_low | 0x00000014 | 0 | 32 | RO
rx_no_buffer_discard_uc_high | 0x00000008 | 0 | 32 | RO
rx_no_buffer_discard_uc_low | 0x0000000c | 0 | 32 | RO
time_since_last_clear_high | 0x00000008 | 0 | 32 | RO
time_since_last_clear_low | 0x0000000c | 0 | 32 | RO
phy_received_bits_high | 0x00000010 | 0 | 32 | RO
phy_received_bits_low | 0x00000014 | 0 | 32 | RO
phy_symbol_errors_high | 0x00000018 | 0 | 32 | RO
phy_symbol_errors_low | 0x0000001c | 0 | 32 | RO
phy_corrected_bits_high | 0x00000020 | 0 | 32 | RO
phy_corrected_bits_low | 0x00000024 | 0 | 32 | RO
phy_raw_errors_lane0_high | 0x00000028 | 0 | 32 | RO
phy_raw_errors_lane0_low | 0x0000002c | 0 | 32 | RO
phy_raw_errors_lane1_high | 0x00000030 | 0 | 32 | RO
phy_raw_errors_lane1_low | 0x00000034 | 0 | 32 | RO
phy_raw_errors_lane2_high | 0x00000038 | 0 | 32 | RO
phy_raw_errors_lane2_low | 0x0000003c | 0 | 32 | RO
phy_raw_errors_lane3_high | 0x00000040 | 0 | 32 | RO
phy_raw_errors_lane3_low | 0x00000044 | 0 | 32 | RO
phy_raw_errors_lane4_high | 0x00000048 | 0 | 32 | RO
phy_raw_errors_lane4_low | 0x0000004c | 0 | 32 | RO
phy_raw_errors_lane5_high | 0x00000050 | 0 | 32 | RO
phy_raw_errors_lane5_low | 0x00000054 | 0 | 32 | RO
phy_raw_errors_lane6_high | 0x00000058 | 0 | 32 | RO
phy_raw_errors_lane6_low | 0x0000005c | 0 | 32 | RO
phy_raw_errors_lane7_high | 0x00000060 | 0 | 32 | RO
phy_raw_errors_lane7_low | 0x00000064 | 0 | 32 | RO
raw_ber_coef | 0x00000068 | 0 | 4 | RO
raw_ber_magnitude | 0x00000068 | 8 | 8 | RO
effective_ber_coef | 0x0000006c | 0 | 4 | RO
effective_ber_magnitude | 0x0000006c | 8 | 8 | RO
symbol_fec_ber_coef | 0x00000070 | 0 | 4 | RO
symbol_ber_magnitude | 0x00000070 | 8 | 8 | RO
phy_effective_errors_high | 0x00000084 | 0 | 32 | RO
phy_effective_errors_low | 0x00000088 | 0 | 32 | RO
if_in_ucast_pkts_high | 0x00000008 | 0 | 32 | RO
if_in_ucast_pkts_low | 0x0000000c | 0 | 32 | RO
if_in_octets_high | 0x00000010 | 0 | 32 | RO
if_in_octets_low | 0x00000014 | 0 | 32 | RO
if_in_discards_high | 0x00000018 | 0 | 32 | RO
if_in_discards_low | 0x0000001c | 0 | 32 | RO
if_in_errors_high | 0x00000020 | 0 | 32 | RO
if_in_errors_low | 0x00000024 | 0 | 32 | RO
ether_stats_crc_align_errors_high | 0x00000028 | 0 | 32 | RO
ether_stats_crc_align_errors_low | 0x0000002c | 0 | 32 | RO
ether_stats_undersize_pkts_high | 0x00000030 | 0 | 32 | RO
ether_stats_undersize_pkts_low | 0x00000034 | 0 | 32 | RO
ether_stats_oversize_pkts_high | 0x00000038 | 0 | 32 | RO
ether_stats_oversize_pkts_low | 0x0000003c | 0 | 32 | RO
dot3stats_symbol_errors_high | 0x00000040 | 0 | 32 | RO
dot3stats_symbol_errors_low | 0x00000044 | 0 | 32 | RO
dot3in_pause_frames_high | 0x00000048 | 0 | 32 | RO
dot3in_pause_frames_low | 0x0000004c | 0 | 32 | RO
dot3control_in_unknown_opcodes_high | 0x00000050 | 0 | 32 | RO
dot3control_in_unknown_opcodes_low | 0x00000054 | 0 | 32 | RO
if_out_ucast_pkts_high | 0x00000058 | 0 | 32 | RO
if_out_ucast_pkts_low | 0x0000005c | 0 | 32 | RO
if_out_octets_high | 0x00000060 | 0 | 32 | RO
if_out_octets_low | 0x00000064 | 0 | 32 | RO
dot3out_pause_frames_high | 0x00000068 | 0 | 32 | RO
dot3out_pause_frames_low | 0x0000006c | 0 | 32 | RO
if_out_errors_high | 0x00000070 | 0 | 32 | RO
if_out_errors_low | 0x00000074 | 0 | 32 | RO
phy_time_since_last_clear_high | 0x00000078 | 0 | 32 | RO
phy_time_since_last_clear_low | 0x0000007c | 0 | 32 | RO
phy_received_bits_high | 0x00000080 | 0 | 32 | RO
phy_received_bits_low | 0x00000084 | 0 | 32 | RO
phy_symbol_errors_high | 0x00000088 | 0 | 32 | RO
phy_symbol_errors_low | 0x0000008c | 0 | 32 | RO
link_downed_counter | 0x00000008 | 0 | 8 | RO
link_error_recovery_counter | 0x00000008 | 8 | 8 | RO
symbol_error_counter | 0x00000008 | 16 | 16 | RO
port_rcv_remote_physical_errors | 0x0000000c | 0 | 16 | RO
port_rcv_errors | 0x0000000c | 16 | 16 | RO
port_xmit_discards | 0x00000010 | 0 | 16 | RO
port_rcv_switch_relay_errors | 0x00000010 | 16 | 16 | RO
excessive_buffer_overrun_errors | 0x00000014 | 0 | 4 | RO
local_link_integrity_errors | 0x00000014 | 4 | 4 | RO
port_rcv_constraint_errors | 0x00000014 | 16 | 8 | RO
port_xmit_constraint_errors | 0x00000014 | 24 | 8 | RO
vl_15_dropped | 0x00000018 | 0 | 16 | RO
port_xmit_data | 0x0000001c | 0 | 32 | RO
port_rcv_data | 0x00000020 | 0 | 32 | RO
port_xmit_pkts | 0x00000024 | 0 | 32 | RO
port_rcv_pkts | 0x00000028 | 0 | 32 | RO
port_xmit_wait | 0x0000002c | 0 | 32 | RO
symbol_error_counter_high | 0x00000008 | 0 | 32 | RO
symbol_error_counter_low | 0x0000000c | 0 | 32 | RO
link_error_recovery_counter_high | 0x00000010 | 0 | 32 | RO
link_error_recovery_counter_low | 0x00000014 | 0 | 32 | RO
link_downed_counter_high | 0x00000018 | 0 | 32 | RO
link_downed_counter_low | 0x0000001c | 0 | 32 | RO
port_rcv_errors_high | 0x00000020 | 0 | 32 | RO
port_rcv_errors_low | 0x00000024 | 0 | 32 | RO
port_rcv_remote_physical_errors_high | 0x00000028 | 0 | 32 | RO
port_rcv_remote_physical_errors_low | 0x0000002c | 0 | 32 | RO
port_rcv_switch_relay_errors_high | 0x00000030 | 0 | 32 | RO
port_rcv_switch_relay_errors_low | 0x00000034 | 0 | 32 | RO
port_xmit_discards_high | 0x00000038 | 0 | 32 | RO
port_xmit_discards_low | 0x0000003c | 0 | 32 | RO
port_xmit_constraint_errors_high | 0x00000040 | 0 | 32 | RO
port_xmit_constraint_errors_low | 0x00000044 | 0 | 32 | RO
port_rcv_constraint_errors_high | 0x00000048 | 0 | 32 | RO
port_rcv_constraint_errors_low | 0x0000004c | 0 | 32 | RO
local_link_integrity_errors_high | 0x00000050 | 0 | 32 | RO
local_link_integrity_errors_low | 0x00000054 | 0 | 32 | RO
excessive_buffer_overrun_errors_high | 0x00000058 | 0 | 32 | RO
excessive_buffer_overrun_errors_low | 0x0000005c | 0 | 32 | RO
vl_15_dropped_high | 0x00000060 | 0 | 32 | RO
vl_15_dropped_low | 0x00000064 | 0 | 32 | RO
port_xmit_data_high | 0x00000068 | 0 | 32 | RO
port_xmit_data_low | 0x0000006c | 0 | 32 | RO
port_rcv_data_high | 0x00000070 | 0 | 32 | RO
port_rcv_data_low | 0x00000074 | 0 | 32 | RO
port_xmit_pkts_high | 0x00000078 | 0 | 32 | RO
port_xmit_pkts_low | 0x0000007c | 0 | 32 | RO
port_rcv_pkts_high | 0x00000080 | 0 | 32 | RO
port_rcv_pkts_low | 0x00000084 | 0 | 32 | RO
port_xmit_wait_high | 0x00000088 | 0 | 32 | RO
port_xmit_wait_low | 0x0000008c | 0 | 32 | RO
plr_rcv_codes_high | 0x00000008 | 0 | 32 | RO
plr_rcv_codes_low | 0x0000000c | 0 | 32 | RO
plr_rcv_code_err_high | 0x00000010 | 0 | 32 | RO
plr_rcv_code_err_low | 0x00000014 | 0 | 32 | RO
plr_rcv_uncorrectable_code_high | 0x00000018 | 0 | 32 | RO
plr_rcv_uncorrectable_code_low | 0x0000001c | 0 | 32 | RO
plr_xmit_codes_high | 0x00000020 | 0 | 32 | RO
plr_xmit_codes_low | 0x00000024 | 0 | 32 | RO
plr_xmit_retry_codes_high | 0x00000028 | 0 | 32 | RO
plr_xmit_retry_codes_low | 0x0000002c | 0 | 32 | RO
plr_xmit_retry_events_high | 0x00000030 | 0 | 32 | RO
plr_xmit_retry_events_low | 0x00000034 | 0 | 32 | RO
plr_sync_events_high | 0x00000038 | 0 | 32 | RO
plr_sync_events_low | 0x0000003c | 0 | 32 | RO
hi_retransmission_rate_high | 0x00000040 | 0 | 32 | RO
hi_retransmission_rate_low | 0x00000044 | 0 | 32 | RO
plr_xmit_retry_codes_within_t_sec_max_high | 0x00000048 | 0 | 32 | RO
plr_xmit_retry_codes_within_t_sec_max_low | 0x0000004c | 0 | 32 | RO
hi | 0x00000008 | 0 | 32 | RO
lo | 0x0000000c | 0 | 32 | RO
hi | 0x00000010 | 0 | 32 | RO
lo | 0x00000014 | 0 | 32 | RO
hi | 0x00000018 | 0 | 32 | RO
lo | 0x0000001c | 0 | 32 | RO
hi | 0x00000020 | 0 | 32 | RO
lo | 0x00000024 | 0 | 32 | RO
hi | 0x00000028 | 0 | 32 | RO
lo | 0x0000002c | 0 | 32 | RO
hi | 0x00000030 | 0 | 32 | RO
lo | 0x00000034 | 0 | 32 | RO
hi | 0x00000038 | 0 | 32 | RO
lo | 0x0000003c | 0 | 32 | RO
hi | 0x00000040 | 0 | 32 | RO
lo | 0x00000044 | 0 | 32 | RO
hi | 0x00000048 | 0 | 32 | RO
lo | 0x0000004c | 0 | 32 | RO
hi | 0x00000050 | 0 | 32 | RO
lo | 0x00000054 | 0 | 32 | RO
hi | 0x00000058 | 0 | 32 | RO
lo | 0x0000005c | 0 | 32 | RO
hi | 0x00000060 | 0 | 32 | RO
lo | 0x00000064 | 0 | 32 | RO
hi | 0x00000068 | 0 | 32 | RO
lo | 0x0000006c | 0 | 32 | RO
hi | 0x00000070 | 0 | 32 | RO
lo | 0x00000074 | 0 | 32 | RO
hi | 0x00000078 | 0 | 32 | RO
lo | 0x0000007c | 0 | 32 | RO
hi | 0x00000080 | 0 | 32 | RO
lo | 0x00000084 | 0 | 32 | RO
time_since_last_clear_high | 0x00000008 | 0 | 32 | RO
time_since_last_clear_low | 0x0000000c | 0 | 32 | RO
fc_fec_corrected_blocks_lane0_high | 0x00000010 | 0 | 32 | RO
fc_fec_corrected_blocks_lane0_low | 0x00000014 | 0 | 32 | RO
fc_fec_corrected_blocks_lane1_high | 0x00000018 | 0 | 32 | RO
fc_fec_corrected_blocks_lane1_low | 0x0000001c | 0 | 32 | RO
fc_fec_corrected_blocks_lane2_high | 0x00000020 | 0 | 32 | RO
fc_fec_corrected_blocks_lane2_low | 0x00000024 | 0 | 32 | RO
fc_fec_corrected_blocks_lane3_high | 0x00000028 | 0 | 32 | RO
fc_fec_corrected_blocks_lane3_low | 0x0000002c | 0 | 32 | RO
fc_fec_corrected_blocks_lane4_high | 0x00000030 | 0 | 32 | RO
fc_fec_corrected_blocks_lane4_low | 0x00000034 | 0 | 32 | RO
fc_fec_corrected_blocks_lane5_high | 0x00000038 | 0 | 32 | RO
fc_fec_corrected_blocks_lane5_low | 0x0000003c | 0 | 32 | RO
fc_fec_corrected_blocks_lane6_high | 0x00000040 | 0 | 32 | RO
fc_fec_corrected_blocks_lane6_low | 0x00000044 | 0 | 32 | RO
fc_fec_corrected_blocks_lane7_high | 0x00000048 | 0 | 32 | RO
fc_fec_corrected_blocks_lane7_low | 0x0000004c | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane0_high | 0x00000050 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane0_low | 0x00000054 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane1_high | 0x00000058 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane1_low | 0x0000005c | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane2_high | 0x00000060 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane2_low | 0x00000064 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane3_high | 0x00000068 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane3_low | 0x0000006c | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane4_high | 0x00000070 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane4_low | 0x00000074 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane5_high | 0x00000078 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane5_low | 0x0000007c | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane6_high | 0x00000080 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane6_low | 0x00000084 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane7_high | 0x00000088 | 0 | 32 | RO
fc_fec_uncorrectable_blocks_lane7_low | 0x0000008c | 0 | 32 | RO
link_down_events | 0x00000090 | 0 | 32 | RO
========================================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PPLM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
fec_mode_active | 0x0000000c | 0 | 24 | RO
fec_override_cap_10g_40g | 0x00000010 | 0 | 4 | RO
fec_override_cap_25g | 0x00000010 | 4 | 4 | RO
fec_override_cap_50g | 0x00000010 | 8 | 4 | RO
fec_override_cap_100g | 0x00000010 | 12 | 4 | RO
fec_override_cap_56g | 0x00000010 | 16 | 4 | RO
rs_fec_correction_bypass_cap | 0x00000010 | 28 | 4 | RO
fec_override_admin_10g_40g | 0x00000014 | 0 | 4 | RW
fec_override_admin_25g | 0x00000014 | 4 | 4 | RW
fec_override_admin_50g | 0x00000014 | 8 | 4 | RW
fec_override_admin_100g | 0x00000014 | 12 | 4 | RW
fec_override_admin_56g | 0x00000014 | 16 | 4 | RW
rs_fec_correction_bypass_admin | 0x00000014 | 28 | 4 | RW
fec_override_cap_200g_4x | 0x00000018 | 0 | 16 | RO
fec_override_cap_400g_8x | 0x00000018 | 16 | 16 | RO
fec_override_cap_50g_1x | 0x0000001c | 0 | 16 | RO
fec_override_cap_100g_2x | 0x0000001c | 16 | 16 | RO
fec_override_admin_200g_4x | 0x00000020 | 0 | 16 | RW
fec_override_admin_400g_8x | 0x00000020 | 16 | 16 | RW
fec_override_admin_50g_1x | 0x00000024 | 0 | 16 | RW
fec_override_admin_100g_2x | 0x00000024 | 16 | 16 | RW
===========================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PPLR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
lb_en | 0x00000004 | 0 | 8 | RW
lb_cap | 0x00000004 | 16 | 8 | RO
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PPRT
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==================================================================================
le | 0x00000000 | 0 | 1 | OP
ls | 0x00000000 | 1 | 1 | RO
lane | 0x00000000 | 8 | 4 | INDEX
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
p_c | 0x00000000 | 27 | 1 | RO
p | 0x00000000 | 28 | 1 | RW
tun_ovr | 0x00000000 | 29 | 1 | OP
s | 0x00000000 | 30 | 1 | OP
e | 0x00000000 | 31 | 1 | RW
prbs_modes_cap | 0x00000004 | 0 | 32 | RO
modulation | 0x00000008 | 0 | 4 | RW
prbs_mode_admin | 0x00000008 | 24 | 8 | RW
lane_rate_cap | 0x0000000c | 16 | 16 | RO
lane_rate_oper | 0x00000010 | 16 | 16 | RW
prbs_lock_status_ext | 0x00000014 | 20 | 4 | RO
prbs_lock_status | 0x00000014 | 24 | 4 | RO
prbs_rx_tuning_status | 0x00000014 | 28 | 4 | RO
==================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PPTB
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==========================================================================
pm | 0x00000000 | 0 | 8 | WO
um | 0x00000000 | 8 | 1 | WO
cm | 0x00000000 | 9 | 1 | WO
local_port | 0x00000000 | 16 | 8 | INDEX
mm | 0x00000000 | 28 | 2 | INDEX
prio0buff | 0x00000004 | 0 | 4 | RW
prio1buff | 0x00000004 | 4 | 4 | RW
prio2buff | 0x00000004 | 8 | 4 | RW
prio3buff | 0x00000004 | 12 | 4 | RW
prio4buff | 0x00000004 | 16 | 4 | RW
prio5buff | 0x00000004 | 20 | 4 | RW
prio6buff | 0x00000004 | 24 | 4 | RW
prio7buff | 0x00000004 | 28 | 4 | RW
untagged_buff | 0x00000008 | 0 | 4 | RW
ctrl_buff | 0x00000008 | 4 | 4 | RW
pm_msb | 0x00000008 | 24 | 8 | WO
==========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PPTT
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
============================================================================
le | 0x00000000 | 0 | 1 | OP
ls | 0x00000000 | 1 | 1 | RO
lane | 0x00000000 | 8 | 4 | INDEX
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
p_c | 0x00000000 | 27 | 1 | RO
p | 0x00000000 | 28 | 1 | RW
e | 0x00000000 | 31 | 1 | RW
prbs_modes_cap | 0x00000004 | 0 | 32 | RO
modulation | 0x00000008 | 0 | 4 | RW
prbs_mode_admin | 0x00000008 | 24 | 8 | RW
lane_rate_cap | 0x0000000c | 16 | 16 | RO
lane_rate_admin | 0x00000010 | 16 | 16 | RW
============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PREI
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==========================================================================
status | 0x00000000 | 0 | 2 | RO
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
version | 0x00000000 | 24 | 4 | RO
ber_exp | 0x00000004 | 0 | 8 | RW
ber_mantissa | 0x00000004 | 8 | 4 | RW
en | 0x00000004 | 31 | 1 | WO
lane_rate_cap | 0x00000008 | 16 | 16 | RO
mixer_offset1 | 0x00000010 | 0 | 16 | RW
mixer_offset0 | 0x00000010 | 16 | 16 | RW
==========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PTER
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================================
status | 0x00000000 | 0 | 4 | RO
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
error_page | 0x00000000 | 24 | 4 | INDEX
error_type_admin | 0x00000004 | 0 | 8 | RW
error_type_cap | 0x00000004 | 8 | 8 | RO
error_type_oper | 0x00000004 | 24 | 4 | RO
ber_exp | 0x00000008 | 0 | 8 | RW
ber_mantissa | 0x00000008 | 8 | 4 | RW
error_injection_time | 0x00000008 | 12 | 16 | RW
error_type_admin | 0x00000004 | 0 | 8 | RW
error_type_cap | 0x00000004 | 8 | 8 | RO
error_count | 0x00000008 | 12 | 5 | RW
=================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PTYS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=====================================================================================
proto_mask | 0x00000000 | 0 | 3 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
force_tx_aba_param | 0x00000000 | 24 | 1 | RW
an_disable_cap | 0x00000000 | 29 | 1 | RO
an_disable_admin | 0x00000000 | 30 | 1 | RW
reserved_high | 0x00000000 | 31 | 1 | RO
data_rate_oper | 0x00000004 | 0 | 16 | RO
max_port_rate | 0x00000004 | 16 | 12 | RO
an_status | 0x00000004 | 28 | 4 | RO
ext_eth_proto_capability | 0x00000008 | 0 | 32 | RO
eth_proto_capability | 0x0000000c | 0 | 32 | RO
ib_proto_capability | 0x00000010 | 0 | 16 | RO
ib_link_width_capability | 0x00000010 | 16 | 16 | RO
ext_eth_proto_admin | 0x00000014 | 0 | 32 | RW
eth_proto_admin | 0x00000018 | 0 | 32 | RW
ib_proto_admin | 0x0000001c | 0 | 16 | RW
ib_link_width_admin | 0x0000001c | 16 | 16 | RW
ext_eth_proto_oper | 0x00000020 | 0 | 32 | RO
eth_proto_oper | 0x00000024 | 0 | 32 | RO
ib_proto_oper | 0x00000028 | 0 | 16 | RO
ib_link_width_oper | 0x00000028 | 16 | 16 | RO
connector_type | 0x0000002c | 0 | 4 | RO
eth_proto_lp_advertise | 0x00000030 | 0 | 32 | RO
=====================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg PVLC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
vl_hw_cap | 0x00000004 | 0 | 4 | RO
vl_admin | 0x00000008 | 0 | 4 | RW
vl_operational | 0x0000000c | 0 | 4 | RO
===========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QCAM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================================
access_reg_group | 0x00000000 | 0 | 8 | INDEX
feature_group | 0x00000000 | 16 | 8 | INDEX
qos_access_reg_cap_mask[0] | 0x00000008 | 0 | 32 | RO
qos_access_reg_cap_mask[1] | 0x0000000c | 0 | 32 | RO
qos_access_reg_cap_mask[2] | 0x00000010 | 0 | 32 | RO
qos_access_reg_cap_mask[3] | 0x00000014 | 0 | 32 | RO
qos_feature_cap_mask[0] | 0x00000028 | 0 | 32 | RO
qos_feature_cap_mask[1] | 0x0000002c | 0 | 32 | RO
qos_feature_cap_mask[2] | 0x00000030 | 0 | 32 | RO
qos_feature_cap_mask[3] | 0x00000034 | 0 | 32 | RO
=======================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QCAP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==================================================================================
max_policers_per_port | 0x00000008 | 0 | 8 | RO
max_policers_global | 0x0000000c | 0 | 8 | RO
max_policers_cpu | 0x00000010 | 0 | 8 | RO
==================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QDPM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=====================================================================
dscp[3] | 0x00000000 | 0 | 8 | RW
dscp[2] | 0x00000000 | 8 | 8 | RW
dscp[1] | 0x00000000 | 16 | 8 | RW
dscp[0] | 0x00000000 | 24 | 8 | RW
dscp[7] | 0x00000004 | 0 | 8 | RW
dscp[6] | 0x00000004 | 8 | 8 | RW
dscp[5] | 0x00000004 | 16 | 8 | RW
dscp[4] | 0x00000004 | 24 | 8 | RW
dscp[11] | 0x00000008 | 0 | 8 | RW
dscp[10] | 0x00000008 | 8 | 8 | RW
dscp[9] | 0x00000008 | 16 | 8 | RW
dscp[8] | 0x00000008 | 24 | 8 | RW
dscp[15] | 0x0000000c | 0 | 8 | RW
dscp[14] | 0x0000000c | 8 | 8 | RW
dscp[13] | 0x0000000c | 16 | 8 | RW
dscp[12] | 0x0000000c | 24 | 8 | RW
dscp[19] | 0x00000010 | 0 | 8 | RW
dscp[18] | 0x00000010 | 8 | 8 | RW
dscp[17] | 0x00000010 | 16 | 8 | RW
dscp[16] | 0x00000010 | 24 | 8 | RW
dscp[23] | 0x00000014 | 0 | 8 | RW
dscp[22] | 0x00000014 | 8 | 8 | RW
dscp[21] | 0x00000014 | 16 | 8 | RW
dscp[20] | 0x00000014 | 24 | 8 | RW
dscp[27] | 0x00000018 | 0 | 8 | RW
dscp[26] | 0x00000018 | 8 | 8 | RW
dscp[25] | 0x00000018 | 16 | 8 | RW
dscp[24] | 0x00000018 | 24 | 8 | RW
dscp[31] | 0x0000001c | 0 | 8 | RW
dscp[30] | 0x0000001c | 8 | 8 | RW
dscp[29] | 0x0000001c | 16 | 8 | RW
dscp[28] | 0x0000001c | 24 | 8 | RW
dscp[35] | 0x00000020 | 0 | 8 | RW
dscp[34] | 0x00000020 | 8 | 8 | RW
dscp[33] | 0x00000020 | 16 | 8 | RW
dscp[32] | 0x00000020 | 24 | 8 | RW
dscp[39] | 0x00000024 | 0 | 8 | RW
dscp[38] | 0x00000024 | 8 | 8 | RW
dscp[37] | 0x00000024 | 16 | 8 | RW
dscp[36] | 0x00000024 | 24 | 8 | RW
dscp[43] | 0x00000028 | 0 | 8 | RW
dscp[42] | 0x00000028 | 8 | 8 | RW
dscp[41] | 0x00000028 | 16 | 8 | RW
dscp[40] | 0x00000028 | 24 | 8 | RW
dscp[47] | 0x0000002c | 0 | 8 | RW
dscp[46] | 0x0000002c | 8 | 8 | RW
dscp[45] | 0x0000002c | 16 | 8 | RW
dscp[44] | 0x0000002c | 24 | 8 | RW
dscp[51] | 0x00000030 | 0 | 8 | RW
dscp[50] | 0x00000030 | 8 | 8 | RW
dscp[49] | 0x00000030 | 16 | 8 | RW
dscp[48] | 0x00000030 | 24 | 8 | RW
dscp[55] | 0x00000034 | 0 | 8 | RW
dscp[54] | 0x00000034 | 8 | 8 | RW
dscp[53] | 0x00000034 | 16 | 8 | RW
dscp[52] | 0x00000034 | 24 | 8 | RW
dscp[59] | 0x00000038 | 0 | 8 | RW
dscp[58] | 0x00000038 | 8 | 8 | RW
dscp[57] | 0x00000038 | 16 | 8 | RW
dscp[56] | 0x00000038 | 24 | 8 | RW
dscp[63] | 0x0000003c | 0 | 8 | RW
dscp[62] | 0x0000003c | 8 | 8 | RW
dscp[61] | 0x0000003c | 16 | 8 | RW
dscp[60] | 0x0000003c | 24 | 8 | RW
=====================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QEEC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
element_index | 0x00000004 | 0 | 8 | INDEX
element_hierarchy | 0x00000004 | 16 | 4 | INDEX
next_element_index | 0x00000008 | 0 | 8 | RW
min_shaper_rate | 0x0000000c | 0 | 28 | RW
pb | 0x0000000c | 28 | 1 | RW
ptps | 0x0000000c | 29 | 1 | RW
mise | 0x0000000c | 31 | 1 | RW
max_shaper_rate | 0x00000010 | 0 | 28 | RW
mase | 0x00000010 | 31 | 1 | RW
phantom_queue_rate | 0x00000014 | 0 | 28 | RW
pqe | 0x00000014 | 31 | 1 | RW
dwrr_weight | 0x00000018 | 0 | 8 | RW
dwrr | 0x00000018 | 15 | 1 | RW
de | 0x00000018 | 31 | 1 | RW
max_shaper_bs | 0x0000001c | 0 | 6 | RW
min_shaper_bs | 0x0000001c | 16 | 6 | RW
===============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QEGCS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=========================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
abr_glob_sp | 0x00000004 | 0 | 1 | RW
grp15_arb_sp | 0x00000004 | 1 | 1 | RW
grp07_arb_sp | 0x00000004 | 2 | 1 | RW
=========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QEPM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
exp[1] | 0x00000004 | 0 | 16 | RW
exp[0] | 0x00000004 | 16 | 16 | RW
exp[3] | 0x00000008 | 0 | 16 | RW
exp[2] | 0x00000008 | 16 | 16 | RW
exp[5] | 0x0000000c | 0 | 16 | RW
exp[4] | 0x0000000c | 16 | 16 | RW
exp[7] | 0x00000010 | 0 | 16 | RW
exp[6] | 0x00000010 | 16 | 16 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QETCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
cap_remote_admin | 0x00000000 | 28 | 1 | RO
cap_local_admin | 0x00000000 | 29 | 1 | RO
operation_type | 0x00000000 | 30 | 2 | INDEX
bw_allocation | 0x00000008 | 0 | 7 | RW
group | 0x00000008 | 16 | 4 | RW
r | 0x00000008 | 29 | 1 | WO
b | 0x00000008 | 30 | 1 | WO
g | 0x00000008 | 31 | 1 | WO
max_bw_value | 0x0000000c | 0 | 8 | RW
max_bw_units | 0x0000000c | 16 | 4 | RW
bw_allocation | 0x00000010 | 0 | 7 | RW
group | 0x00000010 | 16 | 4 | RW
r | 0x00000010 | 29 | 1 | WO
b | 0x00000010 | 30 | 1 | WO
g | 0x00000010 | 31 | 1 | WO
max_bw_value | 0x00000014 | 0 | 8 | RW
max_bw_units | 0x00000014 | 16 | 4 | RW
bw_allocation | 0x00000018 | 0 | 7 | RW
group | 0x00000018 | 16 | 4 | RW
r | 0x00000018 | 29 | 1 | WO
b | 0x00000018 | 30 | 1 | WO
g | 0x00000018 | 31 | 1 | WO
max_bw_value | 0x0000001c | 0 | 8 | RW
max_bw_units | 0x0000001c | 16 | 4 | RW
bw_allocation | 0x00000020 | 0 | 7 | RW
group | 0x00000020 | 16 | 4 | RW
r | 0x00000020 | 29 | 1 | WO
b | 0x00000020 | 30 | 1 | WO
g | 0x00000020 | 31 | 1 | WO
max_bw_value | 0x00000024 | 0 | 8 | RW
max_bw_units | 0x00000024 | 16 | 4 | RW
bw_allocation | 0x00000028 | 0 | 7 | RW
group | 0x00000028 | 16 | 4 | RW
r | 0x00000028 | 29 | 1 | WO
b | 0x00000028 | 30 | 1 | WO
g | 0x00000028 | 31 | 1 | WO
max_bw_value | 0x0000002c | 0 | 8 | RW
max_bw_units | 0x0000002c | 16 | 4 | RW
bw_allocation | 0x00000030 | 0 | 7 | RW
group | 0x00000030 | 16 | 4 | RW
r | 0x00000030 | 29 | 1 | WO
b | 0x00000030 | 30 | 1 | WO
g | 0x00000030 | 31 | 1 | WO
max_bw_value | 0x00000034 | 0 | 8 | RW
max_bw_units | 0x00000034 | 16 | 4 | RW
bw_allocation | 0x00000038 | 0 | 7 | RW
group | 0x00000038 | 16 | 4 | RW
r | 0x00000038 | 29 | 1 | WO
b | 0x00000038 | 30 | 1 | WO
g | 0x00000038 | 31 | 1 | WO
max_bw_value | 0x0000003c | 0 | 8 | RW
max_bw_units | 0x0000003c | 16 | 4 | RW
bw_allocation | 0x00000040 | 0 | 7 | RW
group | 0x00000040 | 16 | 4 | RW
r | 0x00000040 | 29 | 1 | WO
b | 0x00000040 | 30 | 1 | WO
g | 0x00000040 | 31 | 1 | WO
max_bw_value | 0x00000044 | 0 | 8 | RW
max_bw_units | 0x00000044 | 16 | 4 | RW
r | 0x00000048 | 29 | 1 | WO
max_bw_value | 0x0000004c | 0 | 8 | RW
max_bw_units | 0x0000004c | 16 | 4 | RW
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QHLL
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
hll_time | 0x00000004 | 0 | 5 | RW
stall_cnt | 0x00000008 | 0 | 3 | RW
stall_en | 0x00000008 | 31 | 1 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QPBR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
pid | 0x00000000 | 0 | 14 | RW
g | 0x00000000 | 15 | 1 | RW
local_port | 0x00000000 | 16 | 8 | INDEX
op | 0x00000000 | 30 | 2 | RW
uc | 0x00000004 | 0 | 1 | INDEX
mc | 0x00000004 | 1 | 1 | INDEX
bc | 0x00000004 | 2 | 1 | INDEX
uuc | 0x00000004 | 3 | 1 | INDEX
umc | 0x00000004 | 4 | 1 | INDEX
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QPCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================================
pid | 0x00000000 | 0 | 14 | INDEX
g | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
mode | 0x00000004 | 0 | 2 | RW
type | 0x00000004 | 8 | 2 | RW
ir_units | 0x00000004 | 12 | 1 | OP
bytes | 0x00000004 | 14 | 1 | RW
color_aware | 0x00000004 | 15 | 1 | RW
add_counter | 0x00000004 | 30 | 1 | OP
clear_counter | 0x00000004 | 31 | 1 | OP
ebs | 0x00000008 | 16 | 6 | RW
cbs | 0x00000008 | 24 | 6 | RW
cir | 0x0000000c | 0 | 32 | RW
eir | 0x00000010 | 0 | 32 | RW
exceed_action | 0x00000014 | 0 | 4 | RW
violate_action | 0x00000018 | 0 | 4 | RW
violate_count_high | 0x00000020 | 0 | 32 | RW
violate_count_low | 0x00000024 | 0 | 32 | RW
===============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QPDP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
switch_prio | 0x00000004 | 0 | 4 | RW
color | 0x00000004 | 8 | 2 | RW
========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QPDPC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
pcp | 0x00000004 | 0 | 3 | RW
dei | 0x00000004 | 8 | 1 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QPDPM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
dscp[1] | 0x00000004 | 0 | 16 | RW
dscp[0] | 0x00000004 | 16 | 16 | RW
dscp[3] | 0x00000008 | 0 | 16 | RW
dscp[2] | 0x00000008 | 16 | 16 | RW
dscp[5] | 0x0000000c | 0 | 16 | RW
dscp[4] | 0x0000000c | 16 | 16 | RW
dscp[7] | 0x00000010 | 0 | 16 | RW
dscp[6] | 0x00000010 | 16 | 16 | RW
dscp[9] | 0x00000014 | 0 | 16 | RW
dscp[8] | 0x00000014 | 16 | 16 | RW
dscp[11] | 0x00000018 | 0 | 16 | RW
dscp[10] | 0x00000018 | 16 | 16 | RW
dscp[13] | 0x0000001c | 0 | 16 | RW
dscp[12] | 0x0000001c | 16 | 16 | RW
dscp[15] | 0x00000020 | 0 | 16 | RW
dscp[14] | 0x00000020 | 16 | 16 | RW
dscp[17] | 0x00000024 | 0 | 16 | RW
dscp[16] | 0x00000024 | 16 | 16 | RW
dscp[19] | 0x00000028 | 0 | 16 | RW
dscp[18] | 0x00000028 | 16 | 16 | RW
dscp[21] | 0x0000002c | 0 | 16 | RW
dscp[20] | 0x0000002c | 16 | 16 | RW
dscp[23] | 0x00000030 | 0 | 16 | RW
dscp[22] | 0x00000030 | 16 | 16 | RW
dscp[25] | 0x00000034 | 0 | 16 | RW
dscp[24] | 0x00000034 | 16 | 16 | RW
dscp[27] | 0x00000038 | 0 | 16 | RW
dscp[26] | 0x00000038 | 16 | 16 | RW
dscp[29] | 0x0000003c | 0 | 16 | RW
dscp[28] | 0x0000003c | 16 | 16 | RW
dscp[31] | 0x00000040 | 0 | 16 | RW
dscp[30] | 0x00000040 | 16 | 16 | RW
dscp[33] | 0x00000044 | 0 | 16 | RW
dscp[32] | 0x00000044 | 16 | 16 | RW
dscp[35] | 0x00000048 | 0 | 16 | RW
dscp[34] | 0x00000048 | 16 | 16 | RW
dscp[37] | 0x0000004c | 0 | 16 | RW
dscp[36] | 0x0000004c | 16 | 16 | RW
dscp[39] | 0x00000050 | 0 | 16 | RW
dscp[38] | 0x00000050 | 16 | 16 | RW
dscp[41] | 0x00000054 | 0 | 16 | RW
dscp[40] | 0x00000054 | 16 | 16 | RW
dscp[43] | 0x00000058 | 0 | 16 | RW
dscp[42] | 0x00000058 | 16 | 16 | RW
dscp[45] | 0x0000005c | 0 | 16 | RW
dscp[44] | 0x0000005c | 16 | 16 | RW
dscp[47] | 0x00000060 | 0 | 16 | RW
dscp[46] | 0x00000060 | 16 | 16 | RW
dscp[49] | 0x00000064 | 0 | 16 | RW
dscp[48] | 0x00000064 | 16 | 16 | RW
dscp[51] | 0x00000068 | 0 | 16 | RW
dscp[50] | 0x00000068 | 16 | 16 | RW
dscp[53] | 0x0000006c | 0 | 16 | RW
dscp[52] | 0x0000006c | 16 | 16 | RW
dscp[55] | 0x00000070 | 0 | 16 | RW
dscp[54] | 0x00000070 | 16 | 16 | RW
dscp[57] | 0x00000074 | 0 | 16 | RW
dscp[56] | 0x00000074 | 16 | 16 | RW
dscp[59] | 0x00000078 | 0 | 16 | RW
dscp[58] | 0x00000078 | 16 | 16 | RW
dscp[61] | 0x0000007c | 0 | 16 | RW
dscp[60] | 0x0000007c | 16 | 16 | RW
dscp[63] | 0x00000080 | 0 | 16 | RW
dscp[62] | 0x00000080 | 16 | 16 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QPDSM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
color2 | 0x00000004 | 8 | 8 | RW
color1 | 0x00000004 | 16 | 8 | RW
color0 | 0x00000004 | 24 | 8 | RW
color2 | 0x00000008 | 8 | 8 | RW
color1 | 0x00000008 | 16 | 8 | RW
color0 | 0x00000008 | 24 | 8 | RW
color2 | 0x0000000c | 8 | 8 | RW
color1 | 0x0000000c | 16 | 8 | RW
color0 | 0x0000000c | 24 | 8 | RW
color2 | 0x00000010 | 8 | 8 | RW
color1 | 0x00000010 | 16 | 8 | RW
color0 | 0x00000010 | 24 | 8 | RW
color2 | 0x00000014 | 8 | 8 | RW
color1 | 0x00000014 | 16 | 8 | RW
color0 | 0x00000014 | 24 | 8 | RW
color2 | 0x00000018 | 8 | 8 | RW
color1 | 0x00000018 | 16 | 8 | RW
color0 | 0x00000018 | 24 | 8 | RW
color2 | 0x0000001c | 8 | 8 | RW
color1 | 0x0000001c | 16 | 8 | RW
color0 | 0x0000001c | 24 | 8 | RW
color2 | 0x00000020 | 8 | 8 | RW
color1 | 0x00000020 | 16 | 8 | RW
color0 | 0x00000020 | 24 | 8 | RW
color2 | 0x00000024 | 8 | 8 | RW
color1 | 0x00000024 | 16 | 8 | RW
color0 | 0x00000024 | 24 | 8 | RW
color2 | 0x00000028 | 8 | 8 | RW
color1 | 0x00000028 | 16 | 8 | RW
color0 | 0x00000028 | 24 | 8 | RW
color2 | 0x0000002c | 8 | 8 | RW
color1 | 0x0000002c | 16 | 8 | RW
color0 | 0x0000002c | 24 | 8 | RW
color2 | 0x00000030 | 8 | 8 | RW
color1 | 0x00000030 | 16 | 8 | RW
color0 | 0x00000030 | 24 | 8 | RW
color2 | 0x00000034 | 8 | 8 | RW
color1 | 0x00000034 | 16 | 8 | RW
color0 | 0x00000034 | 24 | 8 | RW
color2 | 0x00000038 | 8 | 8 | RW
color1 | 0x00000038 | 16 | 8 | RW
color0 | 0x00000038 | 24 | 8 | RW
color2 | 0x0000003c | 8 | 8 | RW
color1 | 0x0000003c | 16 | 8 | RW
color0 | 0x0000003c | 24 | 8 | RW
color2 | 0x00000040 | 8 | 8 | RW
color1 | 0x00000040 | 16 | 8 | RW
color0 | 0x00000040 | 24 | 8 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QPEM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
color2 | 0x00000004 | 8 | 8 | RW
color1 | 0x00000004 | 16 | 8 | RW
color0 | 0x00000004 | 24 | 8 | RW
color2 | 0x00000008 | 8 | 8 | RW
color1 | 0x00000008 | 16 | 8 | RW
color0 | 0x00000008 | 24 | 8 | RW
color2 | 0x0000000c | 8 | 8 | RW
color1 | 0x0000000c | 16 | 8 | RW
color0 | 0x0000000c | 24 | 8 | RW
color2 | 0x00000010 | 8 | 8 | RW
color1 | 0x00000010 | 16 | 8 | RW
color0 | 0x00000010 | 24 | 8 | RW
color2 | 0x00000014 | 8 | 8 | RW
color1 | 0x00000014 | 16 | 8 | RW
color0 | 0x00000014 | 24 | 8 | RW
color2 | 0x00000018 | 8 | 8 | RW
color1 | 0x00000018 | 16 | 8 | RW
color0 | 0x00000018 | 24 | 8 | RW
color2 | 0x0000001c | 8 | 8 | RW
color1 | 0x0000001c | 16 | 8 | RW
color0 | 0x0000001c | 24 | 8 | RW
color2 | 0x00000020 | 8 | 8 | RW
color1 | 0x00000020 | 16 | 8 | RW
color0 | 0x00000020 | 24 | 8 | RW
color2 | 0x00000024 | 8 | 8 | RW
color1 | 0x00000024 | 16 | 8 | RW
color0 | 0x00000024 | 24 | 8 | RW
color2 | 0x00000028 | 8 | 8 | RW
color1 | 0x00000028 | 16 | 8 | RW
color0 | 0x00000028 | 24 | 8 | RW
color2 | 0x0000002c | 8 | 8 | RW
color1 | 0x0000002c | 16 | 8 | RW
color0 | 0x0000002c | 24 | 8 | RW
color2 | 0x00000030 | 8 | 8 | RW
color1 | 0x00000030 | 16 | 8 | RW
color0 | 0x00000030 | 24 | 8 | RW
color2 | 0x00000034 | 8 | 8 | RW
color1 | 0x00000034 | 16 | 8 | RW
color0 | 0x00000034 | 24 | 8 | RW
color2 | 0x00000038 | 8 | 8 | RW
color1 | 0x00000038 | 16 | 8 | RW
color0 | 0x00000038 | 24 | 8 | RW
color2 | 0x0000003c | 8 | 8 | RW
color1 | 0x0000003c | 16 | 8 | RW
color0 | 0x0000003c | 24 | 8 | RW
color2 | 0x00000040 | 8 | 8 | RW
color1 | 0x00000040 | 16 | 8 | RW
color0 | 0x00000040 | 24 | 8 | RW
color2 | 0x00000044 | 8 | 8 | RW
color1 | 0x00000044 | 16 | 8 | RW
color0 | 0x00000044 | 24 | 8 | RW
color2 | 0x00000048 | 8 | 8 | RW
color1 | 0x00000048 | 16 | 8 | RW
color0 | 0x00000048 | 24 | 8 | RW
color2 | 0x0000004c | 8 | 8 | RW
color1 | 0x0000004c | 16 | 8 | RW
color0 | 0x0000004c | 24 | 8 | RW
color2 | 0x00000050 | 8 | 8 | RW
color1 | 0x00000050 | 16 | 8 | RW
color0 | 0x00000050 | 24 | 8 | RW
color2 | 0x00000054 | 8 | 8 | RW
color1 | 0x00000054 | 16 | 8 | RW
color0 | 0x00000054 | 24 | 8 | RW
color2 | 0x00000058 | 8 | 8 | RW
color1 | 0x00000058 | 16 | 8 | RW
color0 | 0x00000058 | 24 | 8 | RW
color2 | 0x0000005c | 8 | 8 | RW
color1 | 0x0000005c | 16 | 8 | RW
color0 | 0x0000005c | 24 | 8 | RW
color2 | 0x00000060 | 8 | 8 | RW
color1 | 0x00000060 | 16 | 8 | RW
color0 | 0x00000060 | 24 | 8 | RW
color2 | 0x00000064 | 8 | 8 | RW
color1 | 0x00000064 | 16 | 8 | RW
color0 | 0x00000064 | 24 | 8 | RW
color2 | 0x00000068 | 8 | 8 | RW
color1 | 0x00000068 | 16 | 8 | RW
color0 | 0x00000068 | 24 | 8 | RW
color2 | 0x0000006c | 8 | 8 | RW
color1 | 0x0000006c | 16 | 8 | RW
color0 | 0x0000006c | 24 | 8 | RW
color2 | 0x00000070 | 8 | 8 | RW
color1 | 0x00000070 | 16 | 8 | RW
color0 | 0x00000070 | 24 | 8 | RW
color2 | 0x00000074 | 8 | 8 | RW
color1 | 0x00000074 | 16 | 8 | RW
color0 | 0x00000074 | 24 | 8 | RW
color2 | 0x00000078 | 8 | 8 | RW
color1 | 0x00000078 | 16 | 8 | RW
color0 | 0x00000078 | 24 | 8 | RW
color2 | 0x0000007c | 8 | 8 | RW
color1 | 0x0000007c | 16 | 8 | RW
color0 | 0x0000007c | 24 | 8 | RW
color2 | 0x00000080 | 8 | 8 | RW
color1 | 0x00000080 | 16 | 8 | RW
color0 | 0x00000080 | 24 | 8 | RW
color2 | 0x00000084 | 8 | 8 | RW
color1 | 0x00000084 | 16 | 8 | RW
color0 | 0x00000084 | 24 | 8 | RW
color2 | 0x00000088 | 8 | 8 | RW
color1 | 0x00000088 | 16 | 8 | RW
color0 | 0x00000088 | 24 | 8 | RW
color2 | 0x0000008c | 8 | 8 | RW
color1 | 0x0000008c | 16 | 8 | RW
color0 | 0x0000008c | 24 | 8 | RW
color2 | 0x00000090 | 8 | 8 | RW
color1 | 0x00000090 | 16 | 8 | RW
color0 | 0x00000090 | 24 | 8 | RW
color2 | 0x00000094 | 8 | 8 | RW
color1 | 0x00000094 | 16 | 8 | RW
color0 | 0x00000094 | 24 | 8 | RW
color2 | 0x00000098 | 8 | 8 | RW
color1 | 0x00000098 | 16 | 8 | RW
color0 | 0x00000098 | 24 | 8 | RW
color2 | 0x0000009c | 8 | 8 | RW
color1 | 0x0000009c | 16 | 8 | RW
color0 | 0x0000009c | 24 | 8 | RW
color2 | 0x000000a0 | 8 | 8 | RW
color1 | 0x000000a0 | 16 | 8 | RW
color0 | 0x000000a0 | 24 | 8 | RW
color2 | 0x000000a4 | 8 | 8 | RW
color1 | 0x000000a4 | 16 | 8 | RW
color0 | 0x000000a4 | 24 | 8 | RW
color2 | 0x000000a8 | 8 | 8 | RW
color1 | 0x000000a8 | 16 | 8 | RW
color0 | 0x000000a8 | 24 | 8 | RW
color2 | 0x000000ac | 8 | 8 | RW
color1 | 0x000000ac | 16 | 8 | RW
color0 | 0x000000ac | 24 | 8 | RW
color2 | 0x000000b0 | 8 | 8 | RW
color1 | 0x000000b0 | 16 | 8 | RW
color0 | 0x000000b0 | 24 | 8 | RW
color2 | 0x000000b4 | 8 | 8 | RW
color1 | 0x000000b4 | 16 | 8 | RW
color0 | 0x000000b4 | 24 | 8 | RW
color2 | 0x000000b8 | 8 | 8 | RW
color1 | 0x000000b8 | 16 | 8 | RW
color0 | 0x000000b8 | 24 | 8 | RW
color2 | 0x000000bc | 8 | 8 | RW
color1 | 0x000000bc | 16 | 8 | RW
color0 | 0x000000bc | 24 | 8 | RW
color2 | 0x000000c0 | 8 | 8 | RW
color1 | 0x000000c0 | 16 | 8 | RW
color0 | 0x000000c0 | 24 | 8 | RW
color2 | 0x000000c4 | 8 | 8 | RW
color1 | 0x000000c4 | 16 | 8 | RW
color0 | 0x000000c4 | 24 | 8 | RW
color2 | 0x000000c8 | 8 | 8 | RW
color1 | 0x000000c8 | 16 | 8 | RW
color0 | 0x000000c8 | 24 | 8 | RW
color2 | 0x000000cc | 8 | 8 | RW
color1 | 0x000000cc | 16 | 8 | RW
color0 | 0x000000cc | 24 | 8 | RW
color2 | 0x000000d0 | 8 | 8 | RW
color1 | 0x000000d0 | 16 | 8 | RW
color0 | 0x000000d0 | 24 | 8 | RW
color2 | 0x000000d4 | 8 | 8 | RW
color1 | 0x000000d4 | 16 | 8 | RW
color0 | 0x000000d4 | 24 | 8 | RW
color2 | 0x000000d8 | 8 | 8 | RW
color1 | 0x000000d8 | 16 | 8 | RW
color0 | 0x000000d8 | 24 | 8 | RW
color2 | 0x000000dc | 8 | 8 | RW
color1 | 0x000000dc | 16 | 8 | RW
color0 | 0x000000dc | 24 | 8 | RW
color2 | 0x000000e0 | 8 | 8 | RW
color1 | 0x000000e0 | 16 | 8 | RW
color0 | 0x000000e0 | 24 | 8 | RW
color2 | 0x000000e4 | 8 | 8 | RW
color1 | 0x000000e4 | 16 | 8 | RW
color0 | 0x000000e4 | 24 | 8 | RW
color2 | 0x000000e8 | 8 | 8 | RW
color1 | 0x000000e8 | 16 | 8 | RW
color0 | 0x000000e8 | 24 | 8 | RW
color2 | 0x000000ec | 8 | 8 | RW
color1 | 0x000000ec | 16 | 8 | RW
color0 | 0x000000ec | 24 | 8 | RW
color2 | 0x000000f0 | 8 | 8 | RW
color1 | 0x000000f0 | 16 | 8 | RW
color0 | 0x000000f0 | 24 | 8 | RW
color2 | 0x000000f4 | 8 | 8 | RW
color1 | 0x000000f4 | 16 | 8 | RW
color0 | 0x000000f4 | 24 | 8 | RW
color2 | 0x000000f8 | 8 | 8 | RW
color1 | 0x000000f8 | 16 | 8 | RW
color0 | 0x000000f8 | 24 | 8 | RW
color2 | 0x000000fc | 8 | 8 | RW
color1 | 0x000000fc | 16 | 8 | RW
color0 | 0x000000fc | 24 | 8 | RW
color2 | 0x00000100 | 8 | 8 | RW
color1 | 0x00000100 | 16 | 8 | RW
color0 | 0x00000100 | 24 | 8 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QPPM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
color2 | 0x00000004 | 8 | 8 | RW
color1 | 0x00000004 | 16 | 8 | RW
color0 | 0x00000004 | 24 | 8 | RW
color2 | 0x00000008 | 8 | 8 | RW
color1 | 0x00000008 | 16 | 8 | RW
color0 | 0x00000008 | 24 | 8 | RW
color2 | 0x0000000c | 8 | 8 | RW
color1 | 0x0000000c | 16 | 8 | RW
color0 | 0x0000000c | 24 | 8 | RW
color2 | 0x00000010 | 8 | 8 | RW
color1 | 0x00000010 | 16 | 8 | RW
color0 | 0x00000010 | 24 | 8 | RW
color2 | 0x00000014 | 8 | 8 | RW
color1 | 0x00000014 | 16 | 8 | RW
color0 | 0x00000014 | 24 | 8 | RW
color2 | 0x00000018 | 8 | 8 | RW
color1 | 0x00000018 | 16 | 8 | RW
color0 | 0x00000018 | 24 | 8 | RW
color2 | 0x0000001c | 8 | 8 | RW
color1 | 0x0000001c | 16 | 8 | RW
color0 | 0x0000001c | 24 | 8 | RW
color2 | 0x00000020 | 8 | 8 | RW
color1 | 0x00000020 | 16 | 8 | RW
color0 | 0x00000020 | 24 | 8 | RW
color2 | 0x00000024 | 8 | 8 | RW
color1 | 0x00000024 | 16 | 8 | RW
color0 | 0x00000024 | 24 | 8 | RW
color2 | 0x00000028 | 8 | 8 | RW
color1 | 0x00000028 | 16 | 8 | RW
color0 | 0x00000028 | 24 | 8 | RW
color2 | 0x0000002c | 8 | 8 | RW
color1 | 0x0000002c | 16 | 8 | RW
color0 | 0x0000002c | 24 | 8 | RW
color2 | 0x00000030 | 8 | 8 | RW
color1 | 0x00000030 | 16 | 8 | RW
color0 | 0x00000030 | 24 | 8 | RW
color2 | 0x00000034 | 8 | 8 | RW
color1 | 0x00000034 | 16 | 8 | RW
color0 | 0x00000034 | 24 | 8 | RW
color2 | 0x00000038 | 8 | 8 | RW
color1 | 0x00000038 | 16 | 8 | RW
color0 | 0x00000038 | 24 | 8 | RW
color2 | 0x0000003c | 8 | 8 | RW
color1 | 0x0000003c | 16 | 8 | RW
color0 | 0x0000003c | 24 | 8 | RW
color2 | 0x00000040 | 8 | 8 | RW
color1 | 0x00000040 | 16 | 8 | RW
color0 | 0x00000040 | 24 | 8 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QPRT
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
pcp | 0x00000000 | 8 | 3 | INDEX
dei | 0x00000000 | 11 | 1 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
rprio | 0x00000004 | 0 | 4 | RW
color | 0x00000004 | 8 | 2 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QPTS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
trust_state | 0x00000004 | 0 | 3 | RW
========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QRWE
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
pcp | 0x00000004 | 0 | 1 | RW
dscp | 0x00000004 | 1 | 1 | RW
exp | 0x00000004 | 2 | 1 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QSLL
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=====================================================================
sll_time | 0x00000004 | 0 | 5 | RW
=====================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QSPCP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
switch_prio | 0x00000000 | 0 | 4 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
rx_counting_prio | 0x00000004 | 0 | 3 | RW
tx_counting_prio | 0x00000008 | 0 | 3 | RW
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QSPIP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================
switch_prio | 0x00000000 | 0 | 4 | INDEX
ieee_prio | 0x00000004 | 0 | 3 | RW
========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QSPTC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================
itclass | 0x00000000 | 8 | 3 | INDEX
local_eport | 0x00000000 | 16 | 8 | INDEX
local_iport | 0x00000000 | 24 | 8 | INDEX
tclass | 0x00000004 | 0 | 3 | RW
========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QSTCT
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================
switch_prio | 0x00000000 | 8 | 4 | INDEX
swid | 0x00000000 | 24 | 8 | INDEX
utclass | 0x00000004 | 0 | 3 | RW
mtclass | 0x00000008 | 0 | 3 | RW
========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QTCT
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
switch_prio | 0x00000000 | 0 | 4 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
cap_remote_admin | 0x00000000 | 28 | 1 | RO
cap_local_admin | 0x00000000 | 29 | 1 | RO
operation_type | 0x00000000 | 30 | 2 | INDEX
tclass | 0x00000004 | 0 | 4 | RW
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg QTCTM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
mc | 0x00000004 | 0 | 1 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg ROCE_ACCL
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
================================================================================================
roce_adp_retrans_field_select | 0x00000000 | 0 | 1 | RW
roce_tx_window_field_select | 0x00000000 | 1 | 1 | RW
roce_slow_restart_field_select | 0x00000000 | 2 | 1 | RW
roce_slow_restart_idle_field_select | 0x00000000 | 3 | 1 | RW
roce_adp_retrans_en | 0x00000004 | 0 | 1 | RW
roce_tx_window_en | 0x00000004 | 1 | 1 | RW
roce_slow_restart_en | 0x00000004 | 2 | 1 | RW
roce_slow_restart_idle_en | 0x00000004 | 3 | 1 | RW
================================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBCAM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==========================================================================================
access_reg_group | 0x00000000 | 0 | 8 | INDEX
feature_group | 0x00000000 | 16 | 8 | INDEX
sb_access_reg_cap_mask[0] | 0x00000008 | 0 | 32 | RO
sb_access_reg_cap_mask[1] | 0x0000000c | 0 | 32 | RO
sb_access_reg_cap_mask[2] | 0x00000010 | 0 | 32 | RO
sb_access_reg_cap_mask[3] | 0x00000014 | 0 | 32 | RO
sb_feature_cap_mask[0] | 0x00000028 | 0 | 32 | RO
sb_feature_cap_mask[1] | 0x0000002c | 0 | 32 | RO
sb_feature_cap_mask[2] | 0x00000030 | 0 | 32 | RO
sb_feature_cap_mask[3] | 0x00000034 | 0 | 32 | RO
cap_total_descriptors | 0x0000003c | 16 | 16 | RO
cap_total_buffer_size | 0x00000040 | 0 | 32 | RO
cap_num_pool_supported | 0x00000044 | 0 | 8 | RO
cap_max_pg_buffers | 0x00000044 | 8 | 8 | RO
cap_cell_size | 0x00000044 | 16 | 16 | RO
cap_max_cpu_ingress_tclass_sb | 0x00000048 | 0 | 8 | RO
cap_max_tclass_sb | 0x00000048 | 8 | 8 | RO
cap_sbsr_stat_size | 0x00000048 | 16 | 8 | RO
==========================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBCM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================================
dir | 0x00000000 | 0 | 2 | INDEX
pg_buff | 0x00000000 | 8 | 6 | INDEX
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
snap | 0x00000000 | 30 | 1 | OP
desc | 0x00000000 | 31 | 1 | INDEX
exc | 0x00000004 | 0 | 1 | RW
buff_occupancy | 0x00000010 | 0 | 24 | RO
max_buff_occupancy | 0x00000014 | 0 | 24 | RO
clr | 0x00000014 | 31 | 1 | OP
min_buff | 0x00000018 | 0 | 24 | RW
max_buff | 0x0000001c | 0 | 24 | RW
infi_max | 0x0000001c | 31 | 1 | RW
pool | 0x00000024 | 0 | 4 | RW
===============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBCTC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================
mode | 0x00000000 | 0 | 1 | RW
res | 0x00000000 | 4 | 1 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
dir_ing | 0x00000000 | 24 | 2 | INDEX
event | 0x00000004 | 0 | 2 | RW
en_config | 0x00000004 | 31 | 1 | WO
tclass_en_high | 0x00000008 | 0 | 32 | RW
tclass_en_low | 0x0000000c | 0 | 32 | RW
thr_max | 0x00000010 | 0 | 24 | RW
===========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBCTR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================================
entity | 0x00000000 | 0 | 2 | RO
fp | 0x00000000 | 4 | 1 | RO
dir_ing | 0x00000000 | 8 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
ievent | 0x00000000 | 31 | 1 | OP
tclass_vector_high | 0x00000008 | 0 | 32 | RO
tclass_vector_low | 0x0000000c | 0 | 32 | RO
===============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBCTS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==================================================================================
clear | 0x00000000 | 31 | 1 | OP
trap_overflow_counter | 0x00000010 | 0 | 24 | RO
==================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBDCC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
================================================================
clr | 0x00000000 | 31 | 1 | OP
hi | 0x00000010 | 0 | 32 | RO
lo | 0x00000014 | 0 | 32 | RO
hi | 0x00000018 | 0 | 32 | RO
lo | 0x0000001c | 0 | 32 | RO
hi | 0x00000020 | 0 | 32 | RO
lo | 0x00000024 | 0 | 32 | RO
hi | 0x00000028 | 0 | 32 | RO
lo | 0x0000002c | 0 | 32 | RO
hi | 0x00000030 | 0 | 32 | RO
lo | 0x00000034 | 0 | 32 | RO
hi | 0x00000038 | 0 | 32 | RO
lo | 0x0000003c | 0 | 32 | RO
hi | 0x00000040 | 0 | 32 | RO
lo | 0x00000044 | 0 | 32 | RO
hi | 0x00000048 | 0 | 32 | RO
lo | 0x0000004c | 0 | 32 | RO
hi | 0x00000050 | 0 | 32 | RO
lo | 0x00000054 | 0 | 32 | RO
hi | 0x00000058 | 0 | 32 | RO
lo | 0x0000005c | 0 | 32 | RO
hi | 0x00000060 | 0 | 32 | RO
lo | 0x00000064 | 0 | 32 | RO
hi | 0x00000068 | 0 | 32 | RO
lo | 0x0000006c | 0 | 32 | RO
hi | 0x00000070 | 0 | 32 | RO
lo | 0x00000074 | 0 | 32 | RO
hi | 0x00000078 | 0 | 32 | RO
lo | 0x0000007c | 0 | 32 | RO
hi | 0x00000080 | 0 | 32 | RO
lo | 0x00000084 | 0 | 32 | RO
hi | 0x00000088 | 0 | 32 | RO
lo | 0x0000008c | 0 | 32 | RO
hi | 0x00000090 | 0 | 32 | RO
lo | 0x00000094 | 0 | 32 | RO
hi | 0x00000098 | 0 | 32 | RO
lo | 0x0000009c | 0 | 32 | RO
hi | 0x000000a0 | 0 | 32 | RO
lo | 0x000000a4 | 0 | 32 | RO
hi | 0x000000a8 | 0 | 32 | RO
lo | 0x000000ac | 0 | 32 | RO
hi | 0x000000b0 | 0 | 32 | RO
lo | 0x000000b4 | 0 | 32 | RO
hi | 0x000000b8 | 0 | 32 | RO
lo | 0x000000bc | 0 | 32 | RO
hi | 0x000000c0 | 0 | 32 | RO
lo | 0x000000c4 | 0 | 32 | RO
hi | 0x000000c8 | 0 | 32 | RO
lo | 0x000000cc | 0 | 32 | RO
hi | 0x000000d0 | 0 | 32 | RO
lo | 0x000000d4 | 0 | 32 | RO
hi | 0x000000d8 | 0 | 32 | RO
lo | 0x000000dc | 0 | 32 | RO
hi | 0x000000e0 | 0 | 32 | RO
lo | 0x000000e4 | 0 | 32 | RO
hi | 0x000000e8 | 0 | 32 | RO
lo | 0x000000ec | 0 | 32 | RO
hi | 0x000000f0 | 0 | 32 | RO
lo | 0x000000f4 | 0 | 32 | RO
hi | 0x000000f8 | 0 | 32 | RO
lo | 0x000000fc | 0 | 32 | RO
hi | 0x00000100 | 0 | 32 | RO
lo | 0x00000104 | 0 | 32 | RO
hi | 0x00000108 | 0 | 32 | RO
lo | 0x0000010c | 0 | 32 | RO
hi | 0x00000110 | 0 | 32 | RO
lo | 0x00000114 | 0 | 32 | RO
hi | 0x00000118 | 0 | 32 | RO
lo | 0x0000011c | 0 | 32 | RO
hi | 0x00000120 | 0 | 32 | RO
lo | 0x00000124 | 0 | 32 | RO
hi | 0x00000128 | 0 | 32 | RO
lo | 0x0000012c | 0 | 32 | RO
hi | 0x00000130 | 0 | 32 | RO
lo | 0x00000134 | 0 | 32 | RO
hi | 0x00000138 | 0 | 32 | RO
lo | 0x0000013c | 0 | 32 | RO
hi | 0x00000140 | 0 | 32 | RO
lo | 0x00000144 | 0 | 32 | RO
hi | 0x00000148 | 0 | 32 | RO
lo | 0x0000014c | 0 | 32 | RO
hi | 0x00000150 | 0 | 32 | RO
lo | 0x00000154 | 0 | 32 | RO
hi | 0x00000158 | 0 | 32 | RO
lo | 0x0000015c | 0 | 32 | RO
hi | 0x00000160 | 0 | 32 | RO
lo | 0x00000164 | 0 | 32 | RO
hi | 0x00000168 | 0 | 32 | RO
lo | 0x0000016c | 0 | 32 | RO
hi | 0x00000170 | 0 | 32 | RO
lo | 0x00000174 | 0 | 32 | RO
hi | 0x00000178 | 0 | 32 | RO
lo | 0x0000017c | 0 | 32 | RO
hi | 0x00000180 | 0 | 32 | RO
lo | 0x00000184 | 0 | 32 | RO
hi | 0x00000188 | 0 | 32 | RO
lo | 0x0000018c | 0 | 32 | RO
hi | 0x00000190 | 0 | 32 | RO
lo | 0x00000194 | 0 | 32 | RO
hi | 0x00000198 | 0 | 32 | RO
lo | 0x0000019c | 0 | 32 | RO
hi | 0x000001a0 | 0 | 32 | RO
lo | 0x000001a4 | 0 | 32 | RO
hi | 0x000001a8 | 0 | 32 | RO
lo | 0x000001ac | 0 | 32 | RO
hi | 0x000001b0 | 0 | 32 | RO
lo | 0x000001b4 | 0 | 32 | RO
hi | 0x000001b8 | 0 | 32 | RO
lo | 0x000001bc | 0 | 32 | RO
hi | 0x000001c0 | 0 | 32 | RO
lo | 0x000001c4 | 0 | 32 | RO
hi | 0x000001c8 | 0 | 32 | RO
lo | 0x000001cc | 0 | 32 | RO
hi | 0x000001d0 | 0 | 32 | RO
lo | 0x000001d4 | 0 | 32 | RO
hi | 0x000001d8 | 0 | 32 | RO
lo | 0x000001dc | 0 | 32 | RO
hi | 0x000001e0 | 0 | 32 | RO
lo | 0x000001e4 | 0 | 32 | RO
hi | 0x000001e8 | 0 | 32 | RO
lo | 0x000001ec | 0 | 32 | RO
hi | 0x000001f0 | 0 | 32 | RO
lo | 0x000001f4 | 0 | 32 | RO
hi | 0x000001f8 | 0 | 32 | RO
lo | 0x000001fc | 0 | 32 | RO
hi | 0x00000200 | 0 | 32 | RO
lo | 0x00000204 | 0 | 32 | RO
hi | 0x00000208 | 0 | 32 | RO
lo | 0x0000020c | 0 | 32 | RO
================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBDCM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
counter_index | 0x00000010 | 0 | 24 | RW
counter_set_type | 0x00000010 | 24 | 8 | RW
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBDCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
counter_index | 0x00000010 | 0 | 24 | RW
counter_set_type | 0x00000010 | 24 | 8 | RW
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBGCR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================
tele_entity | 0x00000000 | 0 | 2 | RW
cong_fp | 0x00000000 | 4 | 1 | RW
========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBHBR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
============================================================================
local_port | 0x00000000 | 16 | 8 | RW
opcode | 0x00000000 | 28 | 4 | RW
hist_id | 0x00000004 | 0 | 8 | INDEX
hist_type | 0x00000008 | 0 | 16 | RW
hist_parameters | 0x0000000c | 0 | 32 | RW
hist_min_value | 0x00000010 | 0 | 32 | RW
hist_max_value | 0x00000014 | 0 | 32 | RW
sample_time | 0x00000018 | 0 | 6 | RW
============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBHBR_V2
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================
dir | 0x00000000 | 0 | 2 | INDEX
pg_buff | 0x00000000 | 8 | 6 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
en | 0x00000004 | 0 | 1 | RW
hist_type | 0x00000008 | 0 | 16 | INDEX
mode | 0x00000008 | 28 | 3 | RW
hist_min_value | 0x00000010 | 0 | 32 | RW
hist_max_value | 0x00000014 | 0 | 32 | RW
sample_time | 0x00000018 | 0 | 6 | RW
===========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBHPC
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================
max_buff | 0x00000010 | 0 | 24 | RW
buff_occupancy | 0x00000020 | 0 | 24 | RO
===========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBHRR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
====================================================================
clr | 0x00000000 | 31 | 1 | OP
hist_id | 0x00000004 | 0 | 8 | INDEX
hi | 0x00000010 | 0 | 32 | RO
lo | 0x00000014 | 0 | 32 | RO
hi | 0x00000018 | 0 | 32 | RO
lo | 0x0000001c | 0 | 32 | RO
hi | 0x00000020 | 0 | 32 | RO
lo | 0x00000024 | 0 | 32 | RO
hi | 0x00000028 | 0 | 32 | RO
lo | 0x0000002c | 0 | 32 | RO
hi | 0x00000030 | 0 | 32 | RO
lo | 0x00000034 | 0 | 32 | RO
hi | 0x00000038 | 0 | 32 | RO
lo | 0x0000003c | 0 | 32 | RO
hi | 0x00000040 | 0 | 32 | RO
lo | 0x00000044 | 0 | 32 | RO
hi | 0x00000048 | 0 | 32 | RO
lo | 0x0000004c | 0 | 32 | RO
hi | 0x00000050 | 0 | 32 | RO
lo | 0x00000054 | 0 | 32 | RO
hi | 0x00000058 | 0 | 32 | RO
lo | 0x0000005c | 0 | 32 | RO
====================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBHRR_V2
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
dir | 0x00000000 | 0 | 2 | INDEX
pg_buff | 0x00000000 | 8 | 6 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
clr | 0x00000000 | 31 | 1 | OP
hist_type | 0x00000008 | 0 | 16 | INDEX
min_sampled_high | 0x00000010 | 0 | 32 | RO
min_sampled_low | 0x00000014 | 0 | 32 | RO
max_sampled_high | 0x00000018 | 0 | 32 | RO
max_sampled_low | 0x0000001c | 0 | 32 | RO
hi | 0x00000040 | 0 | 32 | RO
lo | 0x00000044 | 0 | 32 | RO
hi | 0x00000048 | 0 | 32 | RO
lo | 0x0000004c | 0 | 32 | RO
hi | 0x00000050 | 0 | 32 | RO
lo | 0x00000054 | 0 | 32 | RO
hi | 0x00000058 | 0 | 32 | RO
lo | 0x0000005c | 0 | 32 | RO
hi | 0x00000060 | 0 | 32 | RO
lo | 0x00000064 | 0 | 32 | RO
hi | 0x00000068 | 0 | 32 | RO
lo | 0x0000006c | 0 | 32 | RO
hi | 0x00000070 | 0 | 32 | RO
lo | 0x00000074 | 0 | 32 | RO
hi | 0x00000078 | 0 | 32 | RO
lo | 0x0000007c | 0 | 32 | RO
hi | 0x00000080 | 0 | 32 | RO
lo | 0x00000084 | 0 | 32 | RO
hi | 0x00000088 | 0 | 32 | RO
lo | 0x0000008c | 0 | 32 | RO
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBIB
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
int_buffer_index | 0x00000000 | 0 | 8 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
status | 0x00000004 | 28 | 4 | RO
buff_size | 0x00000008 | 0 | 24 | RW
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBME
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=======================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
desc | 0x00000000 | 31 | 1 | INDEX
pool | 0x00000024 | 0 | 4 | RW
=======================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBMM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================================
prio | 0x00000000 | 8 | 4 | INDEX
snap | 0x00000000 | 30 | 1 | OP
buff_occupancy | 0x00000010 | 0 | 24 | RO
max_buff_occupancy | 0x00000014 | 0 | 24 | RO
clr | 0x00000014 | 31 | 1 | OP
min_buff | 0x00000018 | 0 | 24 | RW
max_buff | 0x0000001c | 0 | 24 | RW
infi_max | 0x0000001c | 31 | 1 | RW
pool | 0x00000024 | 0 | 4 | RW
===============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBPM
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================================
dir | 0x00000000 | 0 | 2 | INDEX
pool | 0x00000000 | 8 | 4 | INDEX
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
snap | 0x00000000 | 30 | 1 | OP
desc | 0x00000000 | 31 | 1 | INDEX
buff_occupancy | 0x00000010 | 0 | 24 | RO
max_buff_occupancy | 0x00000014 | 0 | 24 | RO
clr | 0x00000014 | 31 | 1 | OP
min_buff | 0x00000018 | 0 | 24 | RW
max_buff | 0x0000001c | 0 | 24 | RW
infi_max | 0x0000001c | 31 | 1 | RW
===============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBPR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================================
pool | 0x00000000 | 0 | 4 | INDEX
dir | 0x00000000 | 24 | 2 | INDEX
snap | 0x00000000 | 30 | 1 | OP
desc | 0x00000000 | 31 | 1 | INDEX
size | 0x00000004 | 0 | 24 | RW
infi_size | 0x00000004 | 31 | 1 | RW
mode | 0x00000008 | 0 | 4 | RW
buff_occupancy | 0x0000000c | 0 | 24 | RO
max_buff_occupancy | 0x00000010 | 0 | 24 | RO
clr | 0x00000010 | 31 | 1 | OP
ext_buff_occupancy | 0x00000014 | 0 | 24 | RO
===============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBSNS
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===============================================================================
status | 0x00000000 | 0 | 1 | RO
trigger_id | 0x00000004 | 0 | 4 | RO
trigger_parameters | 0x00000008 | 0 | 16 | RO
time_high | 0x00000010 | 0 | 6 | RO
time_low | 0x00000014 | 0 | 32 | RO
===============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBSNT
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================
take | 0x00000000 | 0 | 2 | OP
=================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBSNTE
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
===========================================================================
local_port | 0x00000000 | 16 | 8 | INDEX
type | 0x00000004 | 0 | 4 | INDEX
tclass_en_high | 0x00000008 | 0 | 32 | RW
tclass_en_low | 0x0000000c | 0 | 32 | RW
===========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SBSR
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================================
ports | 0x00000000 | 0 | 1 | INDEX
pnat | 0x00000000 | 14 | 2 | INDEX
snap | 0x00000000 | 30 | 1 | INDEX
clr | 0x00000000 | 31 | 1 | OP
desc | 0x00000004 | 31 | 1 | INDEX
ingress_port_mask[0] | 0x00000010 | 0 | 32 | INDEX
ingress_port_mask[1] | 0x00000014 | 0 | 32 | INDEX
ingress_port_mask[2] | 0x00000018 | 0 | 32 | INDEX
ingress_port_mask[3] | 0x0000001c | 0 | 32 | INDEX
ingress_port_mask[4] | 0x00000020 | 0 | 32 | INDEX
ingress_port_mask[5] | 0x00000024 | 0 | 32 | INDEX
ingress_port_mask[6] | 0x00000028 | 0 | 32 | INDEX
ingress_port_mask[7] | 0x0000002c | 0 | 32 | INDEX
pg_buff_mask | 0x00000030 | 0 | 10 | INDEX
egress_port_mask[0] | 0x00000034 | 0 | 32 | INDEX
egress_port_mask[1] | 0x00000038 | 0 | 32 | INDEX
egress_port_mask[2] | 0x0000003c | 0 | 32 | INDEX
egress_port_mask[3] | 0x00000040 | 0 | 32 | INDEX
egress_port_mask[4] | 0x00000044 | 0 | 32 | INDEX
egress_port_mask[5] | 0x00000048 | 0 | 32 | INDEX
egress_port_mask[6] | 0x0000004c | 0 | 32 | INDEX
egress_port_mask[7] | 0x00000050 | 0 | 32 | INDEX
hi | 0x00000054 | 0 | 32 | INDEX
lo | 0x00000058 | 0 | 32 | INDEX
buff_occupancy | 0x0000005c | 0 | 24 | RO
max_buff_occupancy | 0x00000060 | 0 | 24 | RO
buff_occupancy | 0x00000064 | 0 | 24 | RO
max_buff_occupancy | 0x00000068 | 0 | 24 | RO
buff_occupancy | 0x0000006c | 0 | 24 | RO
max_buff_occupancy | 0x00000070 | 0 | 24 | RO
buff_occupancy | 0x00000074 | 0 | 24 | RO
max_buff_occupancy | 0x00000078 | 0 | 24 | RO
buff_occupancy | 0x0000007c | 0 | 24 | RO
max_buff_occupancy | 0x00000080 | 0 | 24 | RO
buff_occupancy | 0x00000084 | 0 | 24 | RO
max_buff_occupancy | 0x00000088 | 0 | 24 | RO
buff_occupancy | 0x0000008c | 0 | 24 | RO
max_buff_occupancy | 0x00000090 | 0 | 24 | RO
buff_occupancy | 0x00000094 | 0 | 24 | RO
max_buff_occupancy | 0x00000098 | 0 | 24 | RO
buff_occupancy | 0x0000009c | 0 | 24 | RO
max_buff_occupancy | 0x000000a0 | 0 | 24 | RO
buff_occupancy | 0x000000a4 | 0 | 24 | RO
max_buff_occupancy | 0x000000a8 | 0 | 24 | RO
buff_occupancy | 0x000000ac | 0 | 24 | RO
max_buff_occupancy | 0x000000b0 | 0 | 24 | RO
buff_occupancy | 0x000000b4 | 0 | 24 | RO
max_buff_occupancy | 0x000000b8 | 0 | 24 | RO
buff_occupancy | 0x000000bc | 0 | 24 | RO
max_buff_occupancy | 0x000000c0 | 0 | 24 | RO
buff_occupancy | 0x000000c4 | 0 | 24 | RO
max_buff_occupancy | 0x000000c8 | 0 | 24 | RO
buff_occupancy | 0x000000cc | 0 | 24 | RO
max_buff_occupancy | 0x000000d0 | 0 | 24 | RO
buff_occupancy | 0x000000d4 | 0 | 24 | RO
max_buff_occupancy | 0x000000d8 | 0 | 24 | RO
buff_occupancy | 0x000000dc | 0 | 24 | RO
max_buff_occupancy | 0x000000e0 | 0 | 24 | RO
buff_occupancy | 0x000000e4 | 0 | 24 | RO
max_buff_occupancy | 0x000000e8 | 0 | 24 | RO
buff_occupancy | 0x000000ec | 0 | 24 | RO
max_buff_occupancy | 0x000000f0 | 0 | 24 | RO
buff_occupancy | 0x000000f4 | 0 | 24 | RO
max_buff_occupancy | 0x000000f8 | 0 | 24 | RO
=================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SET_NODE
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=================================================================================
node_description[0] | 0x00000000 | 0 | 32 | RW
node_description[1] | 0x00000004 | 0 | 32 | RW
node_description[2] | 0x00000008 | 0 | 32 | RW
node_description[3] | 0x0000000c | 0 | 32 | RW
node_description[4] | 0x00000010 | 0 | 32 | RW
node_description[5] | 0x00000014 | 0 | 32 | RW
node_description[6] | 0x00000018 | 0 | 32 | RW
node_description[7] | 0x0000001c | 0 | 32 | RW
node_description[8] | 0x00000020 | 0 | 32 | RW
node_description[9] | 0x00000024 | 0 | 32 | RW
node_description[10] | 0x00000028 | 0 | 32 | RW
node_description[11] | 0x0000002c | 0 | 32 | RW
node_description[12] | 0x00000030 | 0 | 32 | RW
node_description[13] | 0x00000034 | 0 | 32 | RW
node_description[14] | 0x00000038 | 0 | 32 | RW
node_description[15] | 0x0000003c | 0 | 32 | RW
=================================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SLRED
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
=============================================================================
page_data_sel | 0x00000000 | 0 | 4 | INDEX
lane | 0x00000000 | 8 | 4 | INDEX
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
version | 0x00000000 | 24 | 4 | RO
status | 0x00000000 | 28 | 4 | RO
lane_speed | 0x00000004 | 0 | 4 | RO
abort | 0x00000004 | 14 | 1 | WO
err_res_base | 0x00000004 | 15 | 3 | RW
eye_sel | 0x00000004 | 18 | 2 | RW
measure_time | 0x00000004 | 20 | 4 | RW
eye_diag_dim | 0x00000004 | 24 | 3 | RW
err_res_scale | 0x00000004 | 27 | 2 | RW
destructive_ctrl | 0x00000004 | 29 | 1 | RW
last_scan | 0x00000004 | 30 | 1 | WO
en | 0x00000004 | 31 | 1 | WO
mv_ticks_res | 0x00000008 | 0 | 16 | RO
ps_ticks_res | 0x00000008 | 16 | 16 | RO
mv_center_pos | 0x0000000c | 0 | 16 | RO
ps_center_pos | 0x0000000c | 16 | 16 | RO
margin | 0x00000010 | 0 | 24 | RO
margin_version | 0x00000010 | 24 | 8 | RO
height_eo_neg | 0x00000014 | 0 | 16 | RO
height_eo_pos | 0x00000014 | 16 | 16 | RO
phase_eo_neg | 0x00000018 | 0 | 16 | RO
phase_eo_pos | 0x00000018 | 16 | 16 | RO
err_val[7] | 0x00000008 | 0 | 4 | RO
err_val[6] | 0x00000008 | 4 | 4 | RO
err_val[5] | 0x00000008 | 8 | 4 | RO
err_val[4] | 0x00000008 | 12 | 4 | RO
err_val[3] | 0x00000008 | 16 | 4 | RO
err_val[2] | 0x00000008 | 20 | 4 | RO
err_val[1] | 0x00000008 | 24 | 4 | RO
err_val[0] | 0x00000008 | 28 | 4 | RO
err_val[15] | 0x0000000c | 0 | 4 | RO
err_val[14] | 0x0000000c | 4 | 4 | RO
err_val[13] | 0x0000000c | 8 | 4 | RO
err_val[12] | 0x0000000c | 12 | 4 | RO
err_val[11] | 0x0000000c | 16 | 4 | RO
err_val[10] | 0x0000000c | 20 | 4 | RO
err_val[9] | 0x0000000c | 24 | 4 | RO
err_val[8] | 0x0000000c | 28 | 4 | RO
err_val[23] | 0x00000010 | 0 | 4 | RO
err_val[22] | 0x00000010 | 4 | 4 | RO
err_val[21] | 0x00000010 | 8 | 4 | RO
err_val[20] | 0x00000010 | 12 | 4 | RO
err_val[19] | 0x00000010 | 16 | 4 | RO
err_val[18] | 0x00000010 | 20 | 4 | RO
err_val[17] | 0x00000010 | 24 | 4 | RO
err_val[16] | 0x00000010 | 28 | 4 | RO
err_val[31] | 0x00000014 | 0 | 4 | RO
err_val[30] | 0x00000014 | 4 | 4 | RO
err_val[29] | 0x00000014 | 8 | 4 | RO
err_val[28] | 0x00000014 | 12 | 4 | RO
err_val[27] | 0x00000014 | 16 | 4 | RO
err_val[26] | 0x00000014 | 20 | 4 | RO
err_val[25] | 0x00000014 | 24 | 4 | RO
err_val[24] | 0x00000014 | 28 | 4 | RO
err_val[39] | 0x00000018 | 0 | 4 | RO
err_val[38] | 0x00000018 | 4 | 4 | RO
err_val[37] | 0x00000018 | 8 | 4 | RO
err_val[36] | 0x00000018 | 12 | 4 | RO
err_val[35] | 0x00000018 | 16 | 4 | RO
err_val[34] | 0x00000018 | 20 | 4 | RO
err_val[33] | 0x00000018 | 24 | 4 | RO
err_val[32] | 0x00000018 | 28 | 4 | RO
err_val[47] | 0x0000001c | 0 | 4 | RO
err_val[46] | 0x0000001c | 4 | 4 | RO
err_val[45] | 0x0000001c | 8 | 4 | RO
err_val[44] | 0x0000001c | 12 | 4 | RO
err_val[43] | 0x0000001c | 16 | 4 | RO
err_val[42] | 0x0000001c | 20 | 4 | RO
err_val[41] | 0x0000001c | 24 | 4 | RO
err_val[40] | 0x0000001c | 28 | 4 | RO
err_val[55] | 0x00000020 | 0 | 4 | RO
err_val[54] | 0x00000020 | 4 | 4 | RO
err_val[53] | 0x00000020 | 8 | 4 | RO
err_val[52] | 0x00000020 | 12 | 4 | RO
err_val[51] | 0x00000020 | 16 | 4 | RO
err_val[50] | 0x00000020 | 20 | 4 | RO
err_val[49] | 0x00000020 | 24 | 4 | RO
err_val[48] | 0x00000020 | 28 | 4 | RO
err_val[63] | 0x00000024 | 0 | 4 | RO
err_val[62] | 0x00000024 | 4 | 4 | RO
err_val[61] | 0x00000024 | 8 | 4 | RO
err_val[60] | 0x00000024 | 12 | 4 | RO
err_val[59] | 0x00000024 | 16 | 4 | RO
err_val[58] | 0x00000024 | 20 | 4 | RO
err_val[57] | 0x00000024 | 24 | 4 | RO
err_val[56] | 0x00000024 | 28 | 4 | RO
err_val[71] | 0x00000028 | 0 | 4 | RO
err_val[70] | 0x00000028 | 4 | 4 | RO
err_val[69] | 0x00000028 | 8 | 4 | RO
err_val[68] | 0x00000028 | 12 | 4 | RO
err_val[67] | 0x00000028 | 16 | 4 | RO
err_val[66] | 0x00000028 | 20 | 4 | RO
err_val[65] | 0x00000028 | 24 | 4 | RO
err_val[64] | 0x00000028 | 28 | 4 | RO
err_val[79] | 0x0000002c | 0 | 4 | RO
err_val[78] | 0x0000002c | 4 | 4 | RO
err_val[77] | 0x0000002c | 8 | 4 | RO
err_val[76] | 0x0000002c | 12 | 4 | RO
err_val[75] | 0x0000002c | 16 | 4 | RO
err_val[74] | 0x0000002c | 20 | 4 | RO
err_val[73] | 0x0000002c | 24 | 4 | RO
err_val[72] | 0x0000002c | 28 | 4 | RO
err_val[87] | 0x00000030 | 0 | 4 | RO
err_val[86] | 0x00000030 | 4 | 4 | RO
err_val[85] | 0x00000030 | 8 | 4 | RO
err_val[84] | 0x00000030 | 12 | 4 | RO
err_val[83] | 0x00000030 | 16 | 4 | RO
err_val[82] | 0x00000030 | 20 | 4 | RO
err_val[81] | 0x00000030 | 24 | 4 | RO
err_val[80] | 0x00000030 | 28 | 4 | RO
err_val[95] | 0x00000034 | 0 | 4 | RO
err_val[94] | 0x00000034 | 4 | 4 | RO
err_val[93] | 0x00000034 | 8 | 4 | RO
err_val[92] | 0x00000034 | 12 | 4 | RO
err_val[91] | 0x00000034 | 16 | 4 | RO
err_val[90] | 0x00000034 | 20 | 4 | RO
err_val[89] | 0x00000034 | 24 | 4 | RO
err_val[88] | 0x00000034 | 28 | 4 | RO
err_val[103] | 0x00000038 | 0 | 4 | RO
err_val[102] | 0x00000038 | 4 | 4 | RO
err_val[101] | 0x00000038 | 8 | 4 | RO
err_val[100] | 0x00000038 | 12 | 4 | RO
err_val[99] | 0x00000038 | 16 | 4 | RO
err_val[98] | 0x00000038 | 20 | 4 | RO
err_val[97] | 0x00000038 | 24 | 4 | RO
err_val[96] | 0x00000038 | 28 | 4 | RO
err_val[111] | 0x0000003c | 0 | 4 | RO
err_val[110] | 0x0000003c | 4 | 4 | RO
err_val[109] | 0x0000003c | 8 | 4 | RO
err_val[108] | 0x0000003c | 12 | 4 | RO
err_val[107] | 0x0000003c | 16 | 4 | RO
err_val[106] | 0x0000003c | 20 | 4 | RO
err_val[105] | 0x0000003c | 24 | 4 | RO
err_val[104] | 0x0000003c | 28 | 4 | RO
err_val[119] | 0x00000040 | 0 | 4 | RO
err_val[118] | 0x00000040 | 4 | 4 | RO
err_val[117] | 0x00000040 | 8 | 4 | RO
err_val[116] | 0x00000040 | 12 | 4 | RO
err_val[115] | 0x00000040 | 16 | 4 | RO
err_val[114] | 0x00000040 | 20 | 4 | RO
err_val[113] | 0x00000040 | 24 | 4 | RO
err_val[112] | 0x00000040 | 28 | 4 | RO
err_val[127] | 0x00000044 | 0 | 4 | RO
err_val[126] | 0x00000044 | 4 | 4 | RO
err_val[125] | 0x00000044 | 8 | 4 | RO
err_val[124] | 0x00000044 | 12 | 4 | RO
err_val[123] | 0x00000044 | 16 | 4 | RO
err_val[122] | 0x00000044 | 20 | 4 | RO
err_val[121] | 0x00000044 | 24 | 4 | RO
err_val[120] | 0x00000044 | 28 | 4 | RO
err_val[135] | 0x00000048 | 0 | 4 | RO
err_val[134] | 0x00000048 | 4 | 4 | RO
err_val[133] | 0x00000048 | 8 | 4 | RO
err_val[132] | 0x00000048 | 12 | 4 | RO
err_val[131] | 0x00000048 | 16 | 4 | RO
err_val[130] | 0x00000048 | 20 | 4 | RO
err_val[129] | 0x00000048 | 24 | 4 | RO
err_val[128] | 0x00000048 | 28 | 4 | RO
err_val[143] | 0x0000004c | 0 | 4 | RO
err_val[142] | 0x0000004c | 4 | 4 | RO
err_val[141] | 0x0000004c | 8 | 4 | RO
err_val[140] | 0x0000004c | 12 | 4 | RO
err_val[139] | 0x0000004c | 16 | 4 | RO
err_val[138] | 0x0000004c | 20 | 4 | RO
err_val[137] | 0x0000004c | 24 | 4 | RO
err_val[136] | 0x0000004c | 28 | 4 | RO
err_val[151] | 0x00000050 | 0 | 4 | RO
err_val[150] | 0x00000050 | 4 | 4 | RO
err_val[149] | 0x00000050 | 8 | 4 | RO
err_val[148] | 0x00000050 | 12 | 4 | RO
err_val[147] | 0x00000050 | 16 | 4 | RO
err_val[146] | 0x00000050 | 20 | 4 | RO
err_val[145] | 0x00000050 | 24 | 4 | RO
err_val[144] | 0x00000050 | 28 | 4 | RO
err_val[159] | 0x00000054 | 0 | 4 | RO
err_val[158] | 0x00000054 | 4 | 4 | RO
err_val[157] | 0x00000054 | 8 | 4 | RO
err_val[156] | 0x00000054 | 12 | 4 | RO
err_val[155] | 0x00000054 | 16 | 4 | RO
err_val[154] | 0x00000054 | 20 | 4 | RO
err_val[153] | 0x00000054 | 24 | 4 | RO
err_val[152] | 0x00000054 | 28 | 4 | RO
err_val[167] | 0x00000058 | 0 | 4 | RO
err_val[166] | 0x00000058 | 4 | 4 | RO
err_val[165] | 0x00000058 | 8 | 4 | RO
err_val[164] | 0x00000058 | 12 | 4 | RO
err_val[163] | 0x00000058 | 16 | 4 | RO
err_val[162] | 0x00000058 | 20 | 4 | RO
err_val[161] | 0x00000058 | 24 | 4 | RO
err_val[160] | 0x00000058 | 28 | 4 | RO
err_val[175] | 0x0000005c | 0 | 4 | RO
err_val[174] | 0x0000005c | 4 | 4 | RO
err_val[173] | 0x0000005c | 8 | 4 | RO
err_val[172] | 0x0000005c | 12 | 4 | RO
err_val[171] | 0x0000005c | 16 | 4 | RO
err_val[170] | 0x0000005c | 20 | 4 | RO
err_val[169] | 0x0000005c | 24 | 4 | RO
err_val[168] | 0x0000005c | 28 | 4 | RO
err_val[183] | 0x00000060 | 0 | 4 | RO
err_val[182] | 0x00000060 | 4 | 4 | RO
err_val[181] | 0x00000060 | 8 | 4 | RO
err_val[180] | 0x00000060 | 12 | 4 | RO
err_val[179] | 0x00000060 | 16 | 4 | RO
err_val[178] | 0x00000060 | 20 | 4 | RO
err_val[177] | 0x00000060 | 24 | 4 | RO
err_val[176] | 0x00000060 | 28 | 4 | RO
err_val[191] | 0x00000064 | 0 | 4 | RO
err_val[190] | 0x00000064 | 4 | 4 | RO
err_val[189] | 0x00000064 | 8 | 4 | RO
err_val[188] | 0x00000064 | 12 | 4 | RO
err_val[187] | 0x00000064 | 16 | 4 | RO
err_val[186] | 0x00000064 | 20 | 4 | RO
err_val[185] | 0x00000064 | 24 | 4 | RO
err_val[184] | 0x00000064 | 28 | 4 | RO
err_val[199] | 0x00000068 | 0 | 4 | RO
err_val[198] | 0x00000068 | 4 | 4 | RO
err_val[197] | 0x00000068 | 8 | 4 | RO
err_val[196] | 0x00000068 | 12 | 4 | RO
err_val[195] | 0x00000068 | 16 | 4 | RO
err_val[194] | 0x00000068 | 20 | 4 | RO
err_val[193] | 0x00000068 | 24 | 4 | RO
err_val[192] | 0x00000068 | 28 | 4 | RO
err_val[207] | 0x0000006c | 0 | 4 | RO
err_val[206] | 0x0000006c | 4 | 4 | RO
err_val[205] | 0x0000006c | 8 | 4 | RO
err_val[204] | 0x0000006c | 12 | 4 | RO
err_val[203] | 0x0000006c | 16 | 4 | RO
err_val[202] | 0x0000006c | 20 | 4 | RO
err_val[201] | 0x0000006c | 24 | 4 | RO
err_val[200] | 0x0000006c | 28 | 4 | RO
err_val[215] | 0x00000070 | 0 | 4 | RO
err_val[214] | 0x00000070 | 4 | 4 | RO
err_val[213] | 0x00000070 | 8 | 4 | RO
err_val[212] | 0x00000070 | 12 | 4 | RO
err_val[211] | 0x00000070 | 16 | 4 | RO
err_val[210] | 0x00000070 | 20 | 4 | RO
err_val[209] | 0x00000070 | 24 | 4 | RO
err_val[208] | 0x00000070 | 28 | 4 | RO
err_val[223] | 0x00000074 | 0 | 4 | RO
err_val[222] | 0x00000074 | 4 | 4 | RO
err_val[221] | 0x00000074 | 8 | 4 | RO
err_val[220] | 0x00000074 | 12 | 4 | RO
err_val[219] | 0x00000074 | 16 | 4 | RO
err_val[218] | 0x00000074 | 20 | 4 | RO
err_val[217] | 0x00000074 | 24 | 4 | RO
err_val[216] | 0x00000074 | 28 | 4 | RO
err_val[231] | 0x00000078 | 0 | 4 | RO
err_val[230] | 0x00000078 | 4 | 4 | RO
err_val[229] | 0x00000078 | 8 | 4 | RO
err_val[228] | 0x00000078 | 12 | 4 | RO
err_val[227] | 0x00000078 | 16 | 4 | RO
err_val[226] | 0x00000078 | 20 | 4 | RO
err_val[225] | 0x00000078 | 24 | 4 | RO
err_val[224] | 0x00000078 | 28 | 4 | RO
err_val[239] | 0x0000007c | 0 | 4 | RO
err_val[238] | 0x0000007c | 4 | 4 | RO
err_val[237] | 0x0000007c | 8 | 4 | RO
err_val[236] | 0x0000007c | 12 | 4 | RO
err_val[235] | 0x0000007c | 16 | 4 | RO
err_val[234] | 0x0000007c | 20 | 4 | RO
err_val[233] | 0x0000007c | 24 | 4 | RO
err_val[232] | 0x0000007c | 28 | 4 | RO
err_val[247] | 0x00000080 | 0 | 4 | RO
err_val[246] | 0x00000080 | 4 | 4 | RO
err_val[245] | 0x00000080 | 8 | 4 | RO
err_val[244] | 0x00000080 | 12 | 4 | RO
err_val[243] | 0x00000080 | 16 | 4 | RO
err_val[242] | 0x00000080 | 20 | 4 | RO
err_val[241] | 0x00000080 | 24 | 4 | RO
err_val[240] | 0x00000080 | 28 | 4 | RO
err_val[255] | 0x00000084 | 0 | 4 | RO
err_val[254] | 0x00000084 | 4 | 4 | RO
err_val[253] | 0x00000084 | 8 | 4 | RO
err_val[252] | 0x00000084 | 12 | 4 | RO
err_val[251] | 0x00000084 | 16 | 4 | RO
err_val[250] | 0x00000084 | 20 | 4 | RO
err_val[249] | 0x00000084 | 24 | 4 | RO
err_val[248] | 0x00000084 | 28 | 4 | RO
err_val[263] | 0x00000088 | 0 | 4 | RO
err_val[262] | 0x00000088 | 4 | 4 | RO
err_val[261] | 0x00000088 | 8 | 4 | RO
err_val[260] | 0x00000088 | 12 | 4 | RO
err_val[259] | 0x00000088 | 16 | 4 | RO
err_val[258] | 0x00000088 | 20 | 4 | RO
err_val[257] | 0x00000088 | 24 | 4 | RO
err_val[256] | 0x00000088 | 28 | 4 | RO
err_val[271] | 0x0000008c | 0 | 4 | RO
err_val[270] | 0x0000008c | 4 | 4 | RO
err_val[269] | 0x0000008c | 8 | 4 | RO
err_val[268] | 0x0000008c | 12 | 4 | RO
err_val[267] | 0x0000008c | 16 | 4 | RO
err_val[266] | 0x0000008c | 20 | 4 | RO
err_val[265] | 0x0000008c | 24 | 4 | RO
err_val[264] | 0x0000008c | 28 | 4 | RO
err_val[279] | 0x00000090 | 0 | 4 | RO
err_val[278] | 0x00000090 | 4 | 4 | RO
err_val[277] | 0x00000090 | 8 | 4 | RO
err_val[276] | 0x00000090 | 12 | 4 | RO
err_val[275] | 0x00000090 | 16 | 4 | RO
err_val[274] | 0x00000090 | 20 | 4 | RO
err_val[273] | 0x00000090 | 24 | 4 | RO
err_val[272] | 0x00000090 | 28 | 4 | RO
err_val[287] | 0x00000094 | 0 | 4 | RO
err_val[286] | 0x00000094 | 4 | 4 | RO
err_val[285] | 0x00000094 | 8 | 4 | RO
err_val[284] | 0x00000094 | 12 | 4 | RO
err_val[283] | 0x00000094 | 16 | 4 | RO
err_val[282] | 0x00000094 | 20 | 4 | RO
err_val[281] | 0x00000094 | 24 | 4 | RO
err_val[280] | 0x00000094 | 28 | 4 | RO
err_val[295] | 0x00000098 | 0 | 4 | RO
err_val[294] | 0x00000098 | 4 | 4 | RO
err_val[293] | 0x00000098 | 8 | 4 | RO
err_val[292] | 0x00000098 | 12 | 4 | RO
err_val[291] | 0x00000098 | 16 | 4 | RO
err_val[290] | 0x00000098 | 20 | 4 | RO
err_val[289] | 0x00000098 | 24 | 4 | RO
err_val[288] | 0x00000098 | 28 | 4 | RO
err_val[303] | 0x0000009c | 0 | 4 | RO
err_val[302] | 0x0000009c | 4 | 4 | RO
err_val[301] | 0x0000009c | 8 | 4 | RO
err_val[300] | 0x0000009c | 12 | 4 | RO
err_val[299] | 0x0000009c | 16 | 4 | RO
err_val[298] | 0x0000009c | 20 | 4 | RO
err_val[297] | 0x0000009c | 24 | 4 | RO
err_val[296] | 0x0000009c | 28 | 4 | RO
err_val[311] | 0x000000a0 | 0 | 4 | RO
err_val[310] | 0x000000a0 | 4 | 4 | RO
err_val[309] | 0x000000a0 | 8 | 4 | RO
err_val[308] | 0x000000a0 | 12 | 4 | RO
err_val[307] | 0x000000a0 | 16 | 4 | RO
err_val[306] | 0x000000a0 | 20 | 4 | RO
err_val[305] | 0x000000a0 | 24 | 4 | RO
err_val[304] | 0x000000a0 | 28 | 4 | RO
err_val[319] | 0x000000a4 | 0 | 4 | RO
err_val[318] | 0x000000a4 | 4 | 4 | RO
err_val[317] | 0x000000a4 | 8 | 4 | RO
err_val[316] | 0x000000a4 | 12 | 4 | RO
err_val[315] | 0x000000a4 | 16 | 4 | RO
err_val[314] | 0x000000a4 | 20 | 4 | RO
err_val[313] | 0x000000a4 | 24 | 4 | RO
err_val[312] | 0x000000a4 | 28 | 4 | RO
=============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SLRG
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================
lane | 0x00000000 | 8 | 4 | INDEX
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
version | 0x00000000 | 24 | 4 | RO
status | 0x00000000 | 28 | 4 | RO
grade_lane_speed | 0x00000004 | 0 | 4 | RO
grade | 0x00000008 | 0 | 24 | RO
grade_version | 0x00000008 | 24 | 8 | RO
height_eo_neg | 0x00000018 | 0 | 16 | RO
height_eo_pos | 0x00000018 | 16 | 16 | RO
phase_eo_neg | 0x00000020 | 0 | 8 | RO
phase_eo_pos | 0x00000020 | 16 | 8 | RO
grade_lane_speed | 0x00000004 | 0 | 4 | RO
grade | 0x00000008 | 0 | 24 | RO
grade_version | 0x00000008 | 24 | 8 | RO
height_eo_neg_up | 0x0000000c | 0 | 16 | RO
height_eo_pos_up | 0x0000000c | 16 | 16 | RO
height_eo_pos_mid | 0x00000010 | 0 | 16 | RO
phase_eo_neg_up | 0x00000010 | 16 | 8 | RO
phase_eo_pos_up | 0x00000010 | 24 | 8 | RO
phase_eo_neg_mid | 0x00000014 | 0 | 8 | RO
phase_eo_pos_mid | 0x00000014 | 8 | 8 | RO
height_eo_neg_mid | 0x00000014 | 16 | 16 | RO
height_eo_neg_low | 0x00000018 | 0 | 16 | RO
height_eo_pos_low | 0x00000018 | 16 | 16 | RO
phase_eo_neg_low | 0x0000001c | 16 | 8 | RO
phase_eo_pos_low | 0x0000001c | 24 | 8 | RO
eom_measurment | 0x00000004 | 0 | 4 | OP
meas_done | 0x00000004 | 16 | 1 | RO
initial_eom | 0x00000008 | 0 | 16 | RO
initial_eom_mode | 0x00000008 | 16 | 2 | RO
lower_eye | 0x0000000c | 0 | 8 | RO
mid_eye | 0x0000000c | 8 | 8 | RO
upper_eye | 0x0000000c | 16 | 8 | RO
last_eom | 0x0000000c | 24 | 8 | RO
==============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg SLTP
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
==============================================================================
c_db | 0x00000000 | 0 | 1 | OP
lane_speed | 0x00000000 | 4 | 4 | RW
lane | 0x00000000 | 8 | 4 | INDEX
pnat | 0x00000000 | 14 | 2 | INDEX
local_port | 0x00000000 | 16 | 8 | INDEX
version | 0x00000000 | 24 | 4 | RO
status | 0x00000000 | 28 | 4 | RO
ob_tap2 | 0x00000008 | 0 | 8 | RW
ob_tap1 | 0x00000008 | 8 | 8 | RW
ob_tap0 | 0x00000008 | 16 | 8 | RW
polarity | 0x00000008 | 24 | 1 | RW
ob_bias | 0x0000000c | 0 | 8 | RW
ob_reg | 0x0000000c | 8 | 8 | RW
ob_preemp_mode | 0x0000000c | 16 | 4 | RW
ob_leva | 0x0000000c | 20 | 4 | RW
ob_bad_stat | 0x00000010 | 29 | 2 | RO
ob_norm | 0x00000010 | 31 | 1 | RO
post_tap | 0x00000008 | 0 | 8 | RW
main_tap | 0x00000008 | 8 | 8 | RW
pre_tap | 0x00000008 | 16 | 8 | RW
pre_2_tap | 0x00000008 | 24 | 8 | RW
ob_alev_out | 0x0000000c | 0 | 5 | RW
ob_amp | 0x0000000c | 8 | 7 | RW
ob_m2lp | 0x0000000c | 25 | 7 | RW
ob_bad_stat | 0x00000010 | 16 | 16 | RO
pre_tap | 0x00000004 | 0 | 16 | RW
main_tap | 0x00000004 | 16 | 16 | RW
post_tap | 0x00000008 | 0 | 16 | RW
inner_eye_1 | 0x0000000c | 0 | 16 | RW
inner_eye_2 | 0x0000000c | 16 | 16 | RW
tx_swing | 0x00000010 | 0 | 4 | RW
drv_amp | 0x00000008 | 8 | 6 | RW
fir_post1 | 0x00000008 | 15 | 5 | RW
fir_pre3 | 0x00000008 | 20 | 3 | RW
fir_pre2 | 0x00000008 | 23 | 4 | RW
fir_pre1 | 0x00000008 | 27 | 5 | RW
fir_c0 | 0x0000000c | 8 | 7 | RO
tx_fir_scale_ctrl | 0x0000000c | 31 | 1 | RW
==============================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg VHCA_TRUST_LEVEL
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
========================================================================
vhca_id | 0x00000000 | 0 | 16 | RO
all_vhca | 0x00000000 | 31 | 1 | WO
trust_level | 0x00000004 | 0 | 32 | WO
========================================================================
sudo mlxreg -d /dev/mst/mt4119_pciconf0 --show_reg ZTT
Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access
======================================================================
operation | 0x00000000 | 0 | 3 | WO
status | 0x00000000 | 8 | 3 | RO
======================================================================
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