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A Testbench
/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
** GENERATED BY CLASH 0.99. DO NOT MODIFY.
*/
module Clash01_testBench
( // No inputs
// Outputs
output wire \Clash01.testBench
);
// Clash01.hs:23:1-9
wire [0:0] \#Clash01.testBench_rec ;
wire \Clash01.testBench1 ;
wire [0:0] \#app_arg ;
wire [0:0] \#app_arg_0 ;
wire \#app_arg_1 ;
wire [1:0] input_0;
wire input_0_0;
wire input_0_1;
wire [0:0] input_1; // ** signal checked **
wire [0:0] result; // ** signal checked **
Clash01_outputVerifier Clash01_outputVerifier_Clash01testBench_rec
(.result (\#Clash01.testBench_rec )
,.\#pTS (\Clash01.testBench1 )
,.\#pTS_0 (\#app_arg_1 )
,.i (\#app_arg ));
// pragma translate_off
reg clk;
// 1 = 0.1ps
localparam half_period = 1; // (100000 / 2); // ** mod **
always begin
clk = 0;
#1 forever begin // mod
if (~ (~ \#Clash01.testBench_rec )) begin
$finish;
end
clk = ~ clk;
#half_period;
clk = ~ clk;
#half_period;
end
end
assign \Clash01.testBench1 = clk;
// pragma translate_on
assign input_0 = {\Clash01.testBench1
,\#app_arg_1 };
assign input_1 = \#app_arg_0 ;
assign input_0_0 = input_0[1:1];
assign input_0_1 = input_0[0:0];
Clash01_topEntity Clash01_topEntity_app_arg
(.\#$d(%,%)_0 (input_0_0)
,.\#$d(%,%)_1 (input_0_1)
,.eta (input_1)
,.result (result));
assign \#app_arg = result;
Clash01_stimuliGenerator Clash01_stimuliGenerator_app_arg_0
(.result (\#app_arg_0 )
,.\#pTS (\Clash01.testBench1 )
,.\#pTS_0 (\#app_arg_1 ));
// pragma translate_off
reg rst;
initial begin
$dumpfile("Clash01_testBench.vcd"); // ** add **
$dumpvars(0, Clash01_testBench); // ** add **
#1 rst = 1;
#1 rst = 0; // ** mod **
end
assign \#app_arg_1 = rst;
// pragma translate_on
assign \Clash01.testBench = \#Clash01.testBench_rec ;
endmodule
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