Flattened Calyx

flattened.futil

extern "/scratch/nrn25/data/calyx-fpga-new/calyx/primitives/core.sv" {
  comb primitive std_slice<"share"=1>[IN_WIDTH, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);
  comb primitive std_pad<"share"=1>[IN_WIDTH, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);
  comb primitive std_cat<"share"=1>[LEFT_WIDTH, RIGHT_WIDTH, OUT_WIDTH](@data left: LEFT_WIDTH, @data right: RIGHT_WIDTH) -> (out: OUT_WIDTH);
  comb primitive std_bit_slice<"share"=1>[IN_WIDTH, START_IDX, END_IDX, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);
  comb primitive std_not<"share"=1>[WIDTH](@data in: WIDTH) -> (out: WIDTH);
  comb primitive std_and<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_or<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_xor<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_sub<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_gt<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_lt<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_eq<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_neq<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_ge<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_le<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_rsh<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_mux<"share"=1>[WIDTH](@data cond: 1, @data tru: WIDTH, @data fal: WIDTH) -> (out: WIDTH);
}
primitive undef<"share"=1>[WIDTH]() -> (out: WIDTH) {
  assign out = 'x;
}
comb primitive std_const<"share"=1>[WIDTH, VALUE]() -> (out: WIDTH) {
  assign out = VALUE;
}
comb primitive std_wire<"share"=1>[WIDTH](@data in: WIDTH) -> (out: WIDTH) {
  assign out = in;
}
comb primitive std_add<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH) {
  assign out = left + right;
}
comb primitive std_lsh<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH) {
  assign out = left << right;
}
primitive std_reg<"state_share"=1>[WIDTH](@write_together @data in: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@stable out: WIDTH, @done done: 1) {
  always_ff @(posedge clk) begin
    if (reset) begin
       out <= 0;
       done <= 0;
    end else if (write_en) begin
      out <= in;
      done <= 1'd1;
    end else done <= 1'd0;
  end
}
primitive init_one_reg<"state_share"=1>[WIDTH](@write_together @data in: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@stable out: WIDTH, @done done: 1) {
  always_ff @(posedge clk) begin
    if (reset) begin
       out <= 1;
       done <= 0;
    end else if (write_en) begin
      out <= in;
      done <= 1'd1;
    end else done <= 1'd0;
  end
}
component invokee<"state_share"=1>(@go go: 1, @clk clk: 1, @reset reset: 1, ref_reg_out: 32, ref_reg_done: 1) -> (@done done: 1, @data ref_reg_in: 32, ref_reg_write_en: 1) {
  cells {
    @generated invokee_ref_reg_write_go = std_wire(1);
    @generated invokee_ref_reg_write_done = std_wire(1);
  }
  wires {
    done = invokee_ref_reg_write_done.out ? 1'd1;
    ref_reg_in = invokee_ref_reg_write_go.out ? 32'd0;
    ref_reg_write_en = invokee_ref_reg_write_go.out ? 1'd1;
    invokee_ref_reg_write_done.in = ref_reg_done;
    invokee_ref_reg_write_go.in = go;
  }
  control {}
}
component wrapper(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    @data concrete_reg = std_reg(32);
    @data invokee = invokee();
    @generated fsm = std_reg(2);
    @generated invoke0_go = std_wire(1);
    @generated invoke0_done = std_wire(1);
    @generated invoke1_go = std_wire(1);
    @generated invoke1_done = std_wire(1);
    @generated tdcc_go = std_wire(1);
    @generated tdcc_done = std_wire(1);
  }
  wires {
    invokee.ref_reg_out = invoke1_go.out ? concrete_reg.out;
    invokee.clk = clk;
    invokee.go = invoke1_go.out ? 1'd1;
    invokee.reset = reset;
    invokee.ref_reg_done = invoke1_go.out ? concrete_reg.done;
    done = tdcc_done.out ? 1'd1;
    fsm.write_en = fsm.out == 2'd2 | fsm.out == 2'd0 & invoke0_done.out & tdcc_go.out | fsm.out == 2'd1 & invoke1_done.out & tdcc_go.out ? 1'd1;
    fsm.clk = clk;
    fsm.reset = reset;
    fsm.in = fsm.out == 2'd0 & invoke0_done.out & tdcc_go.out ? 2'd1;
    fsm.in = fsm.out == 2'd2 ? 2'd0;
    fsm.in = fsm.out == 2'd1 & invoke1_done.out & tdcc_go.out ? 2'd2;
    invoke0_go.in = !invoke0_done.out & fsm.out == 2'd0 & tdcc_go.out ? 1'd1;
    tdcc_go.in = go;
    invoke0_done.in = concrete_reg.done;
    invoke1_go.in = !invoke1_done.out & fsm.out == 2'd1 & tdcc_go.out ? 1'd1;
    tdcc_done.in = fsm.out == 2'd2 ? 1'd1;
    concrete_reg.write_en = invoke1_go.out ? invokee.ref_reg_write_en;
    concrete_reg.write_en = invoke0_go.out ? 1'd1;
    concrete_reg.clk = clk;
    concrete_reg.reset = reset;
    concrete_reg.in = invoke1_go.out ? invokee.ref_reg_in;
    concrete_reg.in = invoke0_go.out ? 32'd0;
    invoke1_done.in = invokee.done;
  }
  control {}
}
component main<"toplevel"=1>(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    @generated wrapper = wrapper();
  }
  wires {
    done = wrapper.done;
    wrapper.clk = clk;
    wrapper.go = go;
    wrapper.reset = reset;
  }
  control {}
}