Bibliography for "WTF is my processor doing?" lecture @ UniBo

perf.bib

@inproceedings{nowak_establishing_2015,
	title = {Establishing a Base of Trust with Performance Counters for Enterprise Workloads},
	booktitle = {{USENIX} Annual Technical Conference},
	author = {Nowak, Andrzej and Yasin, Ahmad and Mendelson, Avi and Zwaenepoel, Willy},
	date = {2015},
}

@inproceedings{yasin_top-down_2014,
	location = {{CA}, {USA}},
	title = {A Top-Down method for performance analysis and counters architecture},
	isbn = {978-1-4799-3606-9 978-1-4799-3604-5},
	url = {http://ieeexplore.ieee.org/document/6844459/},
	doi = {10.1109/ISPASS.2014.6844459},
	abstract = {Optimizing an application’s performance for a given microarchitecture has become painfully difficult. Increasing microarchitecture complexity, workload diversity, and the unmanageable volume of data produced by performance tools increase the optimization challenges. At the same time resource and time constraints get tougher with recently emerged segments. This further calls for accurate and prompt analysis methods.},
	eventtitle = {2014 {IEEE} International Symposium on Performance Analysis of Systems and Software ({ISPASS})},
	pages = {35--44},
	booktitle = {2014 {IEEE} International Symposium on Performance Analysis of Systems and Software ({ISPASS})},
	publisher = {{IEEE}},
	author = {Yasin, Ahmad},
	urldate = {2021-12-18},
	date = {2014-03},
	langid = {english},
}

@article{yasin_tuning_2019,
	title = {Tuning Performance via Metrics with Expectations},
	volume = {18},
	issn = {1556-6056, 1556-6064, 2473-2575},
	url = {https://ieeexplore.ieee.org/document/8714063/},
	doi = {10.1109/LCA.2019.2916408},
	pages = {91--94},
	number = {2},
	journaltitle = {{IEEE} Computer Architecture Letters},
	shortjournal = {{IEEE} Comput. Arch. Lett.},
	author = {Yasin, Ahmad and Mendelson, Avi and Ben-Asher, Yosi},
	urldate = {2021-12-18},
	date = {2019-07-01},
}

@article{yasin_metric-guided_2020,
	title = {A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors},
	volume = {16},
	issn = {1544-3566, 1544-3973},
	url = {https://dl.acm.org/doi/10.1145/3369383},
	doi = {10.1145/3369383},
	abstract = {The slowdown in technology scaling puts architectural features at the forefront of the innovation in modern processors. This article presents a Metric-Guided Method ({MGM}) that extends Top-Down analysis with carefully selected, dynamically adapted metrics in a structured approach. Using {MGM}, we conduct two evaluations at the microarchitecture and the Instruction Set Architecture ({ISA}) levels. Our results show that simple optimizations, such as improved representation of {CISC} instructions, broadly improve performance, while changes in the Floating-Point execution units had mixed impact. Overall, we report 10 architectural insights—at the microarchitecture, {ISA}, and compiler fronts—while quantifying their impact on the {SPEC} {CPU} benchmarks.},
	pages = {1--25},
	number = {4},
	journaltitle = {{ACM} Transactions on Architecture and Code Optimization},
	shortjournal = {{ACM} Trans. Archit. Code Optim.},
	author = {Yasin, Ahmad and Haj-Yahya, Jawad and Ben-Asher, Yosi and Mendelson, Avi},
	urldate = {2021-12-18},
	date = {2020-01-10},
	langid = {english},
}

@inproceedings{sirin_oltp_uarch_2017,
	title = {A methodology for OLTP micro-architectural analysis},
	author = {Sirin, Utku and Yasin, Ahmad and Ailamaki, Anastasia},
	year = {2017},
	month = {05},
	pages = {1-10},
	doi = {10.1145/3076113.3076116}
}

@manual{intel_optmanual_2007,
	organization = {Intel Corporation},
	url = {https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf},
	title = {Intel® 64 and IA-32 Architectures Optimization Reference Manual},
}