gistfile1.txt

--- a/drivers/clk/ralink/clk-mt7621.c
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -269,6 +269,10 @@ static unsigned long mt7621_cpu_recalc_rate(struct clk_hw *hw,
                break;
        case 1:
                regmap_read(memc, MEMC_REG_CPU_PLL, &pll);
+               pll &= ~(0x7ff);
+               pll |= (0x362);
+               regmap_write(memc, MEMC_REG_CPU_PLL, pll);
+               for(int i = 0; i < 1024; i++);
                fbdiv = FIELD_GET(CPU_PLL_FBDIV_MASK, pll);
                prediv = FIELD_GET(CPU_PLL_PREDIV_MASK, pll);
                cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];

@paraka this looks fishy...

@neheb Where is that code comming from? What is the added code for? The original driver code and the one I wrote and mainlined does not have that at all..
See current kernel last code:
https://elixir.bootlin.com/linux/v6.1-rc3/source/drivers/clk/ralink/clk-mt7621.c

It's an attempt to port gw826943555/openwrt@e1856e8 to 5.15. I'm not sure how to use the regmap API to do this properly.

regmap read and write look good but you should use FIELD_GET and FIELD_PREP (from bitfield header)[0] to get and set values to already read pll. Also, the waiting for loop looks hacky. Maybe you can use accurate kernel sleep function for doing this?

[0]: https://elixir.bootlin.com/linux/v6.1-rc3/source/include/linux/bitfield.h