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@neuro-sys
Created November 11, 2019 21:02
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Clear vertical line counter of GA via bit 4 of Reg 2
org &8000
run &8000
nolist
jp start
vsync:
ld b, &f5
in a, (c)
rra
jr nc, vsync
ret
start:
di
; Put EI RET at &38
ld a, &fb
ld (&38), a
ld a, &c9
ld (&39), a
; Disable Lower and Upper ROM
ld bc, &7f00 or &80 or &08 or &04 or &1
out (c), c
ei
loop:
call vsync
halt
halt
halt
ld bc, &7f00 or &10
out (c), c
ld bc, &7f00 or &40 or &00
out (c), c
repeat 64*15
nop
rend
; Set bit 4 of Register 2 in GA
ld bc, &7f00 or &90 or &08 or &04 or &1
out (c), c
halt
ld bc, &7f00 or &10
out (c), c
ld bc, &7f00 or &40 or &04
out (c), c
jp loop
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