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nevercast/next log when clk12 not used Secret

Created June 23, 2020 06:13
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next log when clk12 not used
Info: constrained 'PIN_TX' to bel 'X4/Y33/io0'
Info: constrained 'PIN_RX' to bel 'X2/Y33/io1'
Warning: unmatched constraint 'PIN_3' (on line 43)
Warning: unmatched constraint 'PIN_4' (on line 44)
Warning: unmatched constraint 'PIN_5' (on line 45)
Warning: unmatched constraint 'PIN_6' (on line 46)
Warning: unmatched constraint 'PIN_7' (on line 47)
Warning: unmatched constraint 'PIN_8' (on line 48)
Warning: unmatched constraint 'PIN_9' (on line 49)
Warning: unmatched constraint 'PIN_10' (on line 50)
Warning: unmatched constraint 'PIN_11' (on line 51)
Warning: unmatched constraint 'PIN_12' (on line 52)
Warning: unmatched constraint 'PIN_13' (on line 53)
Warning: unmatched constraint 'PIN_14' (on line 56)
Warning: unmatched constraint 'PIN_15' (on line 57)
Warning: unmatched constraint 'PIN_16' (on line 58)
Warning: unmatched constraint 'PIN_17' (on line 59)
Warning: unmatched constraint 'PIN_18' (on line 60)
Warning: unmatched constraint 'PIN_19' (on line 61)
Warning: unmatched constraint 'PIN_20' (on line 62)
Warning: unmatched constraint 'PIN_21' (on line 63)
Warning: unmatched constraint 'PIN_22' (on line 64)
Warning: unmatched constraint 'PIN_23' (on line 65)
Warning: unmatched constraint 'PIN_24' (on line 66)
Info: constrained 'SPI_SS' to bel 'X31/Y0/io1'
Info: constrained 'SPI_SCK' to bel 'X31/Y0/io0'
Info: constrained 'SPI_IO0' to bel 'X30/Y0/io0'
Info: constrained 'SPI_IO1' to bel 'X30/Y0/io1'
Info: constrained 'SPI_IO2' to bel 'X17/Y0/io0'
Info: constrained 'SPI_IO3' to bel 'X33/Y1/io0'
Warning: unmatched constraint 'PIN_25' (on line 77)
Warning: unmatched constraint 'PIN_26' (on line 78)
Warning: unmatched constraint 'PIN_27' (on line 79)
Warning: unmatched constraint 'PIN_28' (on line 80)
Warning: unmatched constraint 'PIN_29' (on line 81)
Warning: unmatched constraint 'PIN_30' (on line 82)
Warning: unmatched constraint 'PIN_31' (on line 83)
Info: constrained 'LED' to bel 'X5/Y33/io1'
Info: constrained 'USBP' to bel 'X9/Y33/io0'
Info: constrained 'USBN' to bel 'X10/Y33/io1'
Info: constrained 'USBPU' to bel 'X6/Y33/io0'
Info: constrained 'CLK' to bel 'X0/Y30/io0'
Info: constraining clock net 'clk12' to 12.00 MHz
Info: constraining clock net 'clk48' to 48.00 MHz
Info: Packing constants..
Info: Packing IOs..
Info: SPI_IO0 feeds SB_IO flash_io_buf[0], removing $nextpnr_iobuf SPI_IO0.
Info: SPI_IO1 feeds SB_IO flash_io_buf[1], removing $nextpnr_iobuf SPI_IO1.
Info: SPI_IO2 feeds SB_IO flash_io_buf[2], removing $nextpnr_iobuf SPI_IO2.
Info: SPI_IO3 feeds SB_IO flash_io_buf[3], removing $nextpnr_iobuf SPI_IO3.
Info: USBN feeds SB_IO uart.iobuf_usbn, removing $nextpnr_obuf USBN.
Info: USBP feeds SB_IO uart.iobuf_usbp, removing $nextpnr_obuf USBP.
Info: Packing LUT-FFs..
Info: 529 LCs used as LUT4 only
Info: 193 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info: 239 LCs used as DFF only
Info: Packing carries..
Info: 50 LCs used as CARRY only
Info: Packing RAMs..
Info: Placing PLLs..
Info: constrained PLL 'pll48.uut' to X16/Y0/pll_3
Info: Packing special functions..
Info: PLL 'pll48.uut' has LOCK output, need to pass all outputs via LUT
Info: LUT strategy for LOCK: move all users to new LUT
Info: constrained 'pll48.uut_PLL$nextpnr_LOCK_lut_through' to X1/Y1/lc0
Info: Promoting globals..
Info: promoting clk48 (fanout 382)
Info: promoting reset [reset] (fanout 83)
Info: promoting clk12 (fanout 54)
Info: promoting uart.uart.usb_fs_pe_inst.usb_fs_rx_inst.pid_complete_SB_LUT4_I3_O[0] [reset] (fanout 21)
Info: promoting uart.uart.ctrl_ep_inst.new_dev_addr_SB_DFFE_Q_E[2] [reset] (fanout 20)
Info: promoting uart.uart.usb_fs_pe_inst.usb_fs_tx_inst.data_payload_SB_LUT4_I3_O [reset] (fanout 16)
Info: promoting uart.uart.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state_SB_DFFE_Q_31_D_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3_SB_LUT4_I0_O [cen] (fanout 32)
Info: promoting pll48.uut_PLL$nextnr_LOCK_lut_through_net [cen] (fanout 27)
Info: Constraining chains...
Info: 26 LCs used to legalise carry chains.
Info: Checksum: 0x5f2e7a2c
Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0x05cc3222
Info: Device utilisation:
Info: ICESTORM_LC: 1040/ 7680 13%
Info: ICESTORM_RAM: 2/ 32 6%
Info: SB_IO: 13/ 256 5%
Info: SB_GB: 8/ 8 100%
Info: ICESTORM_PLL: 1/ 2 50%
Info: SB_WARMBOOT: 0/ 1 0%
Info: Placed 15 cells based on constraints.
Info: Creating initial analytic placement for 899 cells, random placement wirelen = 30168.
Info: at initial placer iter 0, wirelen = 327
Info: at initial placer iter 1, wirelen = 340
Info: at initial placer iter 2, wirelen = 256
Info: at initial placer iter 3, wirelen = 243
Info: Running main analytical placer.
Info: at iteration #1, type ALL: wirelen solved = 253, spread = 3981, legal = 4639; time = 0.03s
Info: at iteration #2, type ALL: wirelen solved = 398, spread = 3103, legal = 3749; time = 0.08s
Info: at iteration #3, type ALL: wirelen solved = 551, spread = 3085, legal = 3700; time = 0.03s
Info: at iteration #4, type ALL: wirelen solved = 769, spread = 2885, legal = 4024; time = 0.19s
Info: at iteration #5, type ALL: wirelen solved = 1003, spread = 3055, legal = 3922; time = 0.03s
Info: at iteration #6, type ALL: wirelen solved = 1084, spread = 2992, legal = 3684; time = 0.03s
Info: at iteration #7, type ALL: wirelen solved = 1070, spread = 3042, legal = 3763; time = 0.03s
Info: at iteration #8, type ALL: wirelen solved = 1075, spread = 3072, legal = 4161; time = 0.03s
Info: at iteration #9, type ALL: wirelen solved = 1240, spread = 3075, legal = 3869; time = 0.03s
Info: at iteration #10, type ALL: wirelen solved = 1327, spread = 2888, legal = 3531; time = 0.03s
Info: at iteration #11, type ALL: wirelen solved = 1244, spread = 2955, legal = 3484; time = 0.03s
Info: at iteration #12, type ALL: wirelen solved = 1402, spread = 2774, legal = 3801; time = 0.61s
Info: at iteration #13, type ALL: wirelen solved = 1385, spread = 2902, legal = 3641; time = 0.03s
Info: at iteration #14, type ALL: wirelen solved = 1518, spread = 2963, legal = 3366; time = 1.14s
Info: at iteration #15, type ALL: wirelen solved = 1573, spread = 3004, legal = 3659; time = 0.03s
Info: at iteration #16, type ALL: wirelen solved = 1723, spread = 2754, legal = 4108; time = 0.50s
Info: at iteration #17, type ALL: wirelen solved = 1662, spread = 2858, legal = 4358; time = 0.03s
Info: at iteration #18, type ALL: wirelen solved = 1705, spread = 2958, legal = 4024; time = 0.39s
Info: at iteration #19, type ALL: wirelen solved = 1723, spread = 2987, legal = 3734; time = 0.02s
Info: HeAP Placer Time: 3.56s
Info: of which solving equations: 0.34s
Info: of which spreading cells: 0.08s
Info: of which strict legalisation: 2.93s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 137, wirelen = 3366
Info: at iteration #5: temp = 0.000000, timing cost = 115, wirelen = 2913
Info: at iteration #10: temp = 0.000000, timing cost = 116, wirelen = 2704
Info: at iteration #15: temp = 0.000000, timing cost = 155, wirelen = 2622
Info: at iteration #19: temp = 0.000000, timing cost = 145, wirelen = 2552
Info: SA placement time 0.67s
Info: Max frequency for clock 'clk48_$glb_clk': 48.93 MHz (PASS at 48.00 MHz)
Info: Max frequency for clock 'clk12_$glb_clk': 96.88 MHz (PASS at 12.00 MHz)
Info: Max delay <async> -> posedge clk48_$glb_clk: 2.65 ns
Info: Max delay posedge clk12_$glb_clk -> <async> : 8.96 ns
Info: Max delay posedge clk12_$glb_clk -> posedge clk48_$glb_clk: 10.76 ns
Info: Max delay posedge clk48_$glb_clk -> <async> : 3.79 ns
Info: Slack histogram:
Info: legend: * represents 6 endpoint(s)
Info: + represents [1,6) endpoint(s)
Info: [ 396, 4436) |*******+
Info: [ 4436, 8476) |******************************************+
Info: [ 8476, 12516) |*************************************************+
Info: [ 12516, 16556) |*********************************************************+
Info: [ 16556, 20596) |************************************************************
Info: [ 20596, 24636) |
Info: [ 24636, 28676) |
Info: [ 28676, 32716) |
Info: [ 32716, 36756) |
Info: [ 36756, 40796) |
Info: [ 40796, 44836) |
Info: [ 44836, 48876) |
Info: [ 48876, 52916) |
Info: [ 52916, 56956) |
Info: [ 56956, 60996) |
Info: [ 60996, 65036) |
Info: [ 65036, 69076) |
Info: [ 69076, 73116) |+
Info: [ 73116, 77156) |****+
Info: [ 77156, 81196) |*****************+
Info: Checksum: 0x027230ab
Info: Running timing-driven placement optimisation...
Info: Iteration 0...
Info: Iteration 1...
Info: Iteration 2...
Info: Iteration 3...
Info: Iteration 4...
Info: Iteration 5...
Info: Iteration 6...
Info: Iteration 7...
Info: Iteration 8...
Info: Iteration 9...
Info: Iteration 10...
Info: Iteration 11...
Info: Iteration 12...
Info: Iteration 13...
Info: Iteration 14...
Info: Iteration 15...
Info: Iteration 16...
Info: Iteration 17...
Info: Iteration 18...
Info: Iteration 19...
Info: Iteration 20...
Info: Iteration 21...
Info: Iteration 22...
Info: Iteration 23...
Info: Iteration 24...
Info: Iteration 25...
Info: Iteration 26...
Info: Iteration 27...
Info: Iteration 28...
Info: Iteration 29...
Info: Routing..
Info: Setting up routing queue.
Info: Routing 3074 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 45 954 | 45 954 | 2124| 0.15 0.15|
Info: 2000 | 166 1833 | 121 879 | 1267| 0.16 0.31|
Info: 3000 | 342 2657 | 176 824 | 501| 0.29 0.59|
Info: 3588 | 419 3169 | 77 512 | 0| 0.31 0.90|
Info: Routing complete.
Info: Router1 time 0.90s
Info: Checksum: 0x123d2090
Info: Critical path report for clock 'clk48_$glb_clk' (posedge -> posedge):
Info: curr total
Info: 0.8 0.8 Source uart.uart.ctrl_ep_inst.bytes_sent_SB_DFFESR_Q_7_DFFLC.O
Info: 0.9 1.7 Net uart.uart.ctrl_ep_inst.bytes_sent[0] budget 0.769000 ns (3,5) -> (3,5)
Info: Sink uart.uart.ctrl_ep_inst.bytes_sent_SB_DFFESR_Q_7_D_SB_LUT4_O_6_LC.I3
Info: 0.5 2.1 Source uart.uart.ctrl_ep_inst.bytes_sent_SB_DFFESR_Q_7_D_SB_LUT4_O_6_LC.O
Info: 0.9 3.0 Net uart.uart.ctrl_ep_inst.bytes_sent_SB_DFFESR_Q_7_D[0] budget 0.783000 ns (3,5) -> (3,6)
Info: Sink uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_6$CARRY.I2
Info: 0.3 3.3 Source uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_6$CARRY.COUT
Info: 0.0 3.3 Net uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_CO[1] budget 0.000000 ns (3,6) -> (3,6)
Info: Sink uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_5$CARRY.CIN
Info: 0.2 3.5 Source uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_5$CARRY.COUT
Info: 0.0 3.5 Net uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_CO[2] budget 0.000000 ns (3,6) -> (3,6)
Info: Sink uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_4$CARRY.CIN
Info: 0.2 3.7 Source uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_4$CARRY.COUT
Info: 0.0 3.7 Net uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_CO[3] budget 0.000000 ns (3,6) -> (3,6)
Info: Sink uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_3$CARRY.CIN
Info: 0.2 3.9 Source uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_3$CARRY.COUT
Info: 0.0 3.9 Net uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_CO[4] budget 0.000000 ns (3,6) -> (3,6)
Info: Sink uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_2$CARRY.CIN
Info: 0.2 4.1 Source uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_2$CARRY.COUT
Info: 0.0 4.1 Net uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_CO[5] budget 0.000000 ns (3,6) -> (3,6)
Info: Sink uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_1$CARRY.CIN
Info: 0.2 4.3 Source uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_1$CARRY.COUT
Info: 0.0 4.3 Net uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_CO[6] budget 0.000000 ns (3,6) -> (3,6)
Info: Sink uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0$CARRY.CIN
Info: 0.2 4.5 Source uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0$CARRY.COUT
Info: 0.0 4.5 Net uart.uart.ctrl_ep_inst.rom_length_SB_CARRY_I0_CO[7] budget 0.000000 ns (3,6) -> (3,6)
Info: Sink uart.uart.ctrl_ep_inst.rom_length_SB_LUT4_I2_I3_SB_CARRY_CO$CARRY.CIN
Info: 0.2 4.6 Source uart.uart.ctrl_ep_inst.rom_length_SB_LUT4_I2_I3_SB_CARRY_CO$CARRY.COUT
Info: 0.7 5.3 Net uart.uart.ctrl_ep_inst.rom_length_SB_LUT4_I2_I0[3] budget 0.670000 ns (3,6) -> (3,7)
Info: Sink uart.uart.ctrl_ep_inst.rom_length_SB_LUT4_I2_LC.I3
Info: 0.5 5.8 Source uart.uart.ctrl_ep_inst.rom_length_SB_LUT4_I2_LC.O
Info: 1.9 7.7 Net uart.uart.ctrl_ep_inst.in_ep_stall_SB_LUT4_I3_I2[2] budget 1.006000 ns (3,7) -> (3,10)
Info: Sink uart.uart.usb_uart_bridge_ep_inst.in_ep_req_reg_SB_LUT4_I2_I1_SB_LUT4_O_LC.I2
Info: 0.6 8.2 Source uart.uart.usb_uart_bridge_ep_inst.in_ep_req_reg_SB_LUT4_I2_I1_SB_LUT4_O_LC.O
Info: 2.4 10.6 Net uart.uart.usb_uart_bridge_ep_inst.in_ep_req_reg_SB_LUT4_I2_I1[0] budget 1.006000 ns (3,10) -> (6,5)
Info: Sink uart.uart.usb_uart_bridge_ep_inst.in_ep_req_reg_SB_LUT4_I3_I1_SB_LUT4_O_LC.I1
Info: 0.6 11.2 Source uart.uart.usb_uart_bridge_ep_inst.in_ep_req_reg_SB_LUT4_I3_I1_SB_LUT4_O_LC.O
Info: 2.4 13.7 Net uart.uart.usb_uart_bridge_ep_inst.in_ep_req_reg_SB_LUT4_I3_I0[1] budget 1.319000 ns (6,5) -> (9,6)
Info: Sink uart.uart.usb_uart_bridge_ep_inst.in_ep_req_reg_SB_LUT4_I2_LC.I3
Info: 0.5 14.1 Source uart.uart.usb_uart_bridge_ep_inst.in_ep_req_reg_SB_LUT4_I2_LC.O
Info: 0.9 15.0 Net uart.uart.usb_uart_bridge_ep_inst.in_ep_req_reg_SB_LUT4_I2_O[2] budget 1.154000 ns (9,6) -> (9,6)
Info: Sink uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.in_ep_data_SB_LUT4_O_6_LC.I2
Info: 0.6 15.5 Source uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.in_ep_data_SB_LUT4_O_6_LC.O
Info: 2.2 17.7 Net uart.uart.usb_fs_pe_inst.arb_in_ep_data[2] budget 1.154000 ns (9,6) -> (8,7)
Info: Sink uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.in_data_buffer.0.0.0_RAM.WDATA_4
Info: 0.1 17.8 Setup uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.in_data_buffer.0.0.0_RAM.WDATA_4
Info: 5.6 ns logic, 12.2 ns routing
Info: Critical path report for clock 'clk12_$glb_clk' (posedge -> posedge):
Info: curr total
Info: 0.8 0.8 Source resetn_SB_LUT4_I2_LC.O
Info: 3.8 4.6 Net BOOT_LED_SB_DFFESS_Q_E_SB_LUT4_O_I2[1] budget 3.421000 ns (2,6) -> (16,1)
Info: Sink uart.uart.usb_fs_pe_inst.usb_fs_rx_inst.reset_SB_LUT4_O_LC.I3
Info: 0.5 5.1 Source uart.uart.usb_fs_pe_inst.usb_fs_rx_inst.reset_SB_LUT4_O_LC.O
Info: 3.3 8.4 Net reset budget 37.285999 ns (16,1) -> (2,3)
Info: Sink reset_cnt_SB_CARRY_I1_23$CARRY.I1
Info: 0.4 8.7 Source reset_cnt_SB_CARRY_I1_23$CARRY.COUT
Info: 0.0 8.7 Net reset_cnt_SB_CARRY_I1_CO[1] budget 0.000000 ns (2,3) -> (2,3)
Info: Sink reset_cnt_SB_LUT4_I2_12_LC.CIN
Info: 0.2 8.9 Source reset_cnt_SB_LUT4_I2_12_LC.COUT
Info: 0.0 8.9 Net reset_cnt_SB_CARRY_I1_CO[2] budget 0.000000 ns (2,3) -> (2,3)
Info: Sink reset_cnt_SB_LUT4_I2_7_LC.CIN
Info: 0.2 9.1 Source reset_cnt_SB_LUT4_I2_7_LC.COUT
Info: 0.0 9.1 Net reset_cnt_SB_CARRY_I1_CO[3] budget 0.000000 ns (2,3) -> (2,3)
Info: Sink reset_cnt_SB_LUT4_I2_6_LC.CIN
Info: 0.2 9.3 Source reset_cnt_SB_LUT4_I2_6_LC.COUT
Info: 0.0 9.3 Net reset_cnt_SB_CARRY_I1_CO[4] budget 0.000000 ns (2,3) -> (2,3)
Info: Sink reset_cnt_SB_LUT4_I2_5_LC.CIN
Info: 0.2 9.5 Source reset_cnt_SB_LUT4_I2_5_LC.COUT
Info: 0.0 9.5 Net reset_cnt_SB_CARRY_I1_CO[5] budget 0.000000 ns (2,3) -> (2,3)
Info: Sink reset_cnt_SB_LUT4_I2_4_LC.CIN
Info: 0.2 9.7 Source reset_cnt_SB_LUT4_I2_4_LC.COUT
Info: 0.0 9.7 Net reset_cnt_SB_CARRY_I1_CO[6] budget 0.000000 ns (2,3) -> (2,3)
Info: Sink reset_cnt_SB_LUT4_I2_3_LC.CIN
Info: 0.2 9.9 Source reset_cnt_SB_LUT4_I2_3_LC.COUT
Info: 0.0 9.9 Net reset_cnt_SB_CARRY_I1_CO[7] budget 0.000000 ns (2,3) -> (2,3)
Info: Sink reset_cnt_SB_LUT4_I2_2_LC.CIN
Info: 0.2 10.0 Source reset_cnt_SB_LUT4_I2_2_LC.COUT
Info: 0.3 10.3 Net reset_cnt_SB_CARRY_I1_CO[8] budget 0.290000 ns (2,3) -> (2,4)
Info: Sink reset_cnt_SB_LUT4_I2_1_LC.CIN
Info: 0.2 10.5 Source reset_cnt_SB_LUT4_I2_1_LC.COUT
Info: 0.0 10.5 Net reset_cnt_SB_CARRY_I1_CO[9] budget 0.000000 ns (2,4) -> (2,4)
Info: Sink reset_cnt_SB_LUT4_I2_LC.CIN
Info: 0.2 10.7 Source reset_cnt_SB_LUT4_I2_LC.COUT
Info: 0.0 10.7 Net reset_cnt_SB_CARRY_I1_CO[10] budget 0.000000 ns (2,4) -> (2,4)
Info: Sink reset_cnt_SB_LUT4_I2_22_LC.CIN
Info: 0.2 10.9 Source reset_cnt_SB_LUT4_I2_22_LC.COUT
Info: 0.0 10.9 Net reset_cnt_SB_CARRY_I1_CO[11] budget 0.000000 ns (2,4) -> (2,4)
Info: Sink reset_cnt_SB_LUT4_I2_21_LC.CIN
Info: 0.2 11.1 Source reset_cnt_SB_LUT4_I2_21_LC.COUT
Info: 0.0 11.1 Net reset_cnt_SB_CARRY_I1_CO[12] budget 0.000000 ns (2,4) -> (2,4)
Info: Sink reset_cnt_SB_LUT4_I2_20_LC.CIN
Info: 0.2 11.3 Source reset_cnt_SB_LUT4_I2_20_LC.COUT
Info: 0.0 11.3 Net reset_cnt_SB_CARRY_I1_CO[13] budget 0.000000 ns (2,4) -> (2,4)
Info: Sink reset_cnt_SB_LUT4_I2_19_LC.CIN
Info: 0.2 11.4 Source reset_cnt_SB_LUT4_I2_19_LC.COUT
Info: 0.0 11.4 Net reset_cnt_SB_CARRY_I1_CO[14] budget 0.000000 ns (2,4) -> (2,4)
Info: Sink reset_cnt_SB_LUT4_I2_18_LC.CIN
Info: 0.2 11.6 Source reset_cnt_SB_LUT4_I2_18_LC.COUT
Info: 0.0 11.6 Net reset_cnt_SB_CARRY_I1_CO[15] budget 0.000000 ns (2,4) -> (2,4)
Info: Sink reset_cnt_SB_LUT4_I2_17_LC.CIN
Info: 0.2 11.8 Source reset_cnt_SB_LUT4_I2_17_LC.COUT
Info: 0.3 12.1 Net reset_cnt_SB_CARRY_I1_CO[16] budget 0.290000 ns (2,4) -> (2,5)
Info: Sink reset_cnt_SB_LUT4_I2_16_LC.CIN
Info: 0.2 12.3 Source reset_cnt_SB_LUT4_I2_16_LC.COUT
Info: 0.0 12.3 Net reset_cnt_SB_CARRY_I1_CO[17] budget 0.000000 ns (2,5) -> (2,5)
Info: Sink reset_cnt_SB_LUT4_I2_15_LC.CIN
Info: 0.2 12.5 Source reset_cnt_SB_LUT4_I2_15_LC.COUT
Info: 0.0 12.5 Net reset_cnt_SB_CARRY_I1_CO[18] budget 0.000000 ns (2,5) -> (2,5)
Info: Sink reset_cnt_SB_LUT4_I2_14_LC.CIN
Info: 0.2 12.7 Source reset_cnt_SB_LUT4_I2_14_LC.COUT
Info: 0.0 12.7 Net reset_cnt_SB_CARRY_I1_CO[19] budget 0.000000 ns (2,5) -> (2,5)
Info: Sink reset_cnt_SB_LUT4_I2_13_LC.CIN
Info: 0.2 12.8 Source reset_cnt_SB_LUT4_I2_13_LC.COUT
Info: 0.0 12.8 Net reset_cnt_SB_CARRY_I1_CO[20] budget 0.000000 ns (2,5) -> (2,5)
Info: Sink reset_cnt_SB_LUT4_I2_11_LC.CIN
Info: 0.2 13.0 Source reset_cnt_SB_LUT4_I2_11_LC.COUT
Info: 0.0 13.0 Net reset_cnt_SB_CARRY_I1_CO[21] budget 0.000000 ns (2,5) -> (2,5)
Info: Sink reset_cnt_SB_LUT4_I2_10_LC.CIN
Info: 0.2 13.2 Source reset_cnt_SB_LUT4_I2_10_LC.COUT
Info: 0.0 13.2 Net reset_cnt_SB_CARRY_I1_CO[22] budget 0.000000 ns (2,5) -> (2,5)
Info: Sink reset_cnt_SB_LUT4_I2_9_LC.CIN
Info: 0.2 13.4 Source reset_cnt_SB_LUT4_I2_9_LC.COUT
Info: 0.0 13.4 Net reset_cnt_SB_CARRY_I1_CO[23] budget 0.000000 ns (2,5) -> (2,5)
Info: Sink reset_cnt_SB_LUT4_I2_8_LC.CIN
Info: 0.2 13.6 Source reset_cnt_SB_LUT4_I2_8_LC.COUT
Info: 0.7 14.3 Net reset_cnt_SB_CARRY_I1_CO[24] budget 0.670000 ns (2,5) -> (2,6)
Info: Sink resetn_SB_LUT4_I2_LC.I3
Info: 0.5 14.8 Setup resetn_SB_LUT4_I2_LC.I3
Info: 6.4 ns logic, 8.3 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge clk48_$glb_clk':
Info: curr total
Info: 0.0 0.0 Source uart.iobuf_usbp.D_IN_0
Info: 1.9 1.9 Net uart.usb_p_in budget 20.142000 ns (9,33) -> (9,29)
Info: Sink uart.uart.usb_fs_pe_inst.usb_fs_rx_inst.dpair_q_SB_DFFSS_Q_DFFLC.I0
Info: 0.7 2.6 Setup uart.uart.usb_fs_pe_inst.usb_fs_rx_inst.dpair_q_SB_DFFSS_Q_DFFLC.I0
Info: 0.7 ns logic, 1.9 ns routing
Info: Critical path report for cross-domain path 'posedge clk12_$glb_clk' -> '<async>':
Info: curr total
Info: 0.8 0.8 Source PULSE_LED_SB_LUT4_I2_LC.O
Info: 1.9 2.7 Net PULSE_LED budget 25.667000 ns (1,5) -> (3,4)
Info: Sink USER_LED_SB_LUT4_I2_LC.I1
Info: 0.6 3.3 Source USER_LED_SB_LUT4_I2_LC.O
Info: 0.9 4.1 Net LED_SB_LUT4_O_I2[1] budget 25.542000 ns (3,4) -> (3,4)
Info: Sink LED_SB_LUT4_O_LC.I2
Info: 0.6 4.7 Source LED_SB_LUT4_O_LC.O
Info: 4.7 9.4 Net LED$SB_IO_OUT budget 27.129999 ns (3,4) -> (5,33)
Info: Sink LED$sb_io.D_OUT_0
Info: 1.9 ns logic, 7.4 ns routing
Info: Critical path report for cross-domain path 'posedge clk12_$glb_clk' -> 'posedge clk48_$glb_clk':
Info: curr total
Info: 0.8 0.8 Source resetn_SB_LUT4_I2_LC.O
Info: 2.9 3.7 Net BOOT_LED_SB_DFFESS_Q_E_SB_LUT4_O_I2[1] budget 4.605000 ns (2,6) -> (9,12)
Info: Sink uart.uart.usb_fs_pe_inst.usb_fs_tx_inst.tx_data_get_SB_LUT4_I0_I2_SB_LUT4_O_LC.I3
Info: 0.5 4.2 Source uart.uart.usb_fs_pe_inst.usb_fs_tx_inst.tx_data_get_SB_LUT4_I0_I2_SB_LUT4_O_LC.O
Info: 0.9 5.0 Net uart.uart.usb_fs_pe_inst.usb_fs_tx_inst.tx_data_get_SB_LUT4_I0_I2[3] budget 2.159000 ns (9,12) -> (9,12)
Info: Sink uart.uart.usb_fs_pe_inst.usb_fs_tx_inst.tx_data_get_SB_LUT4_I0_LC.I3
Info: 0.5 5.5 Source uart.uart.usb_fs_pe_inst.usb_fs_tx_inst.tx_data_get_SB_LUT4_I0_LC.O
Info: 0.9 6.3 Net uart.uart.usb_fs_pe_inst.usb_fs_tx_inst.tx_data_get_SB_LUT4_I0_O[2] budget 1.484000 ns (9,12) -> (9,12)
Info: Sink uart.uart.usb_fs_pe_inst.usb_fs_tx_inst.tx_data_get_SB_LUT4_I0_O_SB_LUT4_I1_LC.I1
Info: 0.6 6.9 Source uart.uart.usb_fs_pe_inst.usb_fs_tx_inst.tx_data_get_SB_LUT4_I0_O_SB_LUT4_I1_LC.O
Info: 2.9 9.9 Net uart.uart.usb_fs_pe_inst.usb_fs_tx_inst.tx_data_get_SB_LUT4_I0_O_SB_LUT4_I1_O budget 1.676000 ns (9,12) -> (10,11)
Info: Sink uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.ep_get_addr[1]_SB_DFFESR_Q_DFFLC.CEN
Info: 0.1 10.0 Setup uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.ep_get_addr[1]_SB_DFFESR_Q_DFFLC.CEN
Info: 2.4 ns logic, 7.6 ns routing
Info: Critical path report for cross-domain path 'posedge clk48_$glb_clk' -> '<async>':
Info: curr total
Info: 0.8 0.8 Source uart.uart.usb_fs_pe_inst.usb_fs_tx_inst.dn_SB_LUT4_I3_LC.O
Info: 3.5 4.3 Net uart.usb_n_tx budget 82.538002 ns (11,19) -> (10,33)
Info: Sink uart.iobuf_usbn.D_OUT_0
Info: 0.8 ns logic, 3.5 ns routing
Info: Max frequency for clock 'clk48_$glb_clk': 56.05 MHz (PASS at 48.00 MHz)
Info: Max frequency for clock 'clk12_$glb_clk': 67.76 MHz (PASS at 12.00 MHz)
Info: Max delay <async> -> posedge clk48_$glb_clk: 2.58 ns
Info: Max delay posedge clk12_$glb_clk -> <async> : 9.39 ns
Info: Max delay posedge clk12_$glb_clk -> posedge clk48_$glb_clk: 9.97 ns
Info: Max delay posedge clk48_$glb_clk -> <async> : 4.32 ns
Info: Slack histogram:
Info: legend: * represents 7 endpoint(s)
Info: + represents [1,7) endpoint(s)
Info: [ 2993, 6903) |**************************+
Info: [ 6903, 10813) |*****************************************+
Info: [ 10813, 14723) |**************************************************+
Info: [ 14723, 18633) |************************************************************
Info: [ 18633, 22543) |******+
Info: [ 22543, 26453) |
Info: [ 26453, 30363) |
Info: [ 30363, 34273) |
Info: [ 34273, 38183) |
Info: [ 38183, 42093) |
Info: [ 42093, 46003) |
Info: [ 46003, 49913) |
Info: [ 49913, 53823) |
Info: [ 53823, 57733) |
Info: [ 57733, 61643) |
Info: [ 61643, 65553) |
Info: [ 65553, 69463) |+
Info: [ 69463, 73373) |**+
Info: [ 73373, 77283) |**+
Info: [ 77283, 81193) |*************+
29 warnings, 0 errors
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