Testing nMigen

gistfile1.txt

jneve@Ares MINGW64 /d/Projects/FPGA/TinyFPGA BX/nMigenExperiments
$ python -m nmigen_boards.tinyfpga_bx
Traceback (most recent call last):
  File "C:\Python37\lib\runpy.py", line 193, in _run_module_as_main
    "__main__", mod_spec)
  File "C:\Python37\lib\runpy.py", line 85, in _run_code
    exec(code, run_globals)
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\nmigen_boards\tinyfpga_bx.py", line 56, in <module>
    TinyFPGABXPlatform().build(Blinky(), do_program=True)
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\nmigen\build\plat.py", line 90, in build
    plan = self.prepare(elaboratable, name, **kwargs)
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\nmigen\build\plat.py", line 163, in prepare
    return self.toolchain_prepare(fragment, name, **kwargs)
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\nmigen\build\plat.py", line 437, in toolchain_prepare
    render(content_tpl, origin=content_tpl))
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\nmigen\build\plat.py", line 431, in render
    "autogenerated": autogenerated,
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\jinja2\environment.py", line 1090, in render
    self.environment.handle_exception()
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\jinja2\environment.py", line 832, in handle_exception
    reraise(*rewrite_traceback_stack(source=source))
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\jinja2\_compat.py", line 28, in reraise
    raise value.with_traceback(tb)
  File "<template>", line 2, in top-level template code
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\nmigen\build\plat.py", line 315, in emit_debug_verilog
    strip_internal_attrs=False, write_verilog_opts=opts)
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\nmigen\back\verilog.py", line 10, in _convert_rtlil_text
    yosys = find_yosys(lambda ver: ver >= (0, 9))
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\nmigen\_toolchain\yosys.py", line 220, in find_yosys
    version = proxy.version()
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\nmigen\_toolchain\yosys.py", line 157, in version
    version = cls.run(["-V"])
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\nmigen\_toolchain\yosys.py", line 186, in run
    return cls._process_result(popen.returncode, stdout, stderr, ignore_warnings, src_loc_at)
  File "D:\Projects\FPGA\TinyFPGA BX\nMigenExperiments\.venv\lib\site-packages\nmigen\_toolchain\yosys.py", line 108, in _process_result
    raise YosysError(stderr.strip())
nmigen._toolchain.yosys.YosysError