Modeling inertial delays

assign_test.sv

`timescale 1ns/1ps

module test_assign_test;

   logic enable;
   logic amp_up_orig;
   logic block_up;
   logic block_up_prev;

   timeunit 1ns;
   timeprecision 1ps;
   localparam time TURNON_TIME = 1ns;
   localparam time TURNOFF_TIME = 200ps;

   initial begin
      enable = 0;

      #800ps;
      enable = 1;

      #200ps;
      enable = 0;

      #1000ps;
      enable = 1;
      #5000ps;
      enable = 0;

      #3000ps;
      enable = 1;
      #200ps;
      enable = 0;
      #600ps;
      enable = 1;
      #6000ps;
      enable = 0;

      #4000ps;
      enable = 1;
      #200ps;
      enable = 0;
      #100ps;
      enable = 1;
      #50ps;
      enable = 0;
      #100ps;
      enable = 1;

      #3000ps;
      enable = 0;
      #3000ps;
      enable = 1;
      #200ps;
      enable = 1'bx;
      #600ps;
      enable = 1;
      #3000ps;
      enable = 0;
      #3000ps;
   end // initial begin


   always @(enable) begin
      fork
         begin
            // Fork a new process whenever enable changes so we can handle
            // multiple glitches on enable.
            if (enable)
              #TURNON_TIME block_up = enable;
            else
              #TURNOFF_TIME block_up = enable;
         end
         // This process will make sure we escape the join_any if any transition
         // on enable occurs.
         @(enable);
      join_any

      // Make sure we kill any processes active above enable case we got here
      // because of a transition on enable.
      disable fork;
   end // always @ (enable)


   always @* begin
      if (enable) begin
         #TURNON_TIME block_up_prev = enable;
      end else begin
         #TURNOFF_TIME block_up_prev = enable;
      end
   end


   initial begin
      forever begin
         if (enable) begin
            @(negedge enable);
            #TURNOFF_TIME;
            amp_up_orig = 0;
         end else begin
            @(posedge enable);
            fork
               begin
                  #TURNON_TIME;
                  amp_up_orig = enable;
               end

               begin
                  @(negedge enable);
               end
            join_any
            //disable fork;
         end // else: !if(enable)
      end // forever begin
   end // initial begin
endmodule // test_assign_test