Bridges two Xilinx PicoBlaze microcontrollers via their I/O ports using a pair of 16x8 FIFOs

README

This turned out not to be as useful as just using the raw FIFO interface directly and letting each PicoBlaze do its own I/O logic.

fifo16x8.xco

##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Fri Oct 28 20:41:46 2011
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:fifo_generator:8.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.2
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=fifo16x8
CSET data_count=false
CSET data_count_width=4
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_handshake_flag_options_axis=false
CSET enable_handshake_flag_options_rach=false
CSET enable_handshake_flag_options_rdch=false
CSET enable_handshake_flag_options_wach=false
CSET enable_handshake_flag_options_wdch=false
CSET enable_handshake_flag_options_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=15
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=14
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=8
CSET input_depth=16
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=8
CSET output_depth=16
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=Empty
CSET programmable_empty_type_rach=Empty
CSET programmable_empty_type_rdch=Empty
CSET programmable_empty_type_wach=Empty
CSET programmable_empty_type_wdch=Empty
CSET programmable_empty_type_wrch=Empty
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=Full
CSET programmable_full_type_rach=Full
CSET programmable_full_type_rdch=Full
CSET programmable_full_type_wach=Full
CSET programmable_full_type_wdch=Full
CSET programmable_full_type_wrch=Full
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=4
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=false
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=false
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=4
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-14T07:12:32.000Z
# END Extra information
GENERATE
# CRC: ac326753

pB_bridge.v

/*
Copyright 2011, The Regents of the University of California.
All rights reserved.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:

   1. Redistributions of source code must retain the above copyright notice,
      this list of conditions and the following disclaimer.

   2. Redistributions in binary form must reproduce the above copyright notice,
      this list of conditions and the following disclaimer in the documentation
      and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.

The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/

`timescale 1 ns / 1 ps
`default_nettype none

/*
 * Connects two PicoBlaze microcontrollers via a pair of FIFOs.
 * Supports separate clock domains.
 *
 * ADDR[0]=0:
 *   READ:
 *     io_data_in[1]=TX FIFO FULL
 *     io_data_in[0]=RX FIFO EMPTY 
 * ADDR[0]=1:
 *   READ:
 *     io_data_in=RX FIFO DATA
 *   WRITE:
 *     io_data_in=TX FIFO DATA 
 */
module pB_bridge (
    /*
     * pB0
     */
    input wire pB0_io_en,
    input wire [7:0] pB0_io_addr, // not all signals used
    input wire [7:0] pB0_io_data_out,
    output reg [7:0] pB0_io_data_in,
    input wire pB0_io_rd,
    input wire pB0_io_wr,
    input wire pB0_clk,
    /*
     * pB1
     */
    input wire pB1_io_en,
    input wire [7:0] pB1_io_addr, // not all signals used
    input wire [7:0] pB1_io_data_out,
    output reg [7:0] pB1_io_data_in,
    input wire pB1_io_rd,
    input wire pB1_io_wr,
    input wire pB1_clk
);

////////////////////////////////////////////////////////////////////////////
// PARAMETERS AND CONSTANTS
////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////
// REGISTERS
////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////
// WIRES
////////////////////////////////////////////////////////////////////////////

wire [7:0] fifo0_din;
wire [7:0] fifo0_dout;
wire fifo0_wr_en;
wire fifo0_rd_en;
wire fifo0_empty;
wire fifo0_full;
wire fifo0_rd_clk;
wire fifo0_wr_clk;

wire [7:0] fifo1_din;
wire [7:0] fifo1_dout;
wire fifo1_wr_en;
wire fifo1_rd_en;
wire fifo1_empty;
wire fifo1_full;
wire fifo1_rd_clk;
wire fifo1_wr_clk;

////////////////////////////////////////////////////////////////////////////
// WIRE REGS (wires that are assigned inside of an always block)
////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////
// COMPONENT INSTANTIATIONS
////////////////////////////////////////////////////////////////////////////

fifo16x8 fifo0_inst (
  .wr_clk(fifo0_wr_clk), // input wr_clk
  .rd_clk(fifo0_rd_clk), // input rd_clk
  .din(fifo0_din), // input [7 : 0] din
  .wr_en(fifo0_wr_en), // input wr_en
  .rd_en(fifo0_rd_en), // input rd_en
  .dout(fifo0_dout), // output [7 : 0] dout
  .full(fifo0_full), // output full
  .empty(fifo0_empty) // output empty
);

fifo16x8 fifo1_inst (
  .wr_clk(fifo1_wr_clk), // input wr_clk
  .rd_clk(fifo1_rd_clk), // input rd_clk
  .din(fifo1_din), // input [7 : 0] din
  .wr_en(fifo1_wr_en), // input wr_en
  .rd_en(fifo1_rd_en), // input rd_en
  .dout(fifo1_dout), // output [7 : 0] dout
  .full(fifo1_full), // output full
  .empty(fifo1_empty) // output empty
);

////////////////////////////////////////////////////////////////////////////
// COMBINATIONAL ASSIGN STATEMENTS
////////////////////////////////////////////////////////////////////////////

assign fifo0_wr_clk = pB0_clk;
assign fifo1_wr_clk = pB1_clk;
assign fifo0_rd_clk = pB1_clk;
assign fifo1_rd_clk = pB0_clk;
assign fifo0_din = pB0_io_data_out;
assign fifo1_din = pB1_io_data_out;
assign fifo0_wr_en = (pB0_io_en & pB0_io_addr[0] & pB0_io_wr);
assign fifo1_wr_en = (pB1_io_en & pB1_io_addr[0] & pB1_io_wr);
assign fifo0_rd_en = (pB0_io_en & pB0_io_addr[0] & pB0_io_rd);
assign fifo1_rd_en = (pB1_io_en & pB1_io_addr[0] & pB1_io_rd);

////////////////////////////////////////////////////////////////////////////
// COMBINATIONAL ALWAYS STATEMENTS (always @* begin ... end)
////////////////////////////////////////////////////////////////////////////

always @* begin
    case (pB0_io_addr[0])
        1'b0: pB0_io_data_in = {6'd0, fifo0_full, fifo1_empty};
        1'b1: pB0_io_data_in = fifo1_dout;
        default: pB0_io_data_in = {6'd0, fifo0_full, fifo1_empty};
    endcase
end

always @* begin
    case (pB1_io_addr[0])
        1'b0: pB1_io_data_in = {6'd0, fifo1_full, fifo0_empty};
        1'b1: pB1_io_data_in = fifo0_dout;
        default: pB1_io_data_in = {6'd0, fifo1_full, fifo0_empty};
    endcase
end

////////////////////////////////////////////////////////////////////////////
// SEQUENTIAL ALWAYS STATEMENTS (always @(posedge clk) begin ... end)
////////////////////////////////////////////////////////////////////////////

endmodule