Subtraction prog

gistfile1.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Switches_LEDs is
    Port ( switches : in  STD_LOGIC_VECTOR(7 downto 0);
  		  LEDs     : out STD_LOGIC_VECTOR(7 downto 0));       
end Switches_LEDs;

architecture Behavioral of Switches_LEDs is
   signal A      : STD_LOGIC_VECTOR(3 downto 0);
	signal B      : STD_LOGIC_VECTOR(3 downto 0);
	signal borrow : STD_LOGIC_VECTOR(3 downto 0);
	signal result : STD_LOGIC_VECTOR(3 downto 0);
begin
	LEDs <= "0000" & result;
	A <= switches(3 downto 0);
	B <= switches(7 downto 4);
	
	result(0) <= A(0) XOR B(0);
	borrow(0) <= NOT A(0) AND B(0);
	
	result(1) <= A(1) XOR B(1) XOR borrow(0);
	borrow(1) <= (NOT A(1) AND B(1)) OR (NOT A(1) AND borrow(0)) OR (borrow(0) AND B(1));
	
	result(2) <= A(2) XOR B(2) XOR borrow(1);
	borrow(2) <= (NOT A(2) AND B(2)) OR (NOT A(2) AND borrow(1)) OR (borrow(1) AND B(2));
	
	result(3) <= A(3) XOR B(3) XOR borrow(2);
	borrow(3) <= (NOT A(3) AND B(3)) OR (NOT A(3) AND borrow(2)) OR (borrow(2) AND B(3));
	
	--result(4) <= borrow(3);
end Behavioral;