gistfile1.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Switches_LEDs is
    Port ( switches : in  STD_LOGIC_VECTOR(0 downto 0);
  		  LEDs     : out STD_LOGIC_VECTOR(7 downto 0);
			  clock    : in STD_LOGIC
			 );
end Switches_LEDs;

architecture Behavioral of Switches_LEDs is
   signal counter : STD_LOGIC_VECTOR(36 downto 0) := (others => '0');
begin
	LEDs <= counter(36 downto 29);
count: process (clock)
	begin
		if rising_edge(clock) then
			if (switches(0) = '0') then
				counter <= counter+1;
			else
				counter <= counter-1;
			end if;
		end if;
	end process;
end Behavioral;