Learning Chisel: n-bit full addr

AddrLED.scala

import chisel3._
import chisel3.util._

class HalfAddr extends Module {
  val io = IO(new Bundle {
    val inA = Input(UInt(1.W))
    val inB = Input(UInt(1.W))

    val outSum = Output(UInt(1.W))
    val outCarry = Output(UInt(1.W))
  })

  io.outSum := io.inA ^ io.inB
  io.outCarry := io.inA & io.inB
}

object HalfAddr {
  def apply(a: UInt, b: UInt): (UInt, UInt) = {
    val m = Module(new HalfAddr)
    m.io.inA := a
    m.io.inB := b
    (m.io.outSum, m.io.outCarry)
  }
}

class FullAddr extends Module {
  val io = IO(new Bundle {
    val inA = Input(UInt(1.W))
    val inB = Input(UInt(1.W))
    val inCarry = Input(UInt(1.W))

    val outSum = Output(UInt(1.W))
    val outCarry = Output(UInt(1.W))
  })

  val (halfSum, halfCarry) = HalfAddr(io.inA, io.inB)
  val (sum, carry) = HalfAddr(halfSum, io.inCarry)

  io.outSum := sum
  io.outCarry := halfCarry | carry
}

object FullAddr {
  def apply(a: UInt, b: UInt, carry: UInt): (UInt, UInt) = {
    val m = Module(new FullAddr)
    m.io.inA := a
    m.io.inB := b
    m.io.inCarry := carry
    (m.io.outSum, m.io.outCarry)
  }
}

class Addr(n: Int) extends Module {
  val io = IO(new Bundle {
    val inA = Input(UInt(n.W))
    val inB = Input(UInt(n.W))
    val inCarry = Input(UInt(1.W))

    val outSum = Output(UInt(n.W))
    val outCarry = Output(UInt(1.W))
  })

  val addrs = Seq.fill(n) {
    Module(new FullAddr)
  }
  val addrIOs = VecInit(addrs.map(_.io))
  val sums = Wire(Vec(n, UInt(1.W)))
  val carries = Wire(Vec(n + 1, UInt(1.W)))

  carries(0) := io.inCarry
  for (i <- 0 until n) {
    addrIOs(i).inA := io.inA(i)
    addrIOs(i).inB := io.inB(i)
    addrIOs(i).inCarry := carries(i)

    sums(i) := addrIOs(i).outSum
    carries(i + 1) := addrIOs(i).outCarry
  }

  io.outSum := sums.asUInt()
  io.outCarry := carries(n)
}

object Addr {
  def apply(n: Int, a: UInt, b: UInt, carry: UInt): (UInt, UInt) = {
    val m = Module(new Addr(n))
    m.io.inA := a
    m.io.inB := b
    m.io.inCarry := carry
    (m.io.outSum, m.io.outCarry)
  }
}

class SevenSegLED extends Module {
  val io = IO(new Bundle {
    val input = Input(UInt(4.W))
    val output = Output(UInt(7.W))
  })

  io.output := MuxCase(
    "b0111_1111".U,
    Seq(
      (io.input === "h0".U) -> "b0100_0000".U,
      (io.input === "h1".U) -> "b0111_1001".U,
      (io.input === "h2".U) -> "b0010_0100".U,
      (io.input === "h3".U) -> "b0011_0000".U,
      (io.input === "h4".U) -> "b0001_1001".U,
      (io.input === "h5".U) -> "b0001_0010".U,
      (io.input === "h6".U) -> "b0000_0010".U,
      (io.input === "h7".U) -> "b0111_1000".U,
      (io.input === "h8".U) -> "b0000_0000".U,
      (io.input === "h9".U) -> "b0001_1000".U,
      (io.input === "hA".U) -> "b0000_1000".U,
      (io.input === "hB".U) -> "b0000_0011".U,
      (io.input === "hC".U) -> "b0100_0110".U,
      (io.input === "hD".U) -> "b0010_0001".U,
      (io.input === "hE".U) -> "b0000_0110".U,
      (io.input === "hF".U) -> "b0000_1110".U,
    )
  )
}

object SevenSegLED {
  def apply(input: UInt): UInt = {
    val m = Module(new SevenSegLED)
    m.io.input := input
    m.io.output
  }
}

// 4-bit full addr
class AddrLED extends Module {
  val io = IO(new Bundle {
    val input_a = Input(UInt(4.W))
    val input_b = Input(UInt(4.W))

    val output_sum = Output(UInt(7.W))
    val output_carry = Output(UInt(1.W))
  })

  val (sum, carry) = Addr(4, io.input_a, io.input_b, 0.U)

  io.output_sum := SevenSegLED(sum)
  io.output_carry := carry
}

object Main {
  def main(args: Array[String]) {
    chisel3.Driver.execute(args, () => new AddrLED())
  }
}