【Mac】macでVerilogHDLを動かす ref: http://qiita.com/nomunomu/items/7bd151cbb9cce3fbd219

ha.sv

// 半加算器 ha.sv
module ha(a,b,s,c);
    input       a,b;
    output      s,c;

    assign s=a^c;
    assign c=a&b;
endmodule

// 半加算器haのテストベンチ ha_tb.sv
module ha_tb;
    reg     a,b;
    wire    s,c;

    ha ha_i(.a(a), .b(b), .s(s), .c(c));

    initial begin
        $dumpfile("out.vcd");
        $dumpvars(0,s);
        $monitor ("%t: a = %b, b = %b, s = %b, c = %b", $time, a, b, s, c);
    end

    initial begin
                a=1'b0; b=1'b1;
        #10     a=1'b1;
        #10     b=1'b0;
        #10     a=1'b0;
        #10     $finish;
    end
endmodule

iverilog.sublime-build

{
    "cmd": ["/usr/local/bin/iverilog", "-o", "$file_base_name", "$file"],
    # "cmd": ["iverilog", "-o", "$file_base_name", "$file"],

    "variants":
    [
        {
            "name": "Run",
            "cmd": ["/usr/local/bin/vvp", "$file_base_name"],
            # "cmd": ["vvp", "$file_base_name"],
        }
    ]
}

out.vcd

VCD info: dumpfile out.vcd opened for output.
                   0: a = 0, b = 1, s = 0, c = 0
                  10: a = 1, b = 1, s = 0, c = 1
                  20: a = 1, b = 0, s = 1, c = 0
                  30: a = 0, b = 0, s = 0, c = 0
[Finished in 0.0s]