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June 11, 2015 14:23
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Error building E310_RFNOC GUI=1
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| #----------------------------------------------------------- | |
| # Vivado v2014.4 (64-bit) | |
| # SW Build 1071353 on Tue Nov 18 16:47:07 MST 2014 | |
| # IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 | |
| # Start of session at: Wed Jun 10 16:26:52 2015 | |
| # Process ID: 1424 | |
| # Log file: /home/user/code/uhd/fpga-src/usrp3/top/e300/build-E310_RFNOC/project_1/project_1.runs/impl_1/e300.vdi | |
| # Journal file: /home/user/code/uhd/fpga-src/usrp3/top/e300/build-E310_RFNOC/project_1/project_1.runs/impl_1/vivado.jou | |
| #----------------------------------------------------------- | |
| source e300.tcl -notrace | |
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:0.9 available at /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/0.9/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.0 available at /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.0/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.1 available at /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.1/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:0.9 available at /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/0.9/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available | |
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.0 available at /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.0/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available | |
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.1 available at /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.1/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available | |
| Design is defaulting to srcset: sources_1 | |
| Design is defaulting to constrset: constrs_1 | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.dcp' for cell 'inst_e300_processing_system/inst_axi3_to_axi4lite_protocol_converter' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_fifo_512x64/axi4_fifo_512x64.dcp' for cell 'inst_e300_processing_system/inst_axi4_fifo_512x64' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter.dcp' for cell 'inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover.dcp' for cell 'zynq_fifo_top0/inst_axi_datamover' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm.dcp' for cell 'inst_catcodec_ddr_cmos/inst_catcodec_mmcm' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm.dcp' for cell 'inst_e300_processing_system/inst_e300_ps_fclk0_mmcm' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/processing_system7/processing_system7.dcp' for cell 'inst_e300_processing_system/inst_processing_system7' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/radio0/resp_fifo/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/radio0/rx_fifo/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/radio0/tx_fifo/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/radio0/txresp_fifo/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/radio1/resp_fifo/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/radio1/rx_fifo/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/radio1/tx_fifo/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' for cell 'e300_core0/radio1/txresp_fifo/fifo_4k_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.dcp' for cell 'e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.dcp' for cell 'e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.dcp' for cell 'e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.dcp' for cell 'e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.dcp' for cell 'e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fir/axi_fir.dcp' for cell 'e300_core0/inst_noc_block_fir_filter/inst_axi_fir' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fft/axi_fft.dcp' for cell 'e300_core0/inst_noc_block_fft/inst_axi_fft' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_to_magphase/complex_to_magphase.dcp' for cell 'e300_core0/inst_noc_block_fft/inst_complex_to_magphase' | |
| INFO: [Project 1-491] No black box instances found for design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_multiplier/complex_multiplier.dcp'. | |
| INFO: [Project 1-491] No black box instances found for design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/cordic_rotator/cordic_rotator.dcp'. | |
| INFO: [Project 1-491] No black box instances found for design checkpoint '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/divide_int32/divide_int32.dcp'. | |
| INFO: [Netlist 29-17] Analyzing 7059 Unisim elements for replacement | |
| INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds | |
| INFO: [Project 1-479] Netlist was created with Vivado 2014.4 | |
| Loading clock regions from /opt/Xilinx/Vivado/2014.4/data/parts/xilinx/zynq/zynq/xc7z020/ClockRegion.xml | |
| Loading clock buffers from /opt/Xilinx/Vivado/2014.4/data/parts/xilinx/zynq/zynq/xc7z020/ClockBuffers.xml | |
| Loading clock placement rules from /opt/Xilinx/Vivado/2014.4/data/parts/xilinx/zynq/ClockPlacerRules.xml | |
| Loading package pin functions from /opt/Xilinx/Vivado/2014.4/data/parts/xilinx/zynq/PinFunctions.xml... | |
| Loading package from /opt/Xilinx/Vivado/2014.4/data/parts/xilinx/zynq/zynq/xc7z020/clg484/Package.xml | |
| Loading io standards from /opt/Xilinx/Vivado/2014.4/data/./parts/xilinx/zynq/IOStandards.xml | |
| INFO: [Project 1-570] Preparing netlist for logic optimization | |
| WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. inst_e300_processing_system/inst_e300_ps_fclk0_mmcm/inst/clkin1_ibufg | |
| Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. | |
| INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. | |
| INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio0/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio0/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio0/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio0/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio0/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio0/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio0/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio0/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio1/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio1/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio1/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio1/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio1/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio1/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio1/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio1/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'inst_e300_processing_system/inst_e300_ps_fclk0_mmcm/clk_50MHz_in' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved for implementation tool. [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-E310_RFNOC/project_1/project_1.runs/impl_1/.Xil/Vivado-1424-redbrick/dcp_7/e300_ps_fclk0_mmcm.edf:297] | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover.xdc] for cell 'zynq_fifo_top0/inst_axi_datamover/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover.xdc] for cell 'zynq_fifo_top0/inst_axi_datamover/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm_board.xdc] for cell 'inst_catcodec_ddr_cmos/inst_catcodec_mmcm/inst' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm_board.xdc] for cell 'inst_catcodec_ddr_cmos/inst_catcodec_mmcm/inst' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm.xdc] for cell 'inst_catcodec_ddr_cmos/inst_catcodec_mmcm/inst' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm.xdc] for cell 'inst_catcodec_ddr_cmos/inst_catcodec_mmcm/inst' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm_board.xdc] for cell 'inst_e300_processing_system/inst_e300_ps_fclk0_mmcm/inst' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm_board.xdc] for cell 'inst_e300_processing_system/inst_e300_ps_fclk0_mmcm/inst' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm.xdc] for cell 'inst_e300_processing_system/inst_e300_ps_fclk0_mmcm/inst' | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm.xdc:56] | |
| INFO: [Timing 38-2] Deriving generated clocks [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm.xdc:56] | |
| get_clocks: Time (s): cpu = 00:00:18 ; elapsed = 00:00:11 . Memory (MB): peak = 1948.832 ; gain = 549.516 ; free physical = 1287 ; free virtual = 3371 | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm.xdc] for cell 'inst_e300_processing_system/inst_e300_ps_fclk0_mmcm/inst' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/processing_system7/processing_system7.xdc] for cell 'inst_e300_processing_system/inst_processing_system7/inst' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/processing_system7/processing_system7.xdc] for cell 'inst_e300_processing_system/inst_processing_system7/inst' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio1/txresp_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio1/txresp_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio1/tx_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio1/tx_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio1/rx_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio1/rx_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio1/resp_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio1/resp_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio0/txresp_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio0/txresp_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio0/tx_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio0/tx_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio0/rx_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio0/rx_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio0/resp_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio0/resp_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc] for cell 'e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk.xdc] for cell 'e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk.xdc] for cell 'e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk.xdc] for cell 'e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk.xdc] for cell 'e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk.xdc] for cell 'e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk.xdc] for cell 'e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk.xdc] for cell 'e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk.xdc] for cell 'e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk.xdc] for cell 'e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk.xdc] for cell 'e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/e300.xdc] | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/e300.xdc] | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/timing.xdc] | |
| WARNING: [Vivado 12-2489] -input_jitter contains time 1.628100 which will be rounded to 1.628 to ensure it is an integer multiple of 1 picosecond [/home/user/code/uhd/fpga-src/usrp3/top/e300/timing.xdc:11] | |
| INFO: [Timing 38-2] Deriving generated clocks [/home/user/code/uhd/fpga-src/usrp3/top/e300/timing.xdc:25] | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/timing.xdc] | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_fifo_512x64/axi4_fifo_512x64.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/processing_system7/processing_system7.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fir/axi_fir.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fft/axi_fft.dcp' | |
| INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_to_magphase/complex_to_magphase.dcp' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover_clocks.xdc] for cell 'zynq_fifo_top0/inst_axi_datamover/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover_clocks.xdc] for cell 'zynq_fifo_top0/inst_axi_datamover/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio1/txresp_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio1/txresp_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio1/tx_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio1/tx_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio1/rx_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio1/rx_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio1/resp_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio1/resp_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio0/txresp_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio0/txresp_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio0/tx_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio0/tx_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio0/rx_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio0/rx_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio0/resp_fifo/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio0/resp_fifo/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc] for cell 'e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc] for cell 'e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc] for cell 'e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc] for cell 'e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc] for cell 'e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc] for cell 'e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc] for cell 'e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc] for cell 'e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc] for cell 'e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0' | |
| Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc] for cell 'e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0' | |
| Finished Parsing XDC File [/home/user/code/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc] for cell 'e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0' | |
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |
| INFO: [Project 1-111] Unisim Transformation Summary: | |
| A total of 1922 instances were transformed. | |
| IOBUF => IOBUF (IBUF, OBUFT): 6 instances | |
| RAM16X1D => RAM32X1D (RAMD32, RAMD32): 1026 instances | |
| RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 65 instances | |
| RAM32X1D => RAM32X1D (RAMD32, RAMD32): 793 instances | |
| RAM64X1S => RAM64X1S (RAMS64E): 32 instances | |
| link_design: Time (s): cpu = 00:01:27 ; elapsed = 00:00:53 . Memory (MB): peak = 2070.832 ; gain = 1234.762 ; free physical = 1241 ; free virtual = 3227 | |
| Command: opt_design | |
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' | |
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' | |
| Running DRC as a precondition to command opt_design | |
| Starting DRC Task | |
| INFO: [Drc 23-27] Running DRC with 8 threads | |
| INFO: [Project 1-461] DRC finished with 0 Errors | |
| INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. | |
| Time (s): cpu = 00:00:00.85 ; elapsed = 00:00:00.97 . Memory (MB): peak = 2077.859 ; gain = 6.855 ; free physical = 1240 ; free virtual = 3227 | |
| Starting Logic Optimization Task | |
| Phase 1 Retarget | |
| INFO: [Opt 31-138] Pushed 43 inverter(s) to 153 load pin(s). | |
| INFO: [Opt 31-49] Retargeted 0 cell(s). | |
| Phase 1 Retarget | Checksum: 217c1f099 | |
| Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2077.859 ; gain = 0.000 ; free physical = 1227 ; free virtual = 3216 | |
| Phase 2 Constant Propagation | |
| INFO: [Opt 31-138] Pushed 1 inverter(s) to 2 load pin(s). | |
| INFO: [Opt 31-10] Eliminated 1619 cells. | |
| Phase 2 Constant Propagation | Checksum: 21466f0ae | |
| Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2077.859 ; gain = 0.000 ; free physical = 1184 ; free virtual = 3205 | |
| Phase 3 Sweep | |
| INFO: [Opt 31-12] Eliminated 22160 unconnected nets. | |
| INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. | |
| INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. | |
| INFO: [Opt 31-11] Eliminated 3712 unconnected cells. | |
| Phase 3 Sweep | Checksum: 1ff052f87 | |
| Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2077.859 ; gain = 0.000 ; free physical = 1148 ; free virtual = 3193 | |
| Ending Logic Optimization Task | Checksum: 1ff052f87 | |
| Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2077.859 ; gain = 0.000 ; free physical = 1147 ; free virtual = 3193 | |
| Implement Debug Cores | Checksum: 1954f72d4 | |
| Logic Optimization | Checksum: 1954f72d4 | |
| Starting Power Optimization Task | |
| INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 3.12 ns. | |
| INFO: [Pwropt 34-9] Applying IDT optimizations ... | |
| INFO: [Pwropt 34-10] Applying ODC optimizations ... | |
| Starting PowerOpt Patch Enables Task | |
| INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 142 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. | |
| INFO: [Pwropt 34-201] Structural ODC has moved 103 WE to EN ports | |
| Number of BRAM Ports augmented: 10 newly gated: 108 Total Ports: 284 | |
| Number of Flops added for Enable Generation: 4 | |
| Ending PowerOpt Patch Enables Task | Checksum: 1f2f64369 | |
| Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2386.867 ; gain = 0.000 ; free physical = 804 ; free virtual = 2869 | |
| Ending Power Optimization Task | Checksum: 1f2f64369 | |
| Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2386.867 ; gain = 309.008 ; free physical = 804 ; free virtual = 2870 | |
| INFO: [Common 17-83] Releasing license: Implementation | |
| 88 Infos, 55 Warnings, 0 Critical Warnings and 0 Errors encountered. | |
| opt_design completed successfully | |
| opt_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:46 . Memory (MB): peak = 2386.867 ; gain = 316.035 ; free physical = 804 ; free virtual = 2870 | |
| Writing placer database... | |
| Writing XDEF routing. | |
| Writing XDEF routing logical nets. | |
| Writing XDEF routing special nets. | |
| Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2390.875 ; gain = 0.000 ; free physical = 800 ; free virtual = 2869 | |
| write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2390.879 ; gain = 4.012 ; free physical = 790 ; free virtual = 2867 | |
| INFO: [Drc 23-27] Running DRC with 8 threads | |
| INFO: [Coretcl 2-168] The results of DRC are in file /home/user/code/uhd/fpga-src/usrp3/top/e300/build-E310_RFNOC/project_1/project_1.runs/impl_1/e300_drc_opted.rpt. | |
| report_drc: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 2390.879 ; gain = 0.000 ; free physical = 787 ; free virtual = 2867 | |
| Command: place_design | |
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' | |
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' | |
| INFO: [Drc 23-27] Running DRC with 8 threads | |
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |
| Running DRC as a precondition to command place_design | |
| INFO: [Drc 23-27] Running DRC with 8 threads | |
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |
| Starting Placer Task | |
| INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs | |
| Phase 1 Placer Runtime Estimator | |
| Phase 1 Placer Runtime Estimator | Checksum: 1722b669f | |
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2390.887 ; gain = 0.000 ; free physical = 786 ; free virtual = 2867 | |
| Phase 2 Placer Initialization | |
| Phase 2.1 Placer Initialization Core | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2390.887 ; gain = 0.000 ; free physical = 786 ; free virtual = 2868 | |
| INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. | |
| INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. | |
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2390.887 ; gain = 0.000 ; free physical = 785 ; free virtual = 2867 | |
| Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device | |
| Phase 2.1.1.1 Pre-Place Cells | |
| Phase 2.1.1.1 Pre-Place Cells | Checksum: 7c2f1a95 | |
| Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2390.887 ; gain = 0.000 ; free physical = 785 ; free virtual = 2867 | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/inst_noc_block_fft/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/inst_noc_block_fft/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/inst_noc_block_fir_filter/inst_noc_shell/in_fifo/main_fifo_2clk/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/inst_noc_block_fir_filter/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio0/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio0/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio0/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio0/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio0/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio0/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio0/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio0/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio0/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio0/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio0/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio1/ctrl_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio1/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio1/resp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio1/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio1/rx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio1/settings_bus_crossclock/settings_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio1/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio1/tx_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and e300_core0/radio1/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register e300_core0/radio1/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and e300_core0/radio1/txresp_fifo/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Constraints 18-1079] Register inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and inst_e300_processing_system/inst_axi4_to_axi3_protocol_converter/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers. | |
| WARNING: [Place 30-87] Partially locked IO Bus is found. Following components of the IO Bus DB_EXP_1_8V are not locked: 'DB_EXP_1_8V[30]' 'DB_EXP_1_8V[29]' 'DB_EXP_1_8V[28]' 'DB_EXP_1_8V[27]' 'DB_EXP_1_8V[26]' 'DB_EXP_1_8V[25]' 'DB_EXP_1_8V[23]' 'DB_EXP_1_8V[22]' 'DB_EXP_1_8V[21]' 'DB_EXP_1_8V[20]' 'DB_EXP_1_8V[19]' 'DB_EXP_1_8V[18]' 'DB_EXP_1_8V[17]' 'DB_EXP_1_8V[16]' 'DB_EXP_1_8V[15]' 'DB_EXP_1_8V[14]' 'DB_EXP_1_8V[13]' 'DB_EXP_1_8V[12]' 'DB_EXP_1_8V[7]' 'DB_EXP_1_8V[4]' 'DB_EXP_1_8V[3]' 'DB_EXP_1_8V[2]' 'DB_EXP_1_8V[1]' 'DB_EXP_1_8V[0]' | |
| WARNING: [Place 30-568] A LUT 'e300_core0/sr_misc/refsmp[0]_i_1' is driving clock pin of 25 registers. This could lead to large hold time violations. First few involved registers are: | |
| ppslp/tpps_reg {FDRE} | |
| ppslp/tcnt_reg[9] {FDRE} | |
| ppslp/tcnt_reg[8] {FDRE} | |
| ppslp/tcnt_reg[7] {FDRE} | |
| ppslp/tcnt_reg[6] {FDRE} | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |
| Phase 2.1.1.2 IO & Clk Clean Up | |
| WARNING: [Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. | |
| TCXO_CLK_IBUF_inst (IBUF.O) is locked to IOB_X1Y73 | |
| ppslp/clkgen (PLLE2_ADV.CLKIN1) is provisionally placed by clockplacer on PLLE2_ADV_X1Y0 | |
| Resolution: A dedicated routing path between the two can be used if: (a) The clock-capable IO (CCIO) is placed on a CCIO capable site (b) The PLL is placed in the same clock region as the CCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays. | |
| Phase 2.1.1.2 IO & Clk Clean Up | Checksum: 7c2f1a95 | |
| Time (s): cpu = 00:00:47 ; elapsed = 00:00:34 . Memory (MB): peak = 2420.934 ; gain = 30.047 ; free physical = 787 ; free virtual = 2877 | |
| Phase 2.1.1.3 Implementation Feasibility check On IDelay | |
| Phase 2.1.1.3 Implementation Feasibility check On IDelay | Checksum: 7c2f1a95 | |
| Time (s): cpu = 00:00:47 ; elapsed = 00:00:34 . Memory (MB): peak = 2420.934 ; gain = 30.047 ; free physical = 787 ; free virtual = 2876 | |
| Phase 2.1.1.4 Commit IO Placement | |
| Phase 2.1.1.4 Commit IO Placement | Checksum: 53e68a6b | |
| Time (s): cpu = 00:00:47 ; elapsed = 00:00:34 . Memory (MB): peak = 2420.934 ; gain = 30.047 ; free physical = 787 ; free virtual = 2876 | |
| Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fa57949e | |
| Time (s): cpu = 00:00:47 ; elapsed = 00:00:34 . Memory (MB): peak = 2420.934 ; gain = 30.047 ; free physical = 787 ; free virtual = 2876 | |
| Phase 2.1.2 Build Placer Netlist Model | |
| Phase 2.1.2.1 Place Init Design | |
| Phase 2.1.2.1.1 Init Lut Pin Assignment | |
| Phase 2.1.2.1.1 Init Lut Pin Assignment | Checksum: 176601edd | |
| Time (s): cpu = 00:00:52 ; elapsed = 00:00:38 . Memory (MB): peak = 2420.934 ; gain = 30.047 ; free physical = 786 ; free virtual = 2876 | |
| Phase 2.1.2.1 Place Init Design | Checksum: 14111c7e8 | |
| Time (s): cpu = 00:02:31 ; elapsed = 00:00:58 . Memory (MB): peak = 2420.934 ; gain = 30.047 ; free physical = 782 ; free virtual = 2874 | |
| Phase 2.1.2 Build Placer Netlist Model | Checksum: 14111c7e8 | |
| Time (s): cpu = 00:02:32 ; elapsed = 00:00:58 . Memory (MB): peak = 2420.934 ; gain = 30.047 ; free physical = 782 ; free virtual = 2874 | |
| Phase 2.1.3 Constrain Clocks/Macros | |
| Phase 2.1.3.1 Constrain Global/Regional Clocks | |
| Phase 2.1.3.1 Constrain Global/Regional Clocks | Checksum: 14111c7e8 | |
| Time (s): cpu = 00:02:32 ; elapsed = 00:00:58 . Memory (MB): peak = 2420.934 ; gain = 30.047 ; free physical = 782 ; free virtual = 2874 | |
| Phase 2.1.3 Constrain Clocks/Macros | Checksum: 14111c7e8 | |
| Time (s): cpu = 00:02:32 ; elapsed = 00:00:58 . Memory (MB): peak = 2420.934 ; gain = 30.047 ; free physical = 782 ; free virtual = 2874 | |
| Phase 2.1 Placer Initialization Core | Checksum: 14111c7e8 | |
| Time (s): cpu = 00:02:32 ; elapsed = 00:00:59 . Memory (MB): peak = 2420.934 ; gain = 30.047 ; free physical = 783 ; free virtual = 2874 | |
| Phase 2 Placer Initialization | Checksum: 14111c7e8 | |
| Time (s): cpu = 00:02:32 ; elapsed = 00:00:59 . Memory (MB): peak = 2420.934 ; gain = 30.047 ; free physical = 783 ; free virtual = 2874 | |
| Phase 3 Global Placement | |
| Phase 3 Global Placement | Checksum: 16beffe93 | |
| Time (s): cpu = 00:08:59 ; elapsed = 00:04:20 . Memory (MB): peak = 2449.246 ; gain = 58.359 ; free physical = 724 ; free virtual = 2834 | |
| Phase 4 Detail Placement | |
| Phase 4.1 Commit Multi Column Macros | |
| Phase 4.1 Commit Multi Column Macros | Checksum: 16beffe93 | |
| Time (s): cpu = 00:09:00 ; elapsed = 00:04:20 . Memory (MB): peak = 2449.246 ; gain = 58.359 ; free physical = 724 ; free virtual = 2834 | |
| Phase 4.2 Commit Most Macros & LUTRAMs | |
| Phase 4.2 Commit Most Macros & LUTRAMs | Checksum: 1e59f8c1a | |
| Time (s): cpu = 00:12:15 ; elapsed = 00:06:39 . Memory (MB): peak = 2453.652 ; gain = 62.766 ; free physical = 716 ; free virtual = 2828 | |
| Phase 4.3 Area Swap Optimization | |
| Phase 4.3 Area Swap Optimization | Checksum: 13ba3cb54 | |
| Time (s): cpu = 00:12:16 ; elapsed = 00:06:40 . Memory (MB): peak = 2453.652 ; gain = 62.766 ; free physical = 716 ; free virtual = 2828 | |
| Phase 4.4 updateClock Trees: DP | |
| Phase 4.4 updateClock Trees: DP | Checksum: 13ba3cb54 | |
| Time (s): cpu = 00:12:17 ; elapsed = 00:06:40 . Memory (MB): peak = 2453.652 ; gain = 62.766 ; free physical = 716 ; free virtual = 2828 | |
| Phase 4.5 Timing Path Optimizer | |
| Phase 4.5 Timing Path Optimizer | Checksum: 102045bb3 | |
| Time (s): cpu = 00:12:51 ; elapsed = 00:06:47 . Memory (MB): peak = 2453.652 ; gain = 62.766 ; free physical = 716 ; free virtual = 2828 | |
| Phase 4.6 Small Shape Detail Placement | |
| Phase 4.6.1 Commit Small Macros & Core Logic | |
| Phase 4.6.1.1 setBudgets | |
| Phase 4.6.1.1 setBudgets | Checksum: 137ab1da0 | |
| Time (s): cpu = 00:12:52 ; elapsed = 00:06:47 . Memory (MB): peak = 2453.652 ; gain = 62.766 ; free physical = 716 ; free virtual = 2828 | |
| Phase 4.6.1.2 Commit Slice Clusters | |
| Phase 4.6.1.2 Commit Slice Clusters | Checksum: ff3d05be | |
| Time (s): cpu = 00:13:41 ; elapsed = 00:07:10 . Memory (MB): peak = 2500.254 ; gain = 109.367 ; free physical = 669 ; free virtual = 2783 | |
| Phase 4.6.1 Commit Small Macros & Core Logic | Checksum: ff3d05be | |
| Time (s): cpu = 00:13:41 ; elapsed = 00:07:10 . Memory (MB): peak = 2500.254 ; gain = 109.367 ; free physical = 669 ; free virtual = 2783 | |
| Phase 4.6.2 Clock Restriction Legalization for Leaf Columns | |
| Phase 4.6.2 Clock Restriction Legalization for Leaf Columns | Checksum: ff3d05be | |
| Time (s): cpu = 00:13:43 ; elapsed = 00:07:11 . Memory (MB): peak = 2504.254 ; gain = 113.367 ; free physical = 665 ; free virtual = 2779 | |
| Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins | |
| Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins | Checksum: ff3d05be | |
| Time (s): cpu = 00:13:44 ; elapsed = 00:07:11 . Memory (MB): peak = 2506.254 ; gain = 115.367 ; free physical = 663 ; free virtual = 2777 | |
| Phase 4.6 Small Shape Detail Placement | Checksum: ff3d05be | |
| Time (s): cpu = 00:13:44 ; elapsed = 00:07:12 . Memory (MB): peak = 2506.254 ; gain = 115.367 ; free physical = 663 ; free virtual = 2777 | |
| Phase 4.7 Re-assign LUT pins | |
| Phase 4.7 Re-assign LUT pins | Checksum: ff3d05be | |
| Time (s): cpu = 00:13:46 ; elapsed = 00:07:14 . Memory (MB): peak = 2506.254 ; gain = 115.367 ; free physical = 663 ; free virtual = 2777 | |
| Phase 4 Detail Placement | Checksum: ff3d05be | |
| Time (s): cpu = 00:13:46 ; elapsed = 00:07:14 . Memory (MB): peak = 2506.254 ; gain = 115.367 ; free physical = 663 ; free virtual = 2777 | |
| Phase 5 Post Placement Optimization and Clean-Up | |
| Phase 5.1 PCOPT Shape updates | |
| Phase 5.1 PCOPT Shape updates | Checksum: 97187631 | |
| Time (s): cpu = 00:13:48 ; elapsed = 00:07:15 . Memory (MB): peak = 2543.770 ; gain = 152.883 ; free physical = 644 ; free virtual = 2758 | |
| Phase 5.2 Post Commit Optimization | |
| Phase 5.2.1 updateClock Trees: PCOPT | |
| Phase 5.2.1 updateClock Trees: PCOPT | Checksum: 97187631 | |
| Time (s): cpu = 00:13:48 ; elapsed = 00:07:15 . Memory (MB): peak = 2543.770 ; gain = 152.883 ; free physical = 644 ; free virtual = 2758 | |
| Phase 5.2.2 Post Placement Optimization | |
| Phase 5.2.2.1 Post Placement Timing Optimization | |
| Phase 5.2.2.1.1 Restore Best Placement | |
| Phase 5.2.2.1.1 Restore Best Placement | Checksum: 1534dbd9f | |
| Time (s): cpu = 00:14:44 ; elapsed = 00:07:30 . Memory (MB): peak = 2580.473 ; gain = 189.586 ; free physical = 608 ; free virtual = 2723 | |
| INFO: [Place 30-746] Post Placement Timing Summary WNS=0.522. For the most accurate timing information please run report_timing. | |
| Phase 5.2.2.1 Post Placement Timing Optimization | Checksum: 1534dbd9f | |
| Time (s): cpu = 00:14:44 ; elapsed = 00:07:30 . Memory (MB): peak = 2580.473 ; gain = 189.586 ; free physical = 608 ; free virtual = 2723 | |
| Phase 5.2.2 Post Placement Optimization | Checksum: 1534dbd9f | |
| Time (s): cpu = 00:14:44 ; elapsed = 00:07:31 . Memory (MB): peak = 2580.473 ; gain = 189.586 ; free physical = 608 ; free virtual = 2722 | |
| Phase 5.2 Post Commit Optimization | Checksum: 1534dbd9f | |
| Time (s): cpu = 00:14:44 ; elapsed = 00:07:31 . Memory (MB): peak = 2580.473 ; gain = 189.586 ; free physical = 608 ; free virtual = 2722 | |
| Phase 5.3 Sweep Clock Roots: Post-Placement | |
| Phase 5.3 Sweep Clock Roots: Post-Placement | Checksum: 1534dbd9f | |
| Time (s): cpu = 00:14:44 ; elapsed = 00:07:31 . Memory (MB): peak = 2580.473 ; gain = 189.586 ; free physical = 608 ; free virtual = 2722 | |
| Phase 5.4 Post Placement Cleanup | |
| Phase 5.4 Post Placement Cleanup | Checksum: 1534dbd9f | |
| Time (s): cpu = 00:14:45 ; elapsed = 00:07:31 . Memory (MB): peak = 2580.473 ; gain = 189.586 ; free physical = 608 ; free virtual = 2722 | |
| Phase 5.5 Placer Reporting | |
| Phase 5.5.1 Restore STA | |
| Phase 5.5.1 Restore STA | Checksum: 1534dbd9f | |
| Time (s): cpu = 00:14:45 ; elapsed = 00:07:32 . Memory (MB): peak = 2580.473 ; gain = 189.586 ; free physical = 607 ; free virtual = 2722 | |
| Phase 5.5 Placer Reporting | Checksum: 1534dbd9f | |
| Time (s): cpu = 00:14:45 ; elapsed = 00:07:32 . Memory (MB): peak = 2580.473 ; gain = 189.586 ; free physical = 607 ; free virtual = 2722 | |
| Phase 5.6 Final Placement Cleanup | |
| Phase 5.6 Final Placement Cleanup | Checksum: 1b7568064 | |
| Time (s): cpu = 00:14:46 ; elapsed = 00:07:32 . Memory (MB): peak = 2580.473 ; gain = 189.586 ; free physical = 607 ; free virtual = 2722 | |
| Phase 5 Post Placement Optimization and Clean-Up | Checksum: 1b7568064 | |
| Time (s): cpu = 00:14:46 ; elapsed = 00:07:32 . Memory (MB): peak = 2580.473 ; gain = 189.586 ; free physical = 607 ; free virtual = 2722 | |
| Ending Placer Task | Checksum: 1aa0d3fa5 | |
| Time (s): cpu = 00:14:46 ; elapsed = 00:07:32 . Memory (MB): peak = 2580.473 ; gain = 189.586 ; free physical = 607 ; free virtual = 2722 | |
| INFO: [Common 17-83] Releasing license: Implementation | |
| 104 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. | |
| place_design completed successfully | |
| place_design: Time (s): cpu = 00:14:55 ; elapsed = 00:07:37 . Memory (MB): peak = 2580.473 ; gain = 189.594 ; free physical = 607 ; free virtual = 2722 | |
| Writing placer database... | |
| Writing XDEF routing. | |
| Writing XDEF routing logical nets. | |
| Writing XDEF routing special nets. | |
| Write XDEF Complete: Time (s): cpu = 00:00:22 ; elapsed = 00:00:11 . Memory (MB): peak = 2580.477 ; gain = 0.000 ; free physical = 505 ; free virtual = 2719 | |
| write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:13 . Memory (MB): peak = 2580.477 ; gain = 0.004 ; free physical = 586 ; free virtual = 2719 | |
| report_io: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2580.477 ; gain = 0.000 ; free physical = 586 ; free virtual = 2720 | |
| report_utilization: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2580.477 ; gain = 0.000 ; free physical = 587 ; free virtual = 2721 | |
| report_control_sets: Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2580.477 ; gain = 0.000 ; free physical = 586 ; free virtual = 2721 | |
| Command: route_design | |
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' | |
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' | |
| Running DRC as a precondition to command route_design | |
| INFO: [Drc 23-27] Running DRC with 8 threads | |
| WARNING: [Drc 23-20] Rule violation (PLCK-20) Clock Placer Checks - Sub-optimal placement for a clock-capable IO pin and PLL pair. | |
| Resolution: A dedicated routing path between the two can be used if: (a) The clock-capable IO (CCIO) is placed on a CCIO capable site (b) The PLL is placed in the same clock region as the CCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays. | |
| This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. | |
| TCXO_CLK_IBUF_inst (IBUF.O) is locked to M20 | |
| ppslp/clkgen (PLLE2_ADV.CLKIN1) is provisionally placed by clockplacer on PLLE2_ADV_X1Y0 | |
| WARNING: [Drc 23-20] Rule violation (PLIO-3) Placement Constraints Check for IO constraints - Partially locked IO Bus is found. Following components of the IO Bus DB_EXP_1_8V[34:0] are not locked: DB_EXP_1_8V[30] DB_EXP_1_8V[29] DB_EXP_1_8V[28] DB_EXP_1_8V[27] DB_EXP_1_8V[26] DB_EXP_1_8V[25] DB_EXP_1_8V[23] DB_EXP_1_8V[22] DB_EXP_1_8V[21] DB_EXP_1_8V[20] DB_EXP_1_8V[19] DB_EXP_1_8V[18] DB_EXP_1_8V[17] DB_EXP_1_8V[16] DB_EXP_1_8V[15] DB_EXP_1_8V[14] DB_EXP_1_8V[13] DB_EXP_1_8V[12] DB_EXP_1_8V[7] DB_EXP_1_8V[4] DB_EXP_1_8V[3] DB_EXP_1_8V[2] DB_EXP_1_8V[1] DB_EXP_1_8V[0] | |
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Warnings | |
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |
| Starting Routing Task | |
| INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs | |
| Phase 1 Build RT Design | |
| Phase 1 Build RT Design | Checksum: c2b1d3cc | |
| Time (s): cpu = 00:00:33 ; elapsed = 00:00:19 . Memory (MB): peak = 2580.484 ; gain = 0.000 ; free physical = 573 ; free virtual = 2710 | |
| Phase 2 Router Initialization | |
| Phase 2.1 Create Timer | |
| Phase 2.1 Create Timer | Checksum: c2b1d3cc | |
| Time (s): cpu = 00:00:35 ; elapsed = 00:00:21 . Memory (MB): peak = 2580.484 ; gain = 0.000 ; free physical = 570 ; free virtual = 2707 | |
| Phase 2.2 Pre Route Cleanup | |
| Phase 2.2 Pre Route Cleanup | Checksum: c2b1d3cc | |
| Time (s): cpu = 00:00:35 ; elapsed = 00:00:21 . Memory (MB): peak = 2592.473 ; gain = 11.988 ; free physical = 551 ; free virtual = 2689 | |
| Number of Nodes with overlaps = 0 | |
| Phase 2.3 Update Timing | |
| Phase 2.3 Update Timing | Checksum: 1d2e570af | |
| Time (s): cpu = 00:02:33 ; elapsed = 00:00:45 . Memory (MB): peak = 2792.234 ; gain = 211.750 ; free physical = 354 ; free virtual = 2493 | |
| INFO: [Route 35-57] Estimated Timing Summary | WNS=0.39 | TNS=0 | WHS=-0.388 | THS=-877 | | |
| Phase 2 Router Initialization | Checksum: 26c086cc8 | |
| Time (s): cpu = 00:03:56 ; elapsed = 00:01:00 . Memory (MB): peak = 2832.375 ; gain = 251.891 ; free physical = 311 ; free virtual = 2448 | |
| Phase 3 Initial Routing | |
| Phase 3 Initial Routing | Checksum: 13ec4ea78 | |
| Time (s): cpu = 00:04:57 ; elapsed = 00:01:10 . Memory (MB): peak = 2832.375 ; gain = 251.891 ; free physical = 311 ; free virtual = 2447 | |
| Phase 4 Rip-up And Reroute | |
| Phase 4.1 Global Iteration 0 | |
| Number of Nodes with overlaps = 22729 | |
| Number of Nodes with overlaps = 10997 | |
| Phase 4.1.1 Update Timing | |
| Phase 4.1.1 Update Timing | Checksum: 16f3aefe1 | |
| Time (s): cpu = 00:54:01 ; elapsed = 00:14:24 . Memory (MB): peak = 2832.375 ; gain = 251.891 ; free physical = 265 ; free virtual = 2452 | |
| INFO: [Route 35-57] Estimated Timing Summary | WNS=0.528 | TNS=0 | WHS=N/A | THS=N/A | | |
| Phase 4.1 Global Iteration 0 | Checksum: 18a22aa70 | |
| Time (s): cpu = 00:55:26 ; elapsed = 00:14:39 . Memory (MB): peak = 2872.516 ; gain = 292.031 ; free physical = 236 ; free virtual = 2423 | |
| Phase 4.2 Global Iteration 1 | |
| Number of Nodes with overlaps = 25603 | |
| Number of Nodes with overlaps = 9891 | |
| Number of Nodes with overlaps = 6270 | |
| Number of Nodes with overlaps = 4815 | |
| Phase 4.2.1 Update Timing | |
| Phase 4.2.1 Update Timing | Checksum: 15977e535 | |
| Time (s): cpu = 03:05:04 ; elapsed = 00:49:08 . Memory (MB): peak = 2872.516 ; gain = 292.031 ; free physical = 261 ; free virtual = 2385 | |
| INFO: [Route 35-57] Estimated Timing Summary | WNS=0.384 | TNS=0 | WHS=N/A | THS=N/A | | |
| Phase 4.2 Global Iteration 1 | Checksum: 20c77dd03 | |
| Time (s): cpu = 03:06:29 ; elapsed = 00:49:24 . Memory (MB): peak = 2872.516 ; gain = 292.031 ; free physical = 203 ; free virtual = 2327 | |
| Phase 4.3 Global Iteration 2 | |
| Number of Nodes with overlaps = 35482 | |
| Number of Nodes with overlaps = 15083 | |
| Number of Nodes with overlaps = 7021 | |
| Number of Nodes with overlaps = 4240 | |
| Number of Nodes with overlaps = 3119 | |
| Number of Nodes with overlaps = 2689 | |
| Number of Nodes with overlaps = 2153 | |
| Number of Nodes with overlaps = 1902 | |
| Number of Nodes with overlaps = 1896 | |
| Number of Nodes with overlaps = 1899 | |
| Number of Nodes with overlaps = 1731 | |
| Phase 4.3.1 Update Timing | |
| Phase 4.3.1 Update Timing | Checksum: 16a325c49 | |
| Time (s): cpu = 09:05:43 ; elapsed = 02:24:21 . Memory (MB): peak = 2884.516 ; gain = 304.031 ; free physical = 331 ; free virtual = 2404 | |
| INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.852 | TNS=-14.8 | WHS=N/A | THS=N/A | | |
| Phase 4.3 Global Iteration 2 | Checksum: 19b2c726d | |
| Time (s): cpu = 09:07:08 ; elapsed = 02:24:37 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 308 ; free virtual = 2381 | |
| Phase 4.4 Global Iteration 3 | |
| Number of Nodes with overlaps = 45848 | |
| Number of Nodes with overlaps = 22478 | |
| Number of Nodes with overlaps = 12824 | |
| Number of Nodes with overlaps = 6890 | |
| Number of Nodes with overlaps = 4168 | |
| Number of Nodes with overlaps = 2647 | |
| Number of Nodes with overlaps = 1725 | |
| Phase 4.4.1 Update Timing | |
| Phase 4.4.1 Update Timing | Checksum: 1d1f7291b | |
| Time (s): cpu = 16:47:07 ; elapsed = 04:25:28 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 262 ; free virtual = 2363 | |
| INFO: [Route 35-57] Estimated Timing Summary | WNS=-3.22 | TNS=-301 | WHS=N/A | THS=N/A | | |
| Phase 4.4 Global Iteration 3 | Checksum: 1c7341d39 | |
| Time (s): cpu = 16:48:33 ; elapsed = 04:25:43 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 262 ; free virtual = 2364 | |
| Phase 4.5 Global Iteration 4 | |
| Phase 4.5 Global Iteration 4 | Checksum: 200fcd2c6 | |
| Time (s): cpu = 17:04:50 ; elapsed = 04:30:05 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 348 ; free virtual = 2450 | |
| Phase 4 Rip-up And Reroute | Checksum: 200fcd2c6 | |
| Time (s): cpu = 17:04:50 ; elapsed = 04:30:05 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 348 ; free virtual = 2450 | |
| Phase 5 Delay CleanUp | |
| Phase 5 Delay CleanUp | Checksum: 1ffab96e1 | |
| Time (s): cpu = 17:04:52 ; elapsed = 04:30:06 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 347 ; free virtual = 2449 | |
| Phase 6 Clock Skew Optimization | |
| Phase 6 Clock Skew Optimization | Checksum: 1ffab96e1 | |
| Time (s): cpu = 17:04:52 ; elapsed = 04:30:07 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 347 ; free virtual = 2449 | |
| Phase 7 Post Hold Fix | |
| Phase 7 Post Hold Fix | Checksum: 1ffab96e1 | |
| Time (s): cpu = 17:04:53 ; elapsed = 04:30:07 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 347 ; free virtual = 2449 | |
| Phase 8 Route finalize | |
| Router Utilization Summary | |
| Global Vertical Routing Utilization = 63.4718 % | |
| Global Horizontal Routing Utilization = 60.8616 % | |
| Routable Net Status* | |
| *Does not include unroutable nets such as driverless and loadless. | |
| Run report_route_status for detailed report. | |
| Number of Failed Nets = 0 | |
| Number of Unrouted Nets = 0 | |
| Number of Partially Routed Nets = 0 | |
| Number of Node Overlaps = 1560 | |
| Congestion Report | |
| North Dir 16x16 Area, Max Cong = 87.7569%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): | |
| PCIE_NULL_X45Y73 -> INT_R_X31Y85 | |
| INT_L_X32Y70 -> INT_FEEDTHRU_2_X118Y89 | |
| PCIE_NULL_X45Y57 -> INT_R_X31Y69 | |
| INT_L_X32Y54 -> INT_FEEDTHRU_2_X118Y72 | |
| INT_FEEDTHRU_2_X121Y57 -> INT_R_X63Y69 | |
| South Dir 32x32 Area, Max Cong = 85.5724%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): | |
| PCIE_NULL_X4Y57 -> INT_R_X31Y85 | |
| INT_L_X32Y22 -> INT_R_X63Y53 | |
| East Dir 16x16 Area, Max Cong = 85.9432%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): | |
| INT_L_X32Y54 -> INT_FEEDTHRU_2_X118Y72 | |
| INT_L_X32Y38 -> INT_FEEDTHRU_2_X118Y56 | |
| INT_L_X32Y22 -> INT_R_X47Y37 | |
| West Dir 32x32 Area, Max Cong = 89.6527%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): | |
| INT_L_X32Y54 -> INT_R_X63Y85 | |
| INT_L_X32Y22 -> INT_R_X63Y53 | |
| INT_L_X32Y1 -> INT_R_X63Y21 | |
| Phase 8 Route finalize | Checksum: 1fea700e7 | |
| Time (s): cpu = 17:04:53 ; elapsed = 04:30:07 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 347 ; free virtual = 2449 | |
| Phase 9 Verifying routed nets | |
| CRITICAL WARNING: [Route 35-162] 2098 signals failed to route due to routing congestion. Please run report_route_status to get a full summary of the design's routing. | |
| Below is a list of the top 10 physical nodes with signal overlaps and up to 5 of the signals that were contending for this node resource: | |
| Resolution: Run report_route_status to get a full summary of the design's routing. To find the areas of the congestion, use the route congestion Metrics in the Device View and check the logfile for the Congestion Report. | |
| 1. Tile Name: INT_R_X45Y0 Node: SW6BEG0 Overlapping Nets: 2 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk0000054f/sig000012bd | |
| e300_core0/inst_noc_block_fir_filter/inst_axi_fir/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_data_array.g_data[1].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/O1[8] | |
| 2. Tile Name: INT_L_X34Y5 Node: SW6BEG1 Overlapping Nets: 2 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk0000054f/sig000012ae | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk00000483/sig00001179 | |
| 3. Tile Name: INT_L_X30Y43 Node: SW6BEG2 Overlapping Nets: 2 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk0000054f/sig000012b8 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk00000705/sig00001593 | |
| 4. Tile Name: INT_R_X27Y16 Node: SW6BEG3 Overlapping Nets: 2 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk0000054f/sig000012b7 | |
| e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/inst_noc_input_port/str_sink_fifo/main_fifo/fifo_bram/rd_addr_reg[3] | |
| 5. Tile Name: INT_L_X26Y2 Node: SS6BEG1 Overlapping Nets: 2 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk0000054f/sig000012ae | |
| e300_core0/inst_noc_block_axi_fifo_loopback/inst_noc_shell/out_fifo/main_fifo_2clk/fifo_4k_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_pntr_plus2[5] | |
| 6. Tile Name: INT_L_X48Y1 Node: LH0 Overlapping Nets: 2 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk0000054f/sig000012b6 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk00000120/sig00000c50 | |
| 7. Tile Name: INT_L_X40Y0 Node: LH0 Overlapping Nets: 2 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk0000054f/sig000012b5 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk000002eb/sig00000f19 | |
| 8. Tile Name: INT_L_X38Y0 Node: NW6BEG3 Overlapping Nets: 2 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk0000054f/sig000012ae | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk00000483/sig00001177 | |
| 9. Tile Name: INT_R_X35Y4 Node: NW2BEG2 Overlapping Nets: 2 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk0000054f/sig000012ae | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk00000483/sig00001179 | |
| 10. Tile Name: INT_L_X26Y3 Node: NW2BEG2 Overlapping Nets: 2 | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk0000054f/sig000012ae | |
| e300_core0/radio0/rx_dsp.ddc_chain/hbdec1/blk00000003/blk0000054f/sig000012c2 | |
| Verification failed | |
| Phase 9 Verifying routed nets | Checksum: 1fea700e7 | |
| Time (s): cpu = 17:04:54 ; elapsed = 04:30:07 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 347 ; free virtual = 2449 | |
| CRITICAL WARNING: [Route 35-2] Design is not legally routed. There are 1560 node overlaps. | |
| Phase 10 Depositing Routes | |
| Phase 10 Depositing Routes | Checksum: 1f03e2cb7 | |
| Time (s): cpu = 17:04:58 ; elapsed = 04:30:12 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 345 ; free virtual = 2449 | |
| Phase 11 Post Router Timing | |
| Phase 11.1 Update Timing | |
| Phase 11.1 Update Timing | Checksum: 1f03e2cb7 | |
| Time (s): cpu = 17:06:01 ; elapsed = 04:30:21 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 343 ; free virtual = 2447 | |
| INFO: [Route 35-57] Estimated Timing Summary | WNS=-3.2 | TNS=-298 | WHS=-0.352 | THS=-13.9 | | |
| WARNING: [Route 35-328] Router estimated timing not met. | |
| Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. | |
| Phase 11 Post Router Timing | Checksum: 1f03e2cb7 | |
| Time (s): cpu = 17:06:01 ; elapsed = 04:30:21 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 343 ; free virtual = 2447 | |
| INFO: [Route 35-77] Router completed with failures. Please check the log file for Critical Warnings and run report_route_status for a summary of routing status. | |
| Routing Is Done. | |
| Time (s): cpu = 17:06:01 ; elapsed = 04:30:21 . Memory (MB): peak = 2924.656 ; gain = 344.172 ; free physical = 342 ; free virtual = 2447 | |
| INFO: [Common 17-83] Releasing license: Implementation | |
| 117 Infos, 107 Warnings, 2 Critical Warnings and 0 Errors encountered. | |
| route_design completed successfully | |
| route_design: Time (s): cpu = 17:06:10 ; elapsed = 04:30:26 . Memory (MB): peak = 2924.656 ; gain = 344.180 ; free physical = 342 ; free virtual = 2447 | |
| Writing placer database... | |
| Writing XDEF routing. | |
| Writing XDEF routing logical nets. | |
| Writing XDEF routing special nets. | |
| Write XDEF Complete: Time (s): cpu = 00:00:16 ; elapsed = 00:00:08 . Memory (MB): peak = 2924.660 ; gain = 0.000 ; free physical = 218 ; free virtual = 2459 | |
| write_checkpoint: Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 2924.660 ; gain = 0.004 ; free physical = 326 ; free virtual = 2460 | |
| INFO: [Drc 23-27] Running DRC with 8 threads | |
| INFO: [Coretcl 2-168] The results of DRC are in file /home/user/code/uhd/fpga-src/usrp3/top/e300/build-E310_RFNOC/project_1/project_1.runs/impl_1/e300_drc_routed.rpt. | |
| report_drc: Time (s): cpu = 00:00:34 ; elapsed = 00:00:11 . Memory (MB): peak = 2932.656 ; gain = 7.996 ; free physical = 308 ; free virtual = 2451 | |
| INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. | |
| INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs | |
| CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. | |
| report_timing_summary: Time (s): cpu = 00:02:41 ; elapsed = 00:00:35 . Memory (MB): peak = 3397.750 ; gain = 465.094 ; free physical = 176 ; free virtual = 2001 | |
| Running Vector-less Activity Propagation... | |
| Finished Running Vector-less Activity Propagation | |
| WARNING: [Power 33-218] MMCM/PLL RST static_probability should be either 0 or 1, power analysis is using 0 by default. | |
| Use 'set_switching_activity -static_probability 1 -signal_rate 0 [get_nets e300_core0/sr_misc/Q[3]]' to set the static_probability to '1' if desired. | |
| WARNING: [Power 33-218] MMCM/PLL RST static_probability should be either 0 or 1, power analysis is using 0 by default. | |
| Use 'set_switching_activity -static_probability 1 -signal_rate 0 [get_nets inst_e300_processing_system/inst_processing_system7/inst/FCLK_RESET0_N]' to set the static_probability to '1' if desired. | |
| report_power: Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3397.750 ; gain = 0.000 ; free physical = 168 ; free virtual = 2000 | |
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' | |
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' | |
| Running DRC as a precondition to command write_bitstream | |
| INFO: [Drc 23-27] Running DRC with 8 threads | |
| ERROR: [Drc 23-20] Rule violation (RTSTAT-6) Partial conflict - 2098 net(s) have a partial conflict. The problem net(s) are e300_core0/inst_noc_block_fft/inst_complex_to_magphase/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[3].eng/data_slice/y_plus_x_shift/ADD_NSUB, e300_core0/inst_noc_block_fft/inst_complex_to_magphase/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[6].eng/data_slice/y_plus_x_shift/ADD_NSUB, e300_core0/inst_noc_block_fft/inst_complex_to_magphase/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[4].eng/data_slice/y_plus_x_shift/ADD_NSUB, inst_e300_processing_system/inst_axi4_fifo_512x64/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/AR, e300_core0/inst_noc_block_fir_filter/inst_axi_fir/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_madds.g_madd[13].i_madd/i_coefin_int/A[0], e300_core0/inst_noc_block_fir_filter/inst_axi_fir/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_madds.g_madd[9].i_madd/i_coefin_int/A[0], e300_core0/inst_noc_block_fir_filter/inst_axi_fir/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_madds.g_madd[5].i_madd/i_coefin_int/A[1], e300_core0/inst_noc_block_fir_filter/inst_axi_fir/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_madds.g_madd[12].i_madd/i_coefin_int/A[1], e300_core0/inst_noc_block_fir_filter/inst_axi_fir/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_madds.g_madd[20].i_madd/i_coefin_int/A[1], e300_core0/inst_noc_block_fir_filter/inst_axi_fir/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_madds.g_madd[2].i_madd/i_coefin_int/A[1], e300_core0/inst_noc_block_fir_filter/inst_axi_fir/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_madds.g_madd[26].i_madd/i_coefin_int/A[2], e300_core0/inst_noc_block_fir_filter/inst_axi_fir/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_madds.g_madd[4].i_madd/i_coefin_int/A[2], e300_core0/inst_noc_block_fir_filter/inst_axi_fir/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_madds.g_madd[17].i_madd/i_coefin_int/A[2], e300_core0/inst_noc_block_fir_filter/inst_axi_fir/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_madds.g_madd[11].i_madd/i_coefin_int/A[2], e300_core0/inst_noc_block_fir_filter/inst_axi_fir/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_madds.g_madd[23].i_madd/i_coefin_int/A[2] (the first 15 of 2083 listed), GLOBAL_LOGIC0. | |
| WARNING: [Drc 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: | |
| set_property CFGBVS value1 [current_design] | |
| #where value1 is either VCCO or GND | |
| set_property CONFIG_VOLTAGE value2 [current_design] | |
| #where value2 is the voltage provided to configuration bank 0 | |
| Refer to the device configuration user guide for more information. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[3].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[3].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[3].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[3].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[4].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[4].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[4].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[4].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/inst_noc_block_fft/inst_complex_to_magphase/U0/i_synth/i_synth/gen_cordic.output_stage/gen_scaling.gen_x_out.scale/multiplier/gCCM.iCCM/emb_mult_ccm.dsp_ccm.dsp48_array/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 input C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/rx_dsp.ddc_chain/SCALE_I/dsp_bl.DSP48_BL input A B is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/rx_dsp.ddc_chain/SCALE_Q/dsp_bl.DSP48_BL input A B is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/rx_dsp.rx_frontend/mult_mag_corr input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/rx_dsp.rx_frontend/mult_phase_corr input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/mult_i/dsp_bl.DSP48_BL input A B is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/mult_q/dsp_bl.DSP48_BL input A B is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/old_hb.hb_interp_i/mult1 input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/old_hb.hb_interp_i/mult2 input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/old_hb.hb_interp_q/mult1 input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/old_hb.hb_interp_q/mult2 input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/old_hb.small_hb_interp_i/mult input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/old_hb.small_hb_interp_q/mult input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/tx_dsp.tx_frontend/mult_mag_corr input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio0/tx_dsp.tx_frontend/mult_phase_corr input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/rx_dsp.ddc_chain/SCALE_I/dsp_bl.DSP48_BL input A B is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/rx_dsp.ddc_chain/SCALE_Q/dsp_bl.DSP48_BL input A B is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/rx_dsp.rx_frontend/mult_mag_corr input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/rx_dsp.rx_frontend/mult_phase_corr input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/tx_dsp.duc_chain/mult_i/dsp_bl.DSP48_BL input A B is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/tx_dsp.duc_chain/mult_q/dsp_bl.DSP48_BL input A B is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/tx_dsp.duc_chain/old_hb.hb_interp_i/mult1 input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/tx_dsp.duc_chain/old_hb.hb_interp_i/mult2 input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/tx_dsp.duc_chain/old_hb.hb_interp_q/mult1 input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/tx_dsp.duc_chain/old_hb.hb_interp_q/mult2 input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/tx_dsp.duc_chain/old_hb.small_hb_interp_i/mult input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/tx_dsp.duc_chain/old_hb.small_hb_interp_q/mult input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/tx_dsp.tx_frontend/mult_mag_corr input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP e300_core0/radio1/tx_dsp.tx_frontend/mult_phase_corr input A B C is not pipelined. Pipelining DSP48 input will improve performance. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/FB_1.BF_1/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e_simd.bf_dsp48e_simd_bypass/A_ir output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/FB_1.BF_1/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e_simd.bf_dsp48e_simd_bypass/B_ir output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/hasbf2.FB_2.BF_2/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e.bf_dsp48e_bypass/A_i output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/hasbf2.FB_2.BF_2/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e.bf_dsp48e_bypass/A_r output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/hasbf2.FB_2.BF_2/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e.bf_dsp48e_bypass/B_i output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/hasbf2.FB_2.BF_2/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e.bf_dsp48e_bypass/B_r output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/FB_1.BF_1/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e_simd.bf_dsp48e_simd_bypass/A_ir output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/FB_1.BF_1/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e_simd.bf_dsp48e_simd_bypass/B_ir output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/hasbf2.FB_2.BF_2/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e.bf_dsp48e_bypass/A_i output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/hasbf2.FB_2.BF_2/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e.bf_dsp48e_bypass/A_r output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/hasbf2.FB_2.BF_2/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e.bf_dsp48e_bypass/B_i output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/hasbf2.FB_2.BF_2/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e.bf_dsp48e_bypass/B_r output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/FB_1.BF_1/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e_simd.bf_dsp48e_simd_bypass/A_ir output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/FB_1.BF_1/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e_simd.bf_dsp48e_simd_bypass/B_ir output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/hasbf2.FB_2.BF_2/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e.bf_dsp48e_bypass/A_i output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/hasbf2.FB_2.BF_2/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e.bf_dsp48e_bypass/A_r output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/hasbf2.FB_2.BF_2/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e.bf_dsp48e_bypass/B_i output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/hasbf2.FB_2.BF_2/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e.bf_dsp48e_bypass/B_r output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[3].natural_order_input.PE/FB_1.BF_1/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e_simd.bf_dsp48e_simd_bypass/A_ir output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[3].natural_order_input.PE/FB_1.BF_1/BTFLY0/dsp48_bfly_byp.bfly_dsp48_byp/dsp48e_simd.bf_dsp48e_simd_bypass/B_ir output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[3].natural_order_input.PE/hasbf2.FW_2.BF_2/dsp48s.dsps_only.vx5_dsp48es.A output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[3].natural_order_input.PE/hasbf2.FW_2.BF_2/dsp48s.dsps_only.vx5_dsp48es.B output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[4].natural_order_input.PE/FW_1.BF_1/dsp48s.dsps_only.vx5_dsp48es.A output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[4].natural_order_input.PE/FW_1.BF_1/dsp48s.dsps_only.vx5_dsp48es.B output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[4].natural_order_input.PE/hasbf2.FW_2.BF_2/dsp48s.dsps_only.vx5_dsp48es.A output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[4].natural_order_input.PE/hasbf2.FW_2.BF_2/dsp48s.dsps_only.vx5_dsp48es.B output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[5].natural_order_input.PE/FW_1.BF_1/dsp48s.dsps_only.vx5_dsp48es.A output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[5].natural_order_input.PE/FW_1.BF_1/dsp48s.dsps_only.vx5_dsp48es.B output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[5].natural_order_input.PE/hasbf2.FW_2.BF_2/dsp48s.dsps_only.vx5_dsp48es.A output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_axi_fft/U0/i_synth/xfft_inst/non_floating_point.arch_d.xfft_inst/pe_gen[5].natural_order_input.PE/hasbf2.FW_2.BF_2/dsp48s.dsps_only.vx5_dsp48es.B output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_complex_to_magphase/U0/i_synth/i_synth/gen_cordic.output_stage/gen_scaling.gen_x_out.scale/multiplier/gCCM.iCCM/emb_mult_ccm.dsp_ccm.dsp48_array/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_complex_to_magphase/U0/i_synth/i_synth/gen_cordic.output_stage/gen_scaling.gen_x_out.scale/multiplier/gCCM.iCCM/emb_mult_ccm.dsp_ccm.dsp48_array/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/inst_noc_block_fft/inst_complex_to_magsq/i_sq_mult/DSP48_inst output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/rx_dsp.ddc_chain/SCALE_I/dsp_bl.DSP48_BL output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/rx_dsp.ddc_chain/SCALE_Q/dsp_bl.DSP48_BL output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/rx_dsp.rx_frontend/mult_mag_corr output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/rx_dsp.rx_frontend/mult_phase_corr output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/mult_i/dsp_bl.DSP48_BL output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/mult_q/dsp_bl.DSP48_BL output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/old_hb.hb_interp_i/mult1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/old_hb.hb_interp_i/mult2 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/old_hb.hb_interp_q/mult1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/old_hb.hb_interp_q/mult2 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/old_hb.small_hb_interp_i/mult output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/tx_dsp.duc_chain/old_hb.small_hb_interp_q/mult output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/tx_dsp.tx_frontend/mult_mag_corr output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP e300_core0/radio0/tx_dsp.tx_frontend/mult_phase_corr output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. | |
| INFO: [Common 17-14] Message 'Drc 23-20' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. | |
| INFO: [Vivado 12-3199] DRC finished with 1 Errors, 115 Warnings, 214 Advisories | |
| INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. | |
| ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. | |
| INFO: [Common 17-83] Releasing license: Implementation | |
| write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:07 . Memory (MB): peak = 3479.312 ; gain = 81.562 ; free physical = 162 ; free virtual = 1927 | |
| ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. | |
| while executing | |
| "write_bitstream -force e300.bit " | |
| INFO: [Common 17-206] Exiting Vivado at Wed Jun 10 21:08:56 2015... |
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