Code for http://niklas-rother.de/artikel/einfache-saettigungsarithmetik-in-vhdl/

satturation_add.vhdl

entity ps2_protocol is
	generic (
		MAX_X				  : integer := 800;
		MAX_Y				  : integer := 600;
		MAX_OVERFLOW	: integer := 255
	);
	port (
		...
    );
end ps2_protocol;

architecture rtl of ps2_protocol is
	signal x_ff, x_nxt		: unsigned(10 downto 0); -- 11 bit for overflow margin
	signal y_ff, y_nxt		: unsigned(10 downto 0);
begin
	process(all)
		variable x_tmp, y_tmp : unsigned(10 downto 0);
	begin
		x_nxt <= x_ff;	
		y_nxt <= y_ff;
		
		-- the following code is addition with saturation (in a somewhat hacky way, but without a pipeline step)
		x_tmp := unsigned(signed(x_ff) + signed(delta_x); -- update x position
		x_nxt <= x_tmp;
		if x_tmp >= MAX_X then
			x_nxt <= to_unsigned(MAX_X, 11) - 1;
		end if;
		if x_tmp >= MAX_X + MAX_OVERFLOW then
			x_nxt <= (others => '0');
		end if ;
		
		y_tmp := unsigned(signed(y_ff) - signed(delta_y); -- update y position
		y_nxt <= y_tmp;
		if y_tmp >= MAX_Y then
			y_nxt <= to_unsigned(MAX_Y, 11) - 1;
		end if;
		if y_tmp >= MAX_Y + MAX_OVERFLOW then
			y_nxt <= (others => '0');
		end if;
	end process;
end architecture;