HY SYN LAB 2-2

lab2-2.asm

.INCLUDE "m168def.inc"
.LIST
.CSEG
.ORG 0

jmp main

.DEF addr1 = R21
.DEF addr2 = R22
.DEF data = R23

.DEF carry = R16
.DEF a1 = R17
.DEF a2 = R18
.DEF a3 = R19
.DEF a4 = R20

.DEF zero = R25

; Read from addr(r30:r31) put into r29
read:
    ; Wait for completion of previous write
	sbic EECR, EEPE
	rjmp read
	; Set up address (r30:r31) in address register
	out EEARH, addr1
	out EEARL, addr2
	; Start eeprom read by setting EERE
	sbi EECR, EERE
	in data, EEDR
	ret

; Write r29 to addr (r30:r31)
write:
	; Wait for completion of previous write
	sbic EECR, EEPE
	rjmp write
	; Set up address (r30:r31) in address register
	out EEARH, addr1
	out EEARL, addr2
	; Write data (r29) to register
	out EEDR, data
	; Write logical one to EEMPE
	sbi EECR, EEMPE
	; Start eeprom write by setting EEPE
	sbi EECR, EEPE
	ret

main:
	ldi addr1, 0x00

	; EEPROM test case
	ldi data, 0xAB
	ldi addr2, 0x00
	call write
	ldi data, 0xCD
	ldi addr2, 0x01
	call write
	ldi data, 0xEF
	ldi addr2, 0x02
	call write
	ldi data, 0xCD
	ldi addr2, 0x03
	call write

	; Blank Register
	ldi zero, 0

	; Set carry to 0
	ldi carry, 0

	; load data from eeprom
	ldi addr2, 0x00
	call read
	mov a1, data

	ldi addr2, 0x01
	call read
	mov a2, data

	ldi addr2, 0x02
	call read
	mov a3, data

	ldi addr2, 0x03
	call read
	mov a4, data

	; sum into a1
	add a1, a2
	adc carry, zero

	add a1, a3
	adc carry, zero

	add a1, a4
	adc carry, zero

	; Shift right
	LSR carry
	ROR a1
	LSR carry
	ROR a1

	; store a1 in eeprom 0x30
	mov data, a1
	ldi addr2, 0x30
	call write


loop:
	NOP
	jmp loop