counter examples

cnt1.v

module cnt1
  #(parameter dw = 32,
    parameter val = 100)
  (input clk,
   output reg en = 1'b0);

   reg [dw-1:0] cnt = 'd0;

   always @(posedge clk) begin
      cnt <= cnt + 1'd1;
      if (cnt == val)
	cnt <= 'd0;
      en <= (cnt == val);
   end
endmodule

cnt2.v

module cnt2
  #(parameter dw = 32,
    parameter val = 100)
  (input clk,
   output reg en = 1'b0);

   reg [dw-1:0] cnt = val;

   always @(posedge clk) begin
      cnt <= cnt - 1'd1;
      if (cnt == 0)
	cnt <= val;
      en <= (cnt == 0);
   end
endmodule

cnt3.v

module cnt3
  #(parameter dw = 32,
    parameter val = 100)
  (input clk,
   output en);

   localparam val_minus_one = val-1;

   reg [dw:0] cnt = {1'b0,val};

   always @(posedge clk) begin
      cnt <= cnt - 1'd1;
      if (cnt[dw])
	cnt <= val_minus_one;
   end

   assign en = cnt[dw];

endmodule

tb_cnt.v

module tb;
   reg clk = 1'b0;
   always #5 clk <= !clk;

   wire en1, en2, en3;

   cnt1 cnt1(clk, en1);
   cnt2 cnt2(clk, en2);
   cnt3 cnt3(clk, en3);

   always @(posedge clk) begin
      if (en1 !== en2)
	 $display("Error");
      if (en1 !== en3)
	 $display("Error");
   end

   initial begin
      $dumpfile("out.vcd");
      $dumpvars;
      #10000 $finish;
   end
endmodule

Chrome thinks this Verilog is French :-P