servive.v

`default_nettype none
module servive
(
 input wire 	   i_clk,
 input wire 	   i_rst_n,
 output wire 	   q,
 output wire 	   uart_txd);

   parameter memfile = "zephyr_hello.hex";
   parameter memsize = 8192;

   assign uart_txd = q;

   reg [4:0] 	   rst_reg = 5'b11111;

   always @(posedge i_clk)
     rst_reg <= {!i_rst_n, rst_reg[4:1]};

   servant
     #(.memfile (memfile),
       .memsize (memsize))
   servant
     (.wb_clk (i_clk),
      .wb_rst (rst_reg[0]),
      .q      (q));

endmodule