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@olofk
Created August 26, 2022 10:43
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diff --git a/edalize/icarus.py b/edalize/icarus.py
index 4e62e45..72e6df6 100644
--- a/edalize/icarus.py
+++ b/edalize/icarus.py
@@ -16,7 +16,7 @@ $(TARGET):
iverilog -s$(TOPLEVEL) -c $(TARGET).scr -o $@ $(IVERILOG_OPTIONS)
run: $(VPI_MODULES) $(TARGET)
- vvp -n -M. -l icarus.log $(patsubst %.vpi,-m%,$(VPI_MODULES)) $(TARGET) -fst $(EXTRA_OPTIONS)
+ vvp -n -M. -l icarus.log $(patsubst %.vpi,-m%,$(VPI_MODULES)) $(VVP_OPTIONS) $(TARGET) -fst $(EXTRA_OPTIONS)
clean:
$(RM) $(VPI_MODULES) $(TARGET)
@@ -53,6 +53,11 @@ class Icarus(Edatool):
"type": "String",
"desc": "Additional options for iverilog",
},
+ {
+ "name": "vvp_options",
+ "type": "String",
+ "desc": "Additional options for vvp",
+ },
],
}
@@ -110,6 +115,11 @@ class Icarus(Edatool):
" ".join(self.tool_options.get("iverilog_options", []))
)
)
+ f.write(
+ "VVP_OPTIONS := {}\n".format(
+ " ".join(self.tool_options.get("vvp_options", []))
+ )
+ )
if self.plusarg:
plusargs = []
for key, value in self.plusarg.items():
CAPI=2:
name : ::cocotb_example:0
filesets:
rtl:
files:
- my_design.sv
- test_my_design.py : {file_type : user, copyto : test_my_design.py}
file_type : systemVerilogSource
targets:
sim:
default_tool : icarus
filesets : [rtl]
parameters: [COCOTB_SIM]
toplevel : my_design
tools:
icarus:
iverilog_options: [-g2012]
vvp_options: [-M, "`cocotb-config --lib-dir`", "-m", libcocotbvpi_icarus]
timescale : 1ns/1ps
parameters:
COCOTB_SIM:
datatype : int
default: 1
paramtype : vlogdefine
MODULE=test_my_design fusesoc --cores-root=. run --target=sim cocotb_example
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