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@olofk
Created August 8, 2022 20:51
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CAPI=2:
name : ::timer:0
filesets:
rtl:
files:
- hdl/timer_thing.sv : {file_type : systemVerilogSource}
tb:
files:
- inc/higgs_helper.hpp : {is_include_file : true}
- test_0.cpp : {is_include_file : true}
- tb.cpp
file_type : cppSource
targets:
sim:
default_tool : verilator
filesets : [rtl, tb]
toplevel : timer_thing
tools:
verilator:
verilator_options : [-trace]
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