olofk/define_test.v

## define_test.v
`default_nettype none
module m(output wire a, input wire b);
   assign `A = b;
endmodule

## define_test.ys
verilog_defines -DA=a
read_verilog define_test.v
synth_ice40 -top m -blif m.blif

## doesntwork.sh
yosys -p 'verilog_defines -DA=a; synth_ice40 -top m -blif m.blif' define_test.v

## works.sh
yosys -s define_test.ys
	`default_nettype none
	module m(output wire a, input wire b);
	assign `A = b;
	endmodule
	verilog_defines -DA=a
	read_verilog define_test.v
	synth_ice40 -top m -blif m.blif