serv_uart_rx.v

`default_nettype none
module serv_uart_rx
  (
   input wire 	    i_clk,

   input wire 	    i_wb_cyc,
   output reg [7:0] o_wb_rdt,
   output wire 	    o_wb_ack,

   input 	    i_rx);

   parameter CLOCK_DIV = 0;

   localparam CNT_WIDTH = $clog2(CLOCK_DIV)+1;

   reg [CNT_WIDTH-1:0] cnt;
   reg [4:0] 	       tickcnt;
   reg 		       running;

   wire 	       go       = !i_rx & !running;
   wire 	       tick     = cnt[CNT_WIDTH-1];
   wire 	       o_wb_ack = tickcnt[4] & tickcnt[0] & i_wb_cyc;
   wire 	       rx_en    = running & tick && !tickcnt[0];

   always @(posedge i_clk) begin
      cnt <= cnt -1;
      if (tick | go)
	cnt <= CLOCK_DIV;

      if (!running)
	tickcnt <= 4'b0;
      else if (tick)
	tickcnt <= tickcnt + 1;
      
      if (go)
	running <= 1'b1;
      else if (tickcnt[4] & tickcnt[2])
	running <= 1'b0;
      
      if (rx_en)
	o_wb_rdt <= {i_rx, o_wb_rdt[7:1]};
   end
endmodule