servant_1.0.2.eda.yml

dependencies:
  ::serv:1.0.2: []
  ::servant:1.0.2:
  - ::serv:1.0.2
files:
- core: ::serv:1.0.2
  file_type: verilogSource
  is_include_file: true
  name: ../src/serv_1.0.2/rtl/serv_params.vh
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_bufreg.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_alu.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_csr.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_ctrl.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_decode.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_immdec.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_mem_if.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_rf_if.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_rf_ram_if.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_rf_ram.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_state.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_top.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_rf_top.v
- core: ::servant:1.0.2
  file_type: user
  name: blinky.hex
- core: ::servant:1.0.2
  file_type: user
  name: zephyr_hello.hex
- core: ::servant:1.0.2
  file_type: verilogSource
  name: ../src/servant_1.0.2/servant/servant_clock_gen.v
- core: ::servant:1.0.2
  file_type: verilogSource
  name: ../src/servant_1.0.2/servant/servant_timer.v
- core: ::servant:1.0.2
  file_type: verilogSource
  name: ../src/servant_1.0.2/servant/servant_gpio.v
- core: ::servant:1.0.2
  file_type: verilogSource
  name: ../src/servant_1.0.2/servant/servant_arbiter.v
- core: ::servant:1.0.2
  file_type: verilogSource
  name: ../src/servant_1.0.2/servant/servant_mux.v
- core: ::servant:1.0.2
  file_type: verilogSource
  name: ../src/servant_1.0.2/servant/servant_ram.v
- core: ::servant:1.0.2
  file_type: verilogSource
  name: ../src/servant_1.0.2/servant/servant.v
- core: ::servant:1.0.2
  file_type: verilogSource
  name: ../src/servant_1.0.2/servant/servix_clock_gen.v
- core: ::servant:1.0.2
  file_type: verilogSource
  name: ../src/servant_1.0.2/servant/servix.v
- core: ::servant:1.0.2
  file_type: xdc
  name: ../src/servant_1.0.2/data/nexys_a7.xdc
hooks: {}
name: servant_1.0.2
parameters:
  RISCV_FORMAL:
    datatype: bool
    paramtype: vlogdefine
  SERV_CLEAR_RAM:
    datatype: bool
    paramtype: vlogdefine
  frequency:
    datatype: int
    default: 32
    description: PLL output frequency
    paramtype: vlogparam
  memfile:
    datatype: file
    description: Preload RAM with a hex file at compile-time
    paramtype: vlogparam
  memsize:
    datatype: int
    default: 8192
    description: Memory size in bytes for RAM (default 8kiB)
    paramtype: vlogparam
tool_options:
  vivado:
    part: xc7a100tcsg324-1
toplevel: servix
version: 0.2.1
vpi: []

subservient_0.1.0.eda.yml

dependencies:
  ::serv:1.0.2: []
  ::serving:1.0.2:
  - ::serv:1.0.2
  ::subservient:0.1.0:
  - ::serving:1.0.2
files:
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_bufreg.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_alu.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_csr.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_ctrl.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_decode.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_immdec.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_mem_if.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_rf_if.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_rf_ram_if.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_rf_ram.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_state.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_top.v
- core: ::serv:1.0.2
  file_type: verilogSource
  name: ../src/serv_1.0.2/rtl/serv_rf_top.v
- core: ::serving:1.0.2
  file_type: verilogSource
  name: ../src/serving_1.0.2/serving/serving_arbiter.v
- core: ::serving:1.0.2
  file_type: verilogSource
  name: ../src/serving_1.0.2/serving/serving_mux.v
- core: ::serving:1.0.2
  file_type: verilogSource
  name: ../src/serving_1.0.2/serving/serving_ram.v
- core: ::serving:1.0.2
  file_type: verilogSource
  name: ../src/serving_1.0.2/serving/serving.v
- core: ::subservient:0.1.0
  file_type: verilogSource
  name: ../src/subservient_0.1.0/rtl/subservient_rf_ram_if.v
- core: ::subservient:0.1.0
  file_type: verilogSource
  name: ../src/subservient_0.1.0/rtl/subservient_ram.v
- core: ::subservient:0.1.0
  file_type: verilogSource
  name: ../src/subservient_0.1.0/rtl/subservient_debug_switch.v
- core: ::subservient:0.1.0
  file_type: verilogSource
  name: ../src/subservient_0.1.0/rtl/subservient_core.v
- core: ::subservient:0.1.0
  file_type: verilogSource
  name: ../src/subservient_0.1.0/rtl/subservient_gpio.v
- core: ::subservient:0.1.0
  file_type: verilogSource
  name: ../src/subservient_0.1.0/rtl/subservient.v
- core: ::subservient:0.1.0
  file_type: tclSource
  name: ../src/subservient_0.1.0/data/params.tcl
hooks: {}
name: subservient_0.1.0
parameters:
  RISCV_FORMAL:
    datatype: bool
    paramtype: vlogdefine
  SERV_CLEAR_RAM:
    datatype: bool
    paramtype: vlogdefine
  memsize:
    datatype: int
    default: 1024
    description: Memory size in bytes for RAM (default 1kiB)
    paramtype: vlogparam
tool_options:
  openlane: {}
toplevel: subservient
version: 0.2.1
vpi: []

swervolf_0.7.4.eda.yml

dependencies:
  ::cdc_utils:0.1-r1: []
  ::jtag_vpi:0-r5: []
  ::simple_spi:1.6.1: []
  ::swervolf-intercon:0.7.4: []
  ::swervolf-swerv_default_config:0.7.4: []
  ::swervolf-version:0.7.4: []
  ::swervolf-wb_intercon:0.7.4: []
  ::swervolf:0.7.4:
  - chipsalliance.org:cores:SweRV_EH1:1.8
  - fusesoc:utils:generators:0.1.5
  - ::jtag_vpi:0-r5
  - pulp-platform.org::axi:0.25.0
  - ::simple_spi:1.6.1
  - ::uart16550:1.5.5-r1
  - ::vidbo:0
  - ::wb_intercon:1.2.2-r1
  ::uart16550:1.5.5-r1: []
  ::verilog-arbiter:0-r3: []
  ::vidbo:0: []
  ::wb_common:1.0.3: []
  ::wb_intercon:1.2.2-r1:
  - ::cdc_utils:0.1-r1
  - ::verilog-arbiter:0-r3
  - ::wb_common:1.0.3
  chipsalliance.org:cores:SweRV_EH1:1.8: []
  fusesoc:utils:generators:0.1.5: []
  pulp-platform.org::axi:0.25.0:
  - pulp-platform.org::common_cells:1.20.0
  pulp-platform.org::common_cells:1.20.0: []
files:
- core: ::swervolf-swerv_default_config:0.7.4
  file_type: systemVerilogSource
  name: config/common_defines.vh
- core: ::swervolf-swerv_default_config:0.7.4
  file_type: systemVerilogSource
  is_include_file: true
  name: config/pic_ctrl_verilator_unroll.sv
- core: ::swervolf-swerv_default_config:0.7.4
  file_type: systemVerilogSource
  is_include_file: true
  name: config/pic_map_auto.h
- core: ::cdc_utils:0.1-r1
  file_type: verilogSource
  name: ../src/cdc_utils_0.1-r1/rtl/verilog/sync2_pgen.v
- core: ::cdc_utils:0.1-r1
  file_type: verilogSource
  name: ../src/cdc_utils_0.1-r1/rtl/verilog/cc561.v
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  is_include_file: true
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/build.h
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  is_include_file: true
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/global.h
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/mem.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/pic_ctrl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/dma_ctrl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/ifu/ifu_aln_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/ifu/ifu_compress_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/ifu/ifu_ifc_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/ifu/ifu_bp_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/ifu/ifu_ic_mem.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/ifu/ifu_mem_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/ifu/ifu_iccm_mem.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/ifu/ifu.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/dec/dec_decode_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/dec/dec_gpr_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/dec/dec_ib_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/dec/dec_tlu_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/dec/dec_trigger.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/dec/dec.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/exu/exu_alu_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/exu/exu_mul_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/exu/exu_div_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/exu/exu.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lsu/lsu.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lsu/lsu_bus_buffer.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lsu/lsu_clkdomain.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lsu/lsu_addrcheck.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lsu/lsu_lsc_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lsu/lsu_stbuf.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lsu/lsu_bus_intf.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lsu/lsu_ecc.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lsu/lsu_dccm_mem.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lsu/lsu_dccm_ctl.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lsu/lsu_trigger.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/dbg/dbg.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/dmi/dmi_wrapper.v
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/dmi/dmi_jtag_to_core_sync.v
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/dmi/rvjtag_tap.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/mem_lib.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/ahb_to_axi4.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/axi4_to_ahb.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/swerv.sv
- core: chipsalliance.org:cores:SweRV_EH1:1.8
  file_type: systemVerilogSource
  name: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/swerv_wrapper.sv
- core: ::jtag_vpi:0-r5
  file_type: cSource
  name: ../src/jtag_vpi_0-r5/jtag_common.c
- core: ::jtag_vpi:0-r5
  file_type: cSource
  is_include_file: true
  name: ../src/jtag_vpi_0-r5/jtag_common.h
- core: ::jtag_vpi:0-r5
  file_type: cppSource
  name: ../src/jtag_vpi_0-r5/jtagServer.cpp
- core: ::jtag_vpi:0-r5
  file_type: cppSource
  is_include_file: true
  name: ../src/jtag_vpi_0-r5/jtagServer.h
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  include_path: ../src/pulp-platform.org__common_cells_1.20.0/include
  is_include_file: true
  name: ../src/pulp-platform.org__common_cells_1.20.0/include/common_cells/registers.svh
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/binary_to_gray.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/cb_filter_pkg.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/cdc_2phase.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/cf_math_pkg.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/clk_div.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/ecc_pkg.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/edge_propagator_tx.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/exp_backoff.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/gray_to_binary.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/isochronous_spill_register.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/lfsr.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/lfsr_16bit.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/lfsr_8bit.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/mv_filter.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/onehot_to_bin.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/plru_tree.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/rstgen_bypass.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/serial_deglitch.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/shift_reg.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_demux.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_filter.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_fork.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_intf.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_join.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_mux.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/sub_per_hash.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/sync.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/sync_wedge.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/unread.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/cb_filter.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/cdc_fifo_2phase.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/cdc_fifo_gray.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/counter.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/ecc_decode.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/ecc_encode.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/edge_detect.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/max_counter.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/rstgen.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_delay.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_fifo.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_fork_dynamic.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_xbar.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/fall_through_register.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/id_queue.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_to_mem.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_arbiter_flushable.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_omega_net.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/stream_arbiter.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/deprecated/clock_divider_counter.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/deprecated/find_first_one.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/deprecated/generic_LFSR_8bit.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/deprecated/generic_fifo.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/deprecated/prioarbiter.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/deprecated/pulp_sync.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/deprecated/pulp_sync_wedge.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/deprecated/rrarbiter.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/deprecated/clock_divider.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v1.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/edge_propagator.sv
- core: pulp-platform.org::common_cells:1.20.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__common_cells_1.20.0/src/edge_propagator_rx.sv
- core: ::simple_spi:1.6.1
  file_type: verilogSource
  name: ../src/simple_spi_1.6.1/rtl/verilog/fifo4.v
- core: ::simple_spi:1.6.1
  file_type: verilogSource
  name: ../src/simple_spi_1.6.1/rtl/verilog/simple_spi_top.v
- core: ::uart16550:1.5.5-r1
  file_type: verilogSource
  is_include_file: true
  name: ../src/uart16550_1.5.5-r1/rtl/verilog/uart_defines.v
- core: ::uart16550:1.5.5-r1
  file_type: verilogSource
  name: ../src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v
- core: ::uart16550:1.5.5-r1
  file_type: verilogSource
  name: ../src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v
- core: ::uart16550:1.5.5-r1
  file_type: verilogSource
  name: ../src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v
- core: ::uart16550:1.5.5-r1
  file_type: verilogSource
  name: ../src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v
- core: ::uart16550:1.5.5-r1
  file_type: verilogSource
  name: ../src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v
- core: ::uart16550:1.5.5-r1
  file_type: verilogSource
  name: ../src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v
- core: ::uart16550:1.5.5-r1
  file_type: verilogSource
  name: ../src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v
- core: ::uart16550:1.5.5-r1
  file_type: verilogSource
  name: ../src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v
- core: ::uart16550:1.5.5-r1
  file_type: verilogSource
  name: ../src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v
- core: ::verilog-arbiter:0-r3
  file_type: verilogSource
  name: ../src/verilog-arbiter_0-r3/src/arbiter.v
- core: ::vidbo:0
  file_type: cSource
  name: ../src/vidbo_0/src/vidbo.c
- core: ::vidbo:0
  file_type: cSource
  is_include_file: true
  name: ../src/vidbo_0/src/vidbo.h
- core: ::wb_common:1.0.3
  file_type: verilogSource
  is_include_file: true
  name: ../src/wb_common_1.0.3/wb_common_params.v
- core: ::wb_common:1.0.3
  file_type: verilogSource
  is_include_file: true
  name: ../src/wb_common_1.0.3/wb_common.v
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  include_path: ../src/pulp-platform.org__axi_0.25.0/include
  is_include_file: true
  name: ../src/pulp-platform.org__axi_0.25.0/include/axi/assign.svh
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  include_path: ../src/pulp-platform.org__axi_0.25.0/include
  is_include_file: true
  name: ../src/pulp-platform.org__axi_0.25.0/include/axi/typedef.svh
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_intf.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_burst_splitter.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_cdc.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_cut.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_delayer.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_dw_downsizer.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_dw_upsizer.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_isolate.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_join.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_lite_demux.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_lite_join.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_lite_mailbox.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_lite_mux.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_lite_regs.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_lite_to_apb.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_lite_to_axi.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_modify_address.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_serializer.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_dw_converter.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_multicut.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_to_axi_lite.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_lite_xbar.sv
- core: pulp-platform.org::axi:0.25.0
  file_type: systemVerilogSource
  name: ../src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv
- core: ::wb_intercon:1.2.2-r1
  file_type: verilogSource
  name: ../src/wb_intercon_1.2.2-r1/rtl/verilog/wb_cdc.v
- core: ::wb_intercon:1.2.2-r1
  file_type: verilogSource
  name: ../src/wb_intercon_1.2.2-r1/rtl/verilog/wb_arbiter.v
- core: ::wb_intercon:1.2.2-r1
  file_type: verilogSource
  name: ../src/wb_intercon_1.2.2-r1/rtl/verilog/wb_data_resize.v
- core: ::wb_intercon:1.2.2-r1
  file_type: verilogSource
  name: ../src/wb_intercon_1.2.2-r1/rtl/verilog/wb_mux.v
- core: ::swervolf:0.7.4
  file_type: systemVerilogSource
  name: ../src/swervolf_0.7.4/rtl/swerv_wrapper.sv
- core: ::swervolf:0.7.4
  file_type: systemVerilogSource
  name: ../src/swervolf_0.7.4/rtl/dpram64.v
- core: ::swervolf:0.7.4
  file_type: systemVerilogSource
  name: ../src/swervolf_0.7.4/rtl/axi2wb.v
- core: ::swervolf:0.7.4
  file_type: systemVerilogSource
  name: ../src/swervolf_0.7.4/rtl/wb_mem_wrapper.v
- core: ::swervolf:0.7.4
  file_type: systemVerilogSource
  name: ../src/swervolf_0.7.4/rtl/swervolf_syscon.v
- core: ::swervolf:0.7.4
  file_type: systemVerilogSource
  name: ../src/swervolf_0.7.4/rtl/swervolf_core.v
- core: ::swervolf:0.7.4
  file_type: user
  name: hello.vh
- core: ::swervolf:0.7.4
  file_type: verilogSource
  name: ../src/swervolf_0.7.4/rtl/axi_mem_wrapper.v
- core: ::swervolf:0.7.4
  file_type: systemVerilogSource
  name: ../src/swervolf_0.7.4/tb/swervolf_core_tb.v
- core: ::swervolf:0.7.4
  file_type: user
  name: bootloader.vh
- core: ::swervolf:0.7.4
  file_type: cppSource
  name: ../src/swervolf_0.7.4/tb/tb.cpp
- core: ::swervolf:0.7.4
  file_type: vlt
  name: ../src/swervolf_0.7.4/data/verilator_waiver.vlt
- core: ::swervolf-intercon:0.7.4
  file_type: systemVerilogSource
  name: ../src/swervolf-intercon_0.7.4/axi_intercon.v
- core: ::swervolf-intercon:0.7.4
  file_type: verilogSource
  is_include_file: true
  name: ../src/swervolf-intercon_0.7.4/axi_intercon.vh
- core: ::swervolf-wb_intercon:0.7.4
  file_type: verilogSource
  name: ../src/swervolf-wb_intercon_0.7.4/wb_intercon.v
- core: ::swervolf-wb_intercon:0.7.4
  file_type: verilogSource
  is_include_file: true
  name: ../src/swervolf-wb_intercon_0.7.4/wb_intercon.vh
hooks: {}
name: swervolf_0.7.4
parameters:
  SIMPRINT:
    datatype: bool
    default: true
    description: Enable simulation character output
    paramtype: vlogdefine
  VERSION_DIRTY:
    datatype: bool
    default: false
    paramtype: vlogdefine
  VERSION_MAJOR:
    datatype: int
    default: 0
    paramtype: vlogdefine
  VERSION_MINOR:
    datatype: int
    default: 7
    paramtype: vlogdefine
  VERSION_PATCH:
    datatype: int
    default: 4
    paramtype: vlogdefine
  VERSION_REV:
    datatype: int
    default: 3
    paramtype: vlogdefine
  VERSION_SHA:
    datatype: str
    default: 63c4b1dc
    paramtype: vlogdefine
  jtag_vpi_enable:
    datatype: bool
    description: Enable JTAG simulation server
    paramtype: plusarg
  ram_init_file:
    datatype: file
    default: /mnt/gentoo/home/olof/projects/swervolf/fusesoc_libraries/swervolf/sw/cnt.vh
    description: Verilog hex file to use as initial on-chip RAM contents
    paramtype: plusarg
  rom_init_file:
    datatype: file
    description: Verilog hex file to use as initial bootrom RAM contents
    paramtype: plusarg
  signature:
    datatype: file
    paramtype: plusarg
  timeout:
    datatype: int
    paramtype: plusarg
  vcd:
    datatype: bool
    description: Dump VCD
    paramtype: plusarg
tool_options:
  verilator:
    libs:
    - -lwebsockets
    verilator_options:
    - --trace
    - -Wno-fatal
toplevel: swervolf_core_tb
version: 0.2.1
vpi:
- include_dirs:
  - ../src/jtag_vpi_0-r5/
  libs: []
  name: jtag_vpi
  src_files:
  - ../src/jtag_vpi_0-r5/jtag_common.c
  - ../src/jtag_vpi_0-r5/jtag_vpi.c
  - ../src/jtag_vpi_0-r5/jtag_vpi.v