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@olofk
Created June 28, 2021 22:08
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module corescore_emitter_uart
#(
parameter clk_freq_hz = 0,
parameter baud_rate = 57600)
(
input wire i_clk,
input wire i_rst,
input wire [7:0] i_data,
input wire i_valid,
output reg o_ready,
output wire o_uart_tx);
localparam START_VALUE = clk_freq_hz/baud_rate;
localparam WIDTH = $clog2(START_VALUE);
reg [WIDTH:0] cnt;
reg [9:0] data;
assign o_uart_tx = data[0] | !(|data);
always @(posedge i_clk) begin
if (cnt[WIDTH] & !(|data))
o_ready <= 1'b1;
else if (i_valid & o_ready)
o_ready <= 1'b0;
if (o_ready | cnt[WIDTH])
cnt <= {1'b0,START_VALUE[WIDTH-1:0]};
else
cnt <= cnt-1;
if (cnt[WIDTH])
data <= {1'b0, data[9:1]};
else if (i_valid & o_ready)
data <= {1'b1, i_data, 1'b0};
end
endmodule
@bl0x
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bl0x commented Feb 28, 2023

This snippet seems unlicensed. What are the modalities of including derived works in a BSD-licensed project?
I've ported the code to Amaranth HDL and added the following note to the header:

# This module is designed after corescore_emitter_uart from Olof Kindgren
# https://gist.github.com/olofk/e91fba2572396f55525f8814f05fb33d

Code is here: learn-fpga-amaranth

@olofk
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olofk commented Feb 28, 2023

Good question. It looks like it ended up in CoreScore eventually, in which case Apache 2.0 would be the preferred license. Is that ok for you?

@bl0x
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bl0x commented Mar 2, 2023

Hi Olof,

I've modified the not a bit:

# This module is designed after corescore_emitter_uart by Olof Kindgren which
# is part of the corescore repository on github.
#
# https://github.com/olofk/corescore/blob/master/rtl/corescore_emitter_uart.v
#
# The original code is licensed under the Apache-2.0 license.
# A copy of this license file is included in this repository in the LICENSES
# directory.

Do you think that is OK?

@olofk
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olofk commented Mar 5, 2023

Yes. That's great. Thanks

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