gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/APU
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.2387 | 0.2386 | -0.0001 (-0.0586%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2478 | 0.2478 | -0.0000 (-0.0198%) ❗ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 10 | 11 | 1 (+10.0000%) ❗ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.6764 | 0.6760 | -0.0004 (-0.0661%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.3804 | 0.3803 | -0.0002 (-0.0457%) ❗ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 10 | 11 | 1 (+10.0000%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2387 | 0.2386 | -0.0001 (-0.0586%) ❗ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.6560 | 0.6555 | -0.0006 (-0.0864%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.3678 | 0.3676 | -0.0003 (-0.0691%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2429 | 0.2428 | -0.0001 (-0.0329%) ❗ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.6652 | 0.6647 | -0.0005 (-0.0750%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.3737 | 0.3734 | -0.0002 (-0.0608%) ❗ |
clock__skew__worst_hold | 0.6764 | 0.6760 | -0.0004 (-0.0661%) ⭕ |
power__internal__total | 0.0094 | 0.0094 | -0.0000 (-0.0028%) ⭕ |
power__switching__total | 0.0050 | 0.0049 | -0.0000 (-0.0504%) ⭕ |
power__total | 0.0144 | 0.0144 | -0.0000 (-0.0192%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.2478 | 0.2478 | -0.0000 (-0.0198%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.6764 | 0.6760 | -0.0004 (-0.0661%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.3804 | 0.3803 | -0.0002 (-0.0457%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.2387 | 0.2386 | -0.0001 (-0.0586%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.6560 | 0.6555 | -0.0006 (-0.0864%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.3678 | 0.3676 | -0.0003 (-0.0691%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.2429 | 0.2428 | -0.0001 (-0.0329%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.6652 | 0.6647 | -0.0005 (-0.0750%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.3737 | 0.3734 | -0.0002 (-0.0608%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 289916 | 289916 | 0 (0.0000%) ⭕ |
design__die__area | 316090 | 316090 | 0 (0.0000%) ⭕ |
design__instance__area | 110860 | 110860 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 174 | 174 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0016 | 0.0016 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 174 | 174 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 174 | 174 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 174 | 174 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 174 | 174 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 174 | 174 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 174 | 174 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 174 | 174 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 174 | 174 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 174 | 174 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/blink
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.0042 | -0.0042 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.0107 | -0.0107 | 0.0000 (0.0000%) ⭕ |
design__core__area | 6146.5600 | 6146.5600 | 0.0000 (0.0000%) ⭕ |
design__die__area | 10108.6000 | 10108.6000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 4151.1200 | 4151.1200 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0013 | 0.0013 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0056 | 0.0056 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0028 | 0.0028 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.0051 | -0.0051 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.0051 | -0.0051 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.0107 | -0.0107 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.0107 | -0.0107 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.0068 | -0.0068 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.0068 | -0.0068 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.0042 | -0.0042 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | -0.0042 | -0.0042 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.0089 | -0.0089 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.0089 | -0.0089 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.0057 | -0.0057 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.0057 | -0.0057 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.0046 | -0.0046 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.0046 | -0.0046 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.0097 | -0.0097 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.0097 | -0.0097 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.0062 | -0.0062 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.0062 | -0.0062 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/spm
Metric | Before | After | Delta |
---|---|---|---|
power__switching__total | 0.0023 | 0.0023 | 0.0000 (+0.0051%) ❗ |
power__total | 0.0098 | 0.0098 | 0.0000 (+0.0011%) ❗ |
power__internal__total | 0.0076 | 0.0076 | -0.0000 (-0.0001%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0126 | 0.0126 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0047 | 0.0047 | 0.0000 (0.0000%) ⭕ |
design__core__area | 22439.3000 | 22439.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 29881.6000 | 29881.6000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 12121.9000 | 12121.9000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0025 | 0.0025 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0118 | 0.0118 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.0049 | 0.0049 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.0049 | 0.0049 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.0126 | 0.0126 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.0126 | 0.0126 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.0073 | 0.0073 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.0073 | 0.0073 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.0047 | 0.0047 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.0047 | 0.0047 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.0116 | 0.0116 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.0116 | 0.0116 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.0068 | 0.0068 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.0068 | 0.0068 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.0047 | 0.0047 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.0047 | 0.0047 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.0120 | 0.0120 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.0120 | 0.0120 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.0069 | 0.0069 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.0069 | 0.0069 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.0293 | -0.0293 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.0809 | -0.0809 | 0.0000 (0.0000%) ⭕ |
design__core__area | 63502.7000 | 63502.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 76043.3000 | 76043.3000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 33015.8000 | 33015.8000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0014 | 0.0014 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0060 | 0.0060 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0160 | 0.0160 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0057 | 0.0057 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0216 | 0.0216 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.0309 | -0.0309 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.0309 | -0.0309 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.0809 | -0.0809 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.0809 | -0.0809 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.0466 | -0.0466 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.0466 | -0.0466 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.0293 | -0.0293 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | -0.0293 | -0.0293 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.0752 | -0.0752 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.0752 | -0.0752 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.0436 | -0.0436 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.0436 | -0.0436 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.0298 | -0.0298 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.0298 | -0.0298 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.0778 | -0.0778 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.0778 | -0.0778 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.0447 | -0.0447 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.0447 | -0.0447 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb_cdc_core
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.7052 | 0.7052 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2488 | 0.2488 | 0.0000 (0.0000%) ⭕ |
design__core__area | 161215 | 161215 | 0 (0.0000%) ⭕ |
design__die__area | 181472 | 181472 | 0 (0.0000%) ⭕ |
design__instance__area | 74202.2000 | 74202.2000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 90 | 90 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0019 | 0.0019 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0144 | 0.0144 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0560 | 0.0560 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0205 | 0.0205 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0765 | 0.0765 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 335 | 335 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 368 | 368 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.2570 | 0.2570 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2570 | 0.2570 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 90 | 90 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.7052 | 0.7052 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.7052 | 0.7052 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 90 | 90 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 116 | 116 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 127 | 127 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.3955 | 0.3955 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.3955 | 0.3955 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 90 | 90 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.2488 | 0.2488 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2488 | 0.2488 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 90 | 90 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.6848 | 0.6848 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.6848 | 0.6848 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 90 | 90 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 106 | 106 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 117 | 117 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.3834 | 0.3834 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.3834 | 0.3834 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 90 | 90 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.2525 | 0.2525 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2525 | 0.2525 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 90 | 90 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.6941 | 0.6941 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.6941 | 0.6941 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 90 | 90 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 113 | 113 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 124 | 124 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.3889 | 0.3889 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.3889 | 0.3889 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 90 | 90 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/wbqspiflash
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | 0.5317 | 0.5351 | 0.0034 (+0.6466%) ❗ |
ir__drop__worst | 0.0450 | 0.0452 | 0.0002 (+0.4444%) ❗ |
power__internal__total | 0.1154 | 0.1154 | 0.0000 (+0.0301%) ❗ |
power__total | 0.2004 | 0.2004 | 0.0000 (+0.0153%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.1911 | 0.1924 | 0.0013 (+0.6650%) ❗ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.5317 | 0.5351 | 0.0034 (+0.6466%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.2963 | 0.2983 | 0.0019 (+0.6567%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.1871 | 0.1879 | 0.0008 (+0.4485%) ❗ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.5212 | 0.5234 | 0.0022 (+0.4261%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.2901 | 0.2914 | 0.0013 (+0.4398%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.1889 | 0.1899 | 0.0010 (+0.5484%) ❗ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.5259 | 0.5287 | 0.0027 (+0.5227%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.2929 | 0.2945 | 0.0016 (+0.5384%) ❗ |
clock__skew__worst_setup | 0.1871 | 0.1879 | 0.0008 (+0.4485%) ⭕ |
power__switching__total | 0.0851 | 0.0851 | -0.0000 (-0.0048%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.1911 | 0.1924 | 0.0013 (+0.6650%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.5317 | 0.5351 | 0.0034 (+0.6466%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2963 | 0.2983 | 0.0019 (+0.6567%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.1871 | 0.1879 | 0.0008 (+0.4485%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.5212 | 0.5234 | 0.0022 (+0.4261%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2901 | 0.2914 | 0.0013 (+0.4398%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.1889 | 0.1899 | 0.0010 (+0.5484%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.5259 | 0.5287 | 0.0027 (+0.5227%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2929 | 0.2945 | 0.0016 (+0.5384%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 94345.3000 | 94345.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 109560 | 109560 | 0 (0.0000%) ⭕ |
design__instance__area | 67361.9000 | 67361.9000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0131 | 0.0131 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9500 | 4.9500 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 444 | 444 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 446 | 446 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 148 | 148 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 149 | 149 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 148 | 148 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 148 | 148 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 148 | 148 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 149 | 149 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/zipdiv
Metric | Before | After | Delta |
---|---|---|---|
power__internal__total | 0.0195 | 0.0195 | 0.0000 (+0.0033%) ❗ |
power__switching__total | 0.0105 | 0.0105 | 0.0000 (+0.0257%) ❗ |
power__total | 0.0300 | 0.0300 | 0.0000 (+0.0111%) ❗ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.1287 | 0.1287 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0452 | 0.0452 | 0.0000 (0.0000%) ⭕ |
design__core__area | 73310.9000 | 73310.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 86150 | 86150 | 0 (0.0000%) ⭕ |
design__instance__area | 35410.8000 | 35410.8000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0019 | 0.0019 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0092 | 0.0092 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 201 | 201 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 201 | 201 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.0506 | 0.0506 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.0506 | 0.0506 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.1287 | 0.1287 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.1287 | 0.1287 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 67 | 67 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 67 | 67 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.0749 | 0.0749 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.0749 | 0.0749 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.0452 | 0.0452 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.0452 | 0.0452 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.1169 | 0.1169 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.1169 | 0.1169 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 67 | 67 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 67 | 67 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.0675 | 0.0675 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.0675 | 0.0675 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.0477 | 0.0477 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.0477 | 0.0477 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.1223 | 0.1223 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.1223 | 0.1223 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 67 | 67 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 67 | 67 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.0709 | 0.0709 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.0709 | 0.0709 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/APU
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.1465 | 0.3730 | 0.5195 (-354.6359%) ❗ |
design__max_fanout_violation__count | 37 | 43 | 6 (+16.2162%) ❗ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (+0.7042%) ❗ |
ir__drop__worst | 0.0011 | 0.0012 | 0.0000 (+0.8772%) ❗ |
power__switching__total | 0.0012 | 0.0012 | 0.0000 (+0.3763%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1578 | 0.1515 | 0.3094 (-196.0135%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 37 | 43 | 6 (+16.2162%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.3825 | 0.3730 | 0.7555 (-197.5238%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 37 | 43 | 6 (+16.2162%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2261 | 0.2185 | 0.4446 (-196.6393%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 37 | 43 | 6 (+16.2162%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.1465 | 0.1403 | 0.2868 (-195.7881%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 37 | 43 | 6 (+16.2162%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.3628 | 0.3519 | 0.7147 (-196.9905%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 37 | 43 | 6 (+16.2162%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2116 | 0.2043 | 0.4158 (-196.5453%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 37 | 43 | 6 (+16.2162%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1517 | 0.1449 | 0.2966 (-195.5636%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 37 | 43 | 6 (+16.2162%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.3724 | 0.3619 | 0.7343 (-197.1617%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 37 | 43 | 6 (+16.2162%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2187 | 0.2107 | 0.4294 (-196.3316%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 37 | 43 | 6 (+16.2162%) ❗ |
antenna__violating__pins | 5 | 3 | -2 (-40.0000%) ⭕ |
clock__skew__worst_setup | -0.3825 | 0.1403 | 0.5228 (-136.6862%) ⭕ |
design__instance__area | 32932.8000 | 32926.6000 | -6.2000 (-0.0188%) ⭕ |
design__max_slew_violation__count | 57 | 33 | -24 (-42.1053%) ⭕ |
power__internal__total | 0.0021 | 0.0021 | -0.0000 (-0.4267%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-0.5254%) ⭕ |
power__total | 0.0033 | 0.0033 | -0.0000 (-0.1394%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.1578 | 0.1515 | 0.3094 (-196.0135%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.3825 | 0.3730 | 0.7555 (-197.5238%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 57 | 33 | -24 (-42.1053%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.2261 | 0.2185 | 0.4446 (-196.6393%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.1465 | 0.1403 | 0.2868 (-195.7881%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.3628 | 0.3519 | 0.7147 (-196.9905%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 21 | 6 | -15 (-71.4286%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.2116 | 0.2043 | 0.4158 (-196.5453%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.1517 | 0.1449 | 0.2966 (-195.5636%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.3724 | 0.3619 | 0.7343 (-197.1617%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 34 | 17 | -17 (-50.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.2187 | 0.2107 | 0.4294 (-196.3316%) ⭕ |
antenna__violating__nets | 3 | 3 | 0 (0.0000%) ⭕ |
design__core__area | 86482.9000 | 86482.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 96822.9000 | 96822.9000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_GPIO
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | 0.0009 | 0.0015 | 0.0006 (+65.4267%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0009 | 0.0015 | 0.0006 (+65.4267%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0008 | 0.0014 | 0.0006 (+65.5660%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0009 | 0.0015 | 0.0006 (+65.6600%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0003 | 0.0003 | 0.0001 (+28.0443%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0003 | 0.0003 | 0.0001 (+27.0916%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0003 | 0.0003 | 0.0001 (+27.5472%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0004 | 0.0006 | 0.0002 (+42.4096%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0004 | 0.0005 | 0.0002 (+42.9319%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0004 | 0.0006 | 0.0002 (+42.4691%) ❗ |
clock__skew__worst_setup | 0.0003 | 0.0003 | 0.0001 (+27.0916%) ⭕ |
power__internal__total | 0.0002 | 0.0002 | -0.0000 (-0.0063%) ⭕ |
power__switching__total | 0.0001 | 0.0001 | -0.0000 (-0.2352%) ⭕ |
power__total | 0.0003 | 0.0003 | -0.0000 (-0.0759%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0009 | 0.0015 | 0.0006 (+65.4267%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0008 | 0.0014 | 0.0006 (+65.5660%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0009 | 0.0015 | 0.0006 (+65.6600%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0003 | 0.0003 | 0.0001 (+28.0443%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0003 | 0.0003 | 0.0001 (+27.0916%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0003 | 0.0003 | 0.0001 (+27.5472%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0004 | 0.0006 | 0.0002 (+42.4096%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0004 | 0.0005 | 0.0002 (+42.9319%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0004 | 0.0006 | 0.0002 (+42.4691%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 1726.6600 | 1726.6600 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2852.0900 | 2852.0900 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 1465.1600 | 1465.1600 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_PSRAM_CTRL_V2
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | 0.0110 | 0.0110 | 0.0000 (+0.0817%) ❗ |
clock__skew__worst_setup | -0.0063 | -0.0066 | -0.0003 (+5.0967%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0051 | -0.0054 | -0.0106 (-205.6519%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0110 | 0.0110 | 0.0000 (+0.0817%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0063 | -0.0066 | -0.0003 (+5.0967%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0046 | 0.0048 | 0.0002 (+4.1874%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0098 | 0.0098 | 0.0000 (+0.0714%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0055 | 0.0059 | 0.0003 (+5.4785%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0047 | -0.0049 | -0.0096 (-203.6183%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0102 | 0.0102 | 0.0000 (+0.0688%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0057 | -0.0059 | -0.0116 (-204.5239%) ❗ |
ir__drop__worst | 0.0017 | 0.0016 | -0.0000 (-0.6024%) ⭕ |
power__internal__total | 0.0010 | 0.0010 | -0.0000 (-0.0012%) ⭕ |
power__switching__total | 0.0011 | 0.0011 | -0.0000 (-0.1104%) ⭕ |
power__total | 0.0022 | 0.0022 | -0.0000 (-0.0585%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0051 | -0.0054 | -0.0106 (-205.6519%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0110 | 0.0110 | 0.0000 (+0.0817%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0063 | -0.0066 | -0.0003 (+5.0967%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0046 | 0.0048 | 0.0002 (+4.1874%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0098 | 0.0098 | 0.0000 (+0.0714%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0055 | 0.0059 | 0.0003 (+5.4785%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0047 | -0.0049 | -0.0096 (-203.6183%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0102 | 0.0102 | 0.0000 (+0.0688%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0057 | -0.0059 | -0.0116 (-204.5239%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 7136.8400 | 7136.8400 | 0.0000 (0.0000%) ⭕ |
design__die__area | 10255.3000 | 10255.3000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 5636.6600 | 5636.6600 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 108 | 108 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 36 | 36 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 36 | 36 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 36 | 36 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_TCC32
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0148 | -0.0138 | 0.0010 (-6.8861%) ❗ |
clock__skew__worst_setup | -0.0311 | -0.0336 | -0.0025 (+7.9178%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0161 | -0.0152 | 0.0009 (-5.4693%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0311 | -0.0336 | -0.0025 (+7.9178%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0202 | -0.0195 | 0.0007 (-3.6876%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0148 | -0.0138 | 0.0010 (-6.8861%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0293 | -0.0309 | -0.0016 (+5.3193%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0190 | -0.0180 | 0.0010 (-5.0999%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0154 | -0.0143 | 0.0011 (-7.0223%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0305 | -0.0325 | -0.0020 (+6.5202%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0196 | -0.0187 | 0.0009 (-4.4175%) ❗ |
power__internal__total | 0.0012 | 0.0012 | -0.0000 (-0.0068%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-0.0842%) ⭕ |
power__switching__total | 0.0009 | 0.0009 | -0.0000 (-0.1993%) ⭕ |
power__total | 0.0020 | 0.0020 | -0.0000 (-0.0889%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0161 | -0.0152 | 0.0009 (-5.4693%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0311 | -0.0336 | -0.0025 (+7.9178%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0202 | -0.0195 | 0.0007 (-3.6876%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0148 | -0.0138 | 0.0010 (-6.8861%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0293 | -0.0309 | -0.0016 (+5.3193%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0190 | -0.0180 | 0.0010 (-5.0999%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0154 | -0.0143 | 0.0011 (-7.0223%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0305 | -0.0325 | -0.0020 (+6.5202%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0196 | -0.0187 | 0.0009 (-4.4175%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 11911.4000 | 11911.4000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 15858.6000 | 15858.6000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 8951.0800 | 8951.0800 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0025 | 0.0025 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_UART
Metric | Before | After | Delta |
---|---|---|---|
timing__setup_vio__count | 32 | 29 | -3 (-9.3750%) |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 12 | 11 | -1 (-8.3333%) |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 12 | 10 | -2 (-16.6667%) |
clock__skew__worst_setup | -0.0739 | -0.0762 | -0.0023 (+3.0471%) ❗ |
power__internal__total | 0.0033 | 0.0033 | 0.0000 (+0.0016%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0375 | -0.0366 | 0.0009 (-2.5083%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0739 | -0.0762 | -0.0023 (+3.0471%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0491 | -0.0493 | -0.0003 (+0.5481%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0314 | -0.0334 | -0.0020 (+6.3111%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0662 | -0.0690 | -0.0028 (+4.2820%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0424 | -0.0447 | -0.0023 (+5.3859%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0330 | -0.0352 | -0.0022 (+6.7887%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0692 | -0.0729 | -0.0037 (+5.3163%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0441 | -0.0471 | -0.0031 (+6.9456%) ❗ |
antenna__violating__nets | 1 | 0 | -1 (-100.0000%) ⭕ |
antenna__violating__pins | 1 | 0 | -1 (-100.0000%) ⭕ |
clock__skew__worst_hold | -0.0314 | -0.0334 | -0.0020 (+6.3111%) ⭕ |
ir__drop__worst | 0.0034 | 0.0034 | -0.0000 (-0.5900%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-0.0181%) ⭕ |
power__switching__total | 0.0016 | 0.0016 | -0.0000 (-0.1085%) ⭕ |
power__total | 0.0048 | 0.0048 | -0.0000 (-0.0338%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0375 | -0.0366 | 0.0009 (-2.5083%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0739 | -0.0762 | -0.0023 (+3.0471%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0491 | -0.0493 | -0.0003 (+0.5481%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0314 | -0.0334 | -0.0020 (+6.3111%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0662 | -0.0690 | -0.0028 (+4.2820%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0424 | -0.0447 | -0.0023 (+5.3859%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0330 | -0.0352 | -0.0022 (+6.7887%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0692 | -0.0729 | -0.0037 (+5.3163%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0441 | -0.0471 | -0.0031 (+6.9456%) ⭕ |
design__core__area | 24176.9000 | 24176.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 29791.4000 | 29791.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 20693.6000 | 20693.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_CLK_RST
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.7528 | -0.7528 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -2.6753 | -2.6753 | 0.0000 (0.0000%) ⭕ |
design__core__area | 9240.1100 | 9240.1100 | 0.0000 (0.0000%) ⭕ |
design__die__area | 12880.8000 | 12880.8000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 5172.4600 | 5172.4600 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 132 | 132 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.7529 | -0.7529 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.7465 | -0.7465 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -2.6803 | -2.6803 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -2.6753 | -2.6753 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 132 | 132 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -1.4381 | -1.4381 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -1.4353 | -1.4353 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.7528 | -0.7528 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.7465 | -0.7465 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -2.6573 | -2.6573 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -2.6523 | -2.6523 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 132 | 132 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -1.4331 | -1.4331 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -1.4303 | -1.4303 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.7571 | -0.7571 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.7507 | -0.7507 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -2.6737 | -2.6737 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -2.6687 | -2.6687 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 132 | 132 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -1.4401 | -1.4401 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -1.4373 | -1.4373 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_DMAC_AHBL
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 1.0411 | 1.0408 | -0.0003 (-0.0320%) ❗ |
power__internal__total | 0.0012 | 0.0012 | 0.0000 (+0.0063%) ❗ |
power__switching__total | 0.0005 | 0.0005 | 0.0000 (+0.1592%) ❗ |
power__total | 0.0018 | 0.0018 | 0.0000 (+0.0525%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 1.0782 | 1.0767 | -0.0015 (-0.1351%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 1.6764 | 1.6746 | -0.0018 (-0.1099%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.5886 | 0.5886 | 0.0000 (+0.0053%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 1.0411 | 1.0408 | -0.0003 (-0.0320%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 1.7788 | 1.7795 | 0.0007 (+0.0397%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 3.0811 | 3.0803 | -0.0007 (-0.0239%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.9202 | 0.9206 | 0.0003 (+0.0339%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 1.6145 | 1.6139 | -0.0006 (-0.0353%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 1.0600 | 1.0595 | -0.0005 (-0.0471%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 1.8111 | 1.8119 | 0.0009 (+0.0481%) ❗ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 3 | 3 ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.9382 | 0.9383 | 0.0002 (+0.0194%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 1.6457 | 1.6448 | -0.0008 (-0.0510%) ❗ |
clock__skew__worst_hold | 1.8445 | 1.8437 | -0.0008 (-0.0451%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.6141 | 0.6129 | -0.0012 (-0.1952%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 1.8445 | 1.8437 | -0.0008 (-0.0451%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 3.1888 | 3.1948 | 0.0060 (+0.1886%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.9573 | 0.9563 | -0.0010 (-0.1062%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.6009 | 0.6008 | -0.0001 (-0.0138%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 3.1339 | 3.1379 | 0.0040 (+0.1277%) ⭕ |
antenna__violating__nets | 2 | 2 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 2 | 2 | 0 (0.0000%) ⭕ |
design__core__area | 19398.6000 | 19398.6000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 24435.4000 | 24435.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 15175.8000 | 15175.8000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0020 | 0.0020 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 89 | 89 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 31 | 31 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 29 | 29 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 9 | 9 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 29 | 29 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_SPI_XIP_CACHE
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | 0.1637 | 0.1642 | 0.0005 (+0.3287%) ❗ |
clock__skew__worst_setup | 0.0620 | -0.1489 | -0.2109 (-340.1603%) ❗ |
design__max_fanout_violation__count | 217 | 226 | 9 (+4.1475%) ❗ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (+0.2500%) ❗ |
ir__drop__worst | 0.0019 | 0.0019 | 0.0000 (+1.6043%) ❗ |
power__internal__total | 0.0148 | 0.0148 | 0.0000 (+0.0035%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.0001%) ❗ |
power__switching__total | 0.0066 | 0.0066 | 0.0000 (+0.0751%) ❗ |
power__total | 0.0214 | 0.0214 | 0.0000 (+0.0256%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0776 | -0.0967 | -0.1744 (-224.5878%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 217 | 226 | 9 (+4.1475%) ❗ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 8 | 11 | 3 (+37.5000%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.1637 | 0.1642 | 0.0005 (+0.3287%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 217 | 226 | 9 (+4.1475%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.1051 | -0.1195 | -0.2246 (-213.7489%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 217 | 226 | 9 (+4.1475%) ❗ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 114 | 116 | 2 (+1.7544%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0620 | -0.0614 | -0.1234 (-199.0501%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 217 | 226 | 9 (+4.1475%) ❗ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.1376 | -0.1394 | -0.2770 (-201.3375%) ❗ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 7 | 8 | 1 (+14.2857%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 217 | 226 | 9 (+4.1475%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0849 | -0.0848 | -0.1697 (-199.8022%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 217 | 226 | 9 (+4.1475%) ❗ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 8 | 14 | 6 (+75.0000%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0666 | -0.0742 | -0.1408 (-211.4569%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 217 | 226 | 9 (+4.1475%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.1470 | -0.1489 | -0.2959 (-201.3302%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 217 | 226 | 9 (+4.1475%) ❗ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 296 | 298 | 2 (+0.6757%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0916 | -0.0946 | -0.1862 (-203.2328%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 217 | 226 | 9 (+4.1475%) ❗ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 30 | 43 | 13 (+43.3333%) ❗ |
antenna__violating__nets | 28 | 26 | -2 (-7.1429%) ⭕ |
antenna__violating__pins | 37 | 32 | -5 (-13.5135%) ⭕ |
design__max_slew_violation__count | 345 | 317 | -28 (-8.1159%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0776 | -0.0967 | -0.1744 (-224.5878%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 31 | 29 | -2 (-6.4516%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.1637 | 0.1642 | 0.0005 (+0.3287%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 345 | 317 | -28 (-8.1159%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.1051 | -0.1195 | -0.2246 (-213.7489%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 30 | 29 | -1 (-3.3333%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0620 | -0.0614 | -0.1234 (-199.0501%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.1376 | -0.1394 | -0.2770 (-201.3375%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 274 | 262 | -12 (-4.3796%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0849 | -0.0848 | -0.1697 (-199.8022%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0666 | -0.0742 | -0.1408 (-211.4569%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 19 | 18 | -1 (-5.2632%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 4 | 3 | -1 (-25.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.1470 | -0.1489 | -0.2959 (-201.3302%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 21 | 19 | -2 (-9.5238%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0916 | -0.0946 | -0.1862 (-203.2328%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 19 | 18 | -1 (-5.2632%) ⭕ |
design__core__area | 175921 | 175921 | 0 (0.0000%) ⭕ |
design__die__area | 190438 | 190438 | 0 (0.0000%) ⭕ |
design__instance__area | 147036 | 147036 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 33 | 33 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 96 | 96 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 33 | 33 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 6 | 6 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 6 | 6 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_user_project_wrapper
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -3.1920 | -3.1920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.1992 | 0.1992 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 656000 | 656000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0094 | 0.0094 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0128 | 0.0128 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.2127 | -3.2127 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2206 | 0.2206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.5492 | -3.5492 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.5638 | 0.5638 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.3170 | -3.3170 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.3268 | 0.3268 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.1920 | -3.1920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1992 | 0.1992 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.5018 | -3.5018 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.5148 | 0.5148 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.2862 | -3.2862 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2955 | 0.2955 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.2007 | -3.2007 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2085 | 0.2085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.5238 | -3.5238 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.5379 | 0.5379 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.2998 | -3.2998 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.3097 | 0.3097 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/blink
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0056 | 0.0056 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0024 | 0.0024 | 0.0000 (0.0000%) ⭕ |
design__core__area | 2387.2900 | 2387.2900 | 0.0000 (0.0000%) ⭕ |
design__die__area | 4273.3200 | 4273.3200 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 1393.8400 | 1393.8400 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0036 | 0.0036 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0036 | 0.0036 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0056 | 0.0056 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0056 | 0.0056 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0041 | 0.0041 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0041 | 0.0041 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0024 | 0.0024 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0024 | 0.0024 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0046 | 0.0046 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0046 | 0.0046 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0029 | 0.0029 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0029 | 0.0029 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0027 | 0.0027 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0027 | 0.0027 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0049 | 0.0049 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0049 | 0.0049 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0032 | 0.0032 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0032 | 0.0032 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/caravel_upw
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 1080000 | 1080000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 15 | 15 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/gcd
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 5 | 5 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 5 | 5 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0229 | 0.0229 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0105 | 0.0105 | 0.0000 (0.0000%) ⭕ |
design__core__area | 67039.3000 | 67039.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 78425.2000 | 78425.2000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 4513.0800 | 4513.0800 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0126 | 0.0126 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0126 | 0.0126 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0229 | 0.0229 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0229 | 0.0229 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0152 | 0.0152 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0152 | 0.0152 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0105 | 0.0105 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0105 | 0.0105 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0204 | 0.0204 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0204 | 0.0204 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0132 | 0.0132 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0132 | 0.0132 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0110 | 0.0110 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0110 | 0.0110 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0212 | 0.0212 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0212 | 0.0212 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/inverter
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 1051.0100 | 1051.0100 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
design__instance__area | 18.7680 | 18.7680 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/io_placer
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/manual_macro_placement_test
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
design__core__area | 80146.9000 | 80146.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 90000 | 90000 | 0 (0.0000%) ⭕ |
design__instance__area | 23795.8000 | 23795.8000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0354 | 0.0354 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0354 | 0.0354 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0143 | 0.0143 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0143 | 0.0143 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0140 | 0.0140 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0140 | 0.0140 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0202 | 0.0202 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0202 | 0.0202 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0193 | 0.0193 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0193 | 0.0193 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0198 | 0.0198 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0198 | 0.0198 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/s44
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | -0.0212 | -0.0214 | -0.0001 (+0.6077%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0108 | -0.0109 | -0.0001 (+0.5813%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0212 | -0.0214 | -0.0001 (+0.6077%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0141 | -0.0142 | -0.0001 (+0.6157%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0103 | -0.0103 | -0.0000 (+0.4189%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0197 | -0.0198 | -0.0001 (+0.4513%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0135 | -0.0136 | -0.0001 (+0.4432%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0107 | -0.0107 | -0.0001 (+0.4872%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0206 | -0.0207 | -0.0001 (+0.5184%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0139 | -0.0140 | -0.0001 (+0.5244%) ❗ |
clock__skew__worst_hold | -0.0103 | -0.0103 | -0.0000 (+0.4189%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | -0.0000 (-0.0009%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | -0.0000 (-0.0309%) ⭕ |
power__total | 0.0001 | 0.0001 | -0.0000 (-0.0088%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0108 | -0.0109 | -0.0001 (+0.5813%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0212 | -0.0214 | -0.0001 (+0.6077%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0141 | -0.0142 | -0.0001 (+0.6157%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0103 | -0.0103 | -0.0000 (+0.4189%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0197 | -0.0198 | -0.0001 (+0.4513%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0135 | -0.0136 | -0.0001 (+0.4432%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0107 | -0.0107 | -0.0001 (+0.4872%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0206 | -0.0207 | -0.0001 (+0.5184%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0139 | -0.0140 | -0.0001 (+0.5244%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 36347.4000 | 36347.4000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 43079.4000 | 43079.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 2536.1800 | 2536.1800 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/spm
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | -0.0145 | -0.0145 | -0.0000 (+0.1799%) ❗ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (+0.0019%) ❗ |
power__total | 0.0011 | 0.0011 | 0.0000 (+0.0006%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0078 | -0.0078 | -0.0000 (+0.1416%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0145 | -0.0145 | -0.0000 (+0.1799%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0066 | -0.0066 | -0.0000 (+0.0605%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0126 | -0.0126 | -0.0000 (+0.0953%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0082 | -0.0082 | -0.0000 (+0.0733%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0134 | -0.0134 | -0.0000 (+0.1272%) ❗ |
clock__skew__worst_hold | -0.0066 | -0.0066 | -0.0000 (+0.0605%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0078 | -0.0078 | -0.0000 (+0.1416%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0145 | -0.0145 | -0.0000 (+0.1799%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0066 | -0.0066 | -0.0000 (+0.0605%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0126 | -0.0126 | -0.0000 (+0.0953%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0082 | -0.0082 | -0.0000 (+0.0733%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0134 | -0.0134 | -0.0000 (+0.1272%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 8092.7600 | 8092.7600 | 0.0000 (0.0000%) ⭕ |
design__die__area | 11327.4000 | 11327.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 3595.9500 | 3595.9500 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0013 | 0.0013 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0099 | -0.0099 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0099 | -0.0099 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0070 | -0.0070 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0070 | -0.0070 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0088 | -0.0088 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0088 | -0.0088 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/test_sram_macro
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.3038 | -0.2838 | 0.0201 (-6.6026%) ❗ |
design__max_slew_violation__count | 160 | 166 | 6 (+3.7500%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.3580 | -0.3347 | 0.0232 (-6.4861%) ❗ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 14 | 15 | 1 (+7.1429%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.8233 | -0.7573 | 0.0660 (-8.0136%) ❗ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 160 | 166 | 6 (+3.7500%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.5234 | -0.4886 | 0.0348 (-6.6407%) ❗ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 14 | 15 | 1 (+7.1429%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.3038 | -0.2838 | 0.0201 (-6.6026%) ❗ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 11 | 12 | 1 (+9.0909%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.6972 | -0.6423 | 0.0549 (-7.8690%) ❗ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 118 | 128 | 10 (+8.4746%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.4410 | -0.4113 | 0.0298 (-6.7489%) ❗ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 11 | 12 | 1 (+9.0909%) ❗ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 75 | 78 | 3 (+4.0000%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.3322 | -0.3117 | 0.0205 (-6.1638%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.7628 | -0.7068 | 0.0560 (-7.3437%) ❗ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 133 | 136 | 3 (+2.2556%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.4801 | -0.4541 | 0.0259 (-5.4047%) ❗ |
clock__skew__worst_setup | -0.8233 | -0.7573 | 0.0660 (-8.0136%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | -0.0000 (-1.6026%) ⭕ |
ir__drop__worst | 0.0005 | 0.0004 | -0.0000 (-4.3478%) ⭕ |
power__internal__total | 0.0018 | 0.0018 | -0.0000 (-0.0008%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-0.0001%) ⭕ |
power__switching__total | 0.0002 | 0.0002 | -0.0000 (-3.4658%) ⭕ |
power__total | 0.0021 | 0.0020 | -0.0000 (-0.3963%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.3580 | -0.3347 | 0.0232 (-6.4861%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 43 | 36 | -7 (-16.2791%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.8233 | -0.7573 | 0.0660 (-8.0136%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.5234 | -0.4886 | 0.0348 (-6.6407%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 105 | 101 | -4 (-3.8095%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.3038 | -0.2838 | 0.0201 (-6.6026%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.6972 | -0.6423 | 0.0549 (-7.8690%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.4410 | -0.4113 | 0.0298 (-6.7489%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.3322 | -0.3117 | 0.0205 (-6.1638%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.7628 | -0.7068 | 0.0560 (-7.3437%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.4801 | -0.4541 | 0.0259 (-5.4047%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 100 | 91 | -9 (-9.0000%) ⭕ |
antenna__violating__nets | 35 | 35 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 36 | 36 | 0 (0.0000%) ⭕ |
design__core__area | 906252 | 906252 | 0 (0.0000%) ⭕ |
design__die__area | 937500 | 937500 | 0 (0.0000%) ⭕ |
design__instance__area | 395875 | 395875 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 5666674 | 5666674 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 26 | 26 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 26 | 26 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0296 | -0.0290 | 0.0005 (-1.7687%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0350 | -0.0341 | 0.0008 (-2.3341%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0618 | -0.0603 | 0.0016 (-2.5424%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0448 | -0.0438 | 0.0011 (-2.3774%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0296 | -0.0290 | 0.0005 (-1.7687%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0551 | -0.0540 | 0.0011 (-1.9208%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0386 | -0.0379 | 0.0007 (-1.8141%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0312 | -0.0306 | 0.0006 (-1.9285%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0575 | -0.0563 | 0.0012 (-2.0866%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0406 | -0.0398 | 0.0008 (-1.9696%) ❗ |
clock__skew__worst_setup | -0.0618 | -0.0603 | 0.0016 (-2.5424%) ⭕ |
power__internal__total | 0.0010 | 0.0010 | -0.0000 (-0.0015%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | -0.0000 (-0.0860%) ⭕ |
power__total | 0.0014 | 0.0014 | -0.0000 (-0.0264%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0350 | -0.0341 | 0.0008 (-2.3341%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0618 | -0.0603 | 0.0016 (-2.5424%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0448 | -0.0438 | 0.0011 (-2.3774%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0296 | -0.0290 | 0.0005 (-1.7687%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0551 | -0.0540 | 0.0011 (-1.9208%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0386 | -0.0379 | 0.0007 (-1.8141%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0312 | -0.0306 | 0.0006 (-1.9285%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0575 | -0.0563 | 0.0012 (-2.0866%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0406 | -0.0398 | 0.0008 (-1.9696%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 25984.9000 | 25984.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 31860.3000 | 31860.3000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 11766.3000 | 11766.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 6 | 6 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0024 | 0.0024 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 6 | 6 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb_cdc_core
Metric | Before | After | Delta |
---|---|---|---|
power__switching__total | 0.0006 | 0.0006 | 0.0000 (+0.0157%) ❗ |
power__total | 0.0021 | 0.0021 | 0.0000 (+0.0046%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.1073 | 0.1073 | -0.0000 (-0.0009%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0900 | 0.0900 | -0.0000 (-0.0011%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0961 | 0.0961 | -0.0000 (-0.0010%) ❗ |
clock__skew__worst_hold | 0.1073 | 0.1073 | -0.0000 (-0.0009%) ⭕ |
power__internal__total | 0.0015 | 0.0015 | -0.0000 (-0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.1073 | 0.1073 | -0.0000 (-0.0009%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0900 | 0.0900 | -0.0000 (-0.0011%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0961 | 0.0961 | -0.0000 (-0.0010%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0433 | 0.0433 | 0.0000 (0.0000%) ⭕ |
design__core__area | 64464.3000 | 64464.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 73561.4000 | 73561.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 22282.6000 | 22282.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 26 | 26 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0551 | 0.0551 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0551 | 0.0551 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 26 | 26 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 26 | 26 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0694 | 0.0694 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0694 | 0.0694 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 26 | 26 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0433 | 0.0433 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0433 | 0.0433 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 26 | 26 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 26 | 26 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0557 | 0.0557 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0557 | 0.0557 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 26 | 26 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0468 | 0.0468 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0468 | 0.0468 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 26 | 26 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 26 | 26 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0601 | 0.0601 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0601 | 0.0601 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 26 | 26 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/user_proj_timer
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0094 | -0.0094 | 0.0000 (-0.0212%) ❗ |
clock__skew__worst_setup | -0.0221 | -0.0221 | -0.0000 (+0.0181%) ❗ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (+0.7246%) ❗ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (+0.0001%) ❗ |
power__switching__total | 0.0001 | 0.0001 | 0.0000 (+0.0859%) ❗ |
power__total | 0.0003 | 0.0003 | 0.0000 (+0.0196%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0120 | -0.0120 | 0.0000 (-0.0334%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0221 | -0.0221 | -0.0000 (+0.0181%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0140 | -0.0140 | 0.0000 (-0.0286%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0094 | -0.0094 | 0.0000 (-0.0212%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0187 | -0.0187 | -0.0000 (+0.0054%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0115 | -0.0115 | 0.0000 (-0.0174%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0102 | -0.0102 | 0.0000 (-0.0294%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0200 | -0.0200 | -0.0000 (+0.0100%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0123 | -0.0123 | 0.0000 (-0.0244%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0120 | -0.0120 | 0.0000 (-0.0334%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0221 | -0.0221 | -0.0000 (+0.0181%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0140 | -0.0140 | 0.0000 (-0.0286%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0094 | -0.0094 | 0.0000 (-0.0212%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0187 | -0.0187 | -0.0000 (+0.0054%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0115 | -0.0115 | 0.0000 (-0.0174%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0102 | -0.0102 | 0.0000 (-0.0294%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0200 | -0.0200 | -0.0000 (+0.0100%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0123 | -0.0123 | 0.0000 (-0.0244%) ⭕ |
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
design__core__area | 655604 | 655604 | 0 (0.0000%) ⭕ |
design__die__area | 700000 | 700000 | 0 (0.0000%) ⭕ |
design__instance__area | 17767 | 17767 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 27 | 27 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 27 | 27 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/wbqspiflash
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 5 | 6 | 1 (+20.0000%) ❗ |
clock__skew__worst_setup | -0.3289 | -0.3632 | -0.0342 (+10.4048%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.1309 | -0.1429 | -0.0120 (+9.1978%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.3289 | -0.3632 | -0.0342 (+10.4048%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.1900 | -0.2096 | -0.0196 (+10.3055%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.1236 | -0.1322 | -0.0087 (+7.0082%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.3151 | -0.3383 | -0.0232 (+7.3479%) ❗ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 20 | 21 | 1 (+5.0000%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.1804 | -0.1945 | -0.0140 (+7.7739%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.1269 | -0.1370 | -0.0100 (+7.9135%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.3219 | -0.3495 | -0.0276 (+8.5642%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.1849 | -0.2012 | -0.0163 (+8.8042%) ❗ |
clock__skew__worst_hold | -0.1236 | -0.1322 | -0.0087 (+7.0082%) ⭕ |
design__instance__area | 27455 | 27335 | -120 (-0.4371%) ⭕ |
design__max_fanout_violation__count | 50 | 48 | -2 (-4.0000%) ⭕ |
design__max_slew_violation__count | 57 | 47 | -10 (-17.5439%) ⭕ |
ir__drop__worst | 0.0019 | 0.0018 | -0.0000 (-1.6043%) ⭕ |
power__internal__total | 0.0030 | 0.0029 | -0.0000 (-0.2865%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-1.0858%) ⭕ |
power__switching__total | 0.0028 | 0.0028 | -0.0000 (-0.5644%) ⭕ |
power__total | 0.0058 | 0.0058 | -0.0000 (-0.4225%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1309 | -0.1429 | -0.0120 (+9.1978%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 50 | 48 | -2 (-4.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.3289 | -0.3632 | -0.0342 (+10.4048%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 50 | 48 | -2 (-4.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 57 | 47 | -10 (-17.5439%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.1900 | -0.2096 | -0.0196 (+10.3055%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 50 | 48 | -2 (-4.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.1236 | -0.1322 | -0.0087 (+7.0082%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 50 | 48 | -2 (-4.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.3151 | -0.3383 | -0.0232 (+7.3479%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 50 | 48 | -2 (-4.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.1804 | -0.1945 | -0.0140 (+7.7739%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 50 | 48 | -2 (-4.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1269 | -0.1370 | -0.0100 (+7.9135%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 50 | 48 | -2 (-4.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.3219 | -0.3495 | -0.0276 (+8.5642%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 50 | 48 | -2 (-4.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 45 | 30 | -15 (-33.3333%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.1849 | -0.2012 | -0.0163 (+8.8042%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 50 | 48 | -2 (-4.0000%) ⭕ |
antenna__violating__pins | 7 | 7 | 0 (0.0000%) ⭕ |
design__core__area | 74571.5000 | 74571.5000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 84643.5000 | 84643.5000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/xtea
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.0262 | 0.0258 | -0.0004 (-1.6605%) ❗ |
ir__drop__worst | 0.0041 | 0.0042 | 0.0000 (+0.2415%) ❗ |
power__switching__total | 0.0100 | 0.0100 | 0.0000 (+0.0299%) ❗ |
power__total | 0.0182 | 0.0182 | 0.0000 (+0.0157%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0324 | 0.0330 | 0.0005 (+1.6708%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0629 | 0.0616 | -0.0013 (-2.0607%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0425 | 0.0425 | -0.0000 (-0.0517%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0262 | 0.0258 | -0.0004 (-1.6605%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0546 | 0.0515 | -0.0031 (-5.6882%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0349 | 0.0339 | -0.0010 (-2.8081%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0284 | 0.0281 | -0.0003 (-1.1131%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0568 | 0.0548 | -0.0020 (-3.5625%) ❗ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 3 | 14 | 11 (+366.6667%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0376 | 0.0367 | -0.0009 (-2.3387%) ❗ |
clock__skew__worst_hold | 0.0629 | 0.0616 | -0.0013 (-2.0607%) ⭕ |
power__internal__total | 0.0083 | 0.0083 | -0.0000 (-0.0013%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0324 | 0.0330 | 0.0005 (+1.6708%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0629 | 0.0616 | -0.0013 (-2.0607%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0425 | 0.0425 | -0.0000 (-0.0517%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0262 | 0.0258 | -0.0004 (-1.6605%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0546 | 0.0515 | -0.0031 (-5.6882%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0349 | 0.0339 | -0.0010 (-2.8081%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0284 | 0.0281 | -0.0003 (-1.1131%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0568 | 0.0548 | -0.0020 (-3.5625%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0376 | 0.0367 | -0.0009 (-2.3387%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 46358.2000 | 46358.2000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 54022.9000 | 54022.9000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 24262 | 24262 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 14 | 14 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 195 | 195 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 195 | 195 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 14 | 14 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 65 | 65 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 65 | 65 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 65 | 65 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 65 | 65 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 10 | 10 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 65 | 65 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 65 | 65 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/zipdiv
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | 0.0344 | 0.0344 | 0.0000 (+0.0116%) ❗ |
ir__drop__worst | 0.0004 | 0.0004 | 0.0000 (+0.4739%) ❗ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (+0.0679%) ❗ |
power__total | 0.0010 | 0.0010 | 0.0000 (+0.0266%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0283 | -0.0283 | 0.0000 (-0.0953%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0594 | -0.0594 | 0.0000 (-0.0438%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0376 | -0.0376 | 0.0000 (-0.0718%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0260 | 0.0260 | -0.0000 (-0.0230%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0543 | -0.0543 | 0.0000 (-0.0221%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0344 | 0.0344 | 0.0000 (+0.0116%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0267 | 0.0267 | -0.0000 (-0.0487%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0564 | -0.0563 | 0.0000 (-0.0337%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0355 | -0.0354 | 0.0000 (-0.0536%) ❗ |
clock__skew__worst_setup | -0.0594 | -0.0594 | 0.0000 (-0.0438%) ⭕ |
power__internal__total | 0.0006 | 0.0006 | -0.0000 (-0.0004%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0283 | -0.0283 | 0.0000 (-0.0953%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0594 | -0.0594 | 0.0000 (-0.0438%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0376 | -0.0376 | 0.0000 (-0.0718%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0260 | 0.0260 | -0.0000 (-0.0230%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0543 | -0.0543 | 0.0000 (-0.0221%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0344 | 0.0344 | 0.0000 (+0.0116%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0267 | 0.0267 | -0.0000 (-0.0487%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0564 | -0.0563 | 0.0000 (-0.0337%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 9 | 5 | -4 (-44.4444%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0355 | -0.0354 | 0.0000 (-0.0536%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 29796.1000 | 29796.1000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 36193 | 36193 | 0 (0.0000%) ⭕ |
design__instance__area | 13086.3000 | 13086.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 13 | 13 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 13 | 13 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |