gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/spm
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.012613 | 0.012613 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.012613 | 0.012613 | 0.000000 (0.00%) ⭕ |
| design__core__area | 22439.300000 | 22439.300000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 29881.600000 | 29881.600000 | 0.000000 (0.00%) ⭕ |
| design__instance__area | 12121.900000 | 12121.900000 | 0.000000 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 81 | 81 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.002480 | 0.002480 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.012000 | 0.012000 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 4.990000 | 4.990000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.007644 | 0.007644 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.002245 | 0.002245 | 0.000000 (0.00%) ⭕ |
| power__total | 0.009889 | 0.009889 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.004852 | 0.004852 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.004852 | 0.004852 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.012613 | 0.012613 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.012613 | 0.012613 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.007251 | 0.007251 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.007251 | 0.007251 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.004739 | 0.004739 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.004739 | 0.004739 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.011579 | 0.011579 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.011579 | 0.011579 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.006781 | 0.006781 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.006781 | 0.006781 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.004675 | 0.004675 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.004675 | 0.004675 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.012026 | 0.012026 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.012026 | 0.012026 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.006892 | 0.006892 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.006892 | 0.006892 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/gcd
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 4 | 4 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 4 | 4 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.022476 | 0.022476 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.022476 | 0.022476 | 0.000000 (0.00%) ⭕ |
| design__core__area | 67039.300000 | 67039.300000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 78425.200000 | 78425.200000 | 0.000000 (0.00%) ⭕ |
| design__instance__area | 4513.080000 | 4513.080000 | 0.000000 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 6 | 6 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000003 | 0.000003 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.000128 | 0.000128 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.000421 | 0.000421 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000341 | 0.000341 | 0.000000 (0.00%) ⭕ |
| power__total | 0.000762 | 0.000762 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.012381 | 0.012381 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.012381 | 0.012381 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.022476 | 0.022476 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.022476 | 0.022476 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.014994 | 0.014994 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.014994 | 0.014994 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.010479 | 0.010479 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.010479 | 0.010479 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.020185 | 0.020185 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.020185 | 0.020185 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.013144 | 0.013144 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.013144 | 0.013144 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.011001 | 0.011001 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.011001 | 0.011001 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.020995 | 0.020995 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.020995 | 0.020995 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.013638 | 0.013638 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.013638 | 0.013638 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/inverter
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| design__core__area | 1051.010000 | 1051.010000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 2500 | 2500 | 0 (0.00%) ⭕ |
| design__instance__area | 18.768000 | 18.768000 | 0.000000 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/spm
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.007846 | 0.007846 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.007846 | 0.007846 | 0.000000 (0.00%) ⭕ |
| design__core__area | 8092.760000 | 8092.760000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 11327.400000 | 11327.400000 | 0.000000 (0.00%) ⭕ |
| design__instance__area | 3595.950000 | 3595.950000 | 0.000000 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000230 | 0.000230 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.001320 | 0.001320 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.000746 | 0.000746 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000360 | 0.000360 | 0.000000 (0.00%) ⭕ |
| power__total | 0.001106 | 0.001106 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.007846 | 0.007846 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.007846 | 0.007846 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.014450 | -0.014450 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.014450 | -0.014450 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.009884 | -0.009884 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.009884 | -0.009884 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.006610 | -0.006610 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.006610 | -0.006610 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.012586 | -0.012586 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.012586 | -0.012586 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.008179 | -0.008179 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.008179 | -0.008179 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.007341 | 0.007341 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.007341 | 0.007341 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.013365 | -0.013365 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.013365 | -0.013365 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.008779 | -0.008779 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.008779 | -0.008779 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |