gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/spm
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.012613 | 0.012613 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.012613 | 0.012613 | 0.000000 (0.00%) ⭕ |
| design__core__area | 22439.300000 | 22439.300000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 29881.600000 | 29881.600000 | 0.000000 (0.00%) ⭕ |
| design__instance__area | 12121.900000 | 12121.900000 | 0.000000 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 81 | 81 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.002480 | 0.002480 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.012000 | 0.012000 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 4.990000 | 4.990000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.007644 | 0.007644 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.002245 | 0.002245 | 0.000000 (0.00%) ⭕ |
| power__total | 0.009889 | 0.009889 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.004852 | 0.004852 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.004852 | 0.004852 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.012613 | 0.012613 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.012613 | 0.012613 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.007251 | 0.007251 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.007251 | 0.007251 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.004739 | 0.004739 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.004739 | 0.004739 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.011579 | 0.011579 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.011579 | 0.011579 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.006781 | 0.006781 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.006781 | 0.006781 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.004675 | 0.004675 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.004675 | 0.004675 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.012026 | 0.012026 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.012026 | 0.012026 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.006892 | 0.006892 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.006892 | 0.006892 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_GPIO
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.000914 | 0.000914 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.000914 | 0.000914 | 0.000000 (0.00%) ⭕ |
| design__core__area | 1726.660000 | 1726.660000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 2852.090000 | 2852.090000 | 0.000000 (0.00%) ⭕ |
| design__instance__area | 1465.160000 | 1465.160000 | 0.000000 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 18 | 18 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000088 | 0.000088 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.000277 | 0.000277 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.000200 | 0.000200 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000087 | 0.000087 | 0.000000 (0.00%) ⭕ |
| power__total | 0.000287 | 0.000287 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.000914 | 0.000914 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.000914 | 0.000914 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.000848 | 0.000848 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.000848 | 0.000848 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.000894 | 0.000894 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.000894 | 0.000894 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.000270 | 0.000270 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.000270 | 0.000270 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.000248 | 0.000248 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.000248 | 0.000248 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.000263 | 0.000263 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.000263 | 0.000263 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.000415 | 0.000415 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.000415 | 0.000415 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.000382 | 0.000382 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.000382 | 0.000382 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.000405 | 0.000405 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.000405 | 0.000405 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_PSRAM_CTRL_V2
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.009575 | 0.009575 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.009575 | 0.009575 | 0.000000 (0.00%) ⭕ |
| design__core__area | 7136.840000 | 7136.840000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 10255.300000 | 10255.300000 | 0.000000 (0.00%) ⭕ |
| design__instance__area | 5636.660000 | 5636.660000 | 0.000000 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 18 | 18 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000545 | 0.000545 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.001620 | 0.001620 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.000986 | 0.000986 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.001101 | 0.001101 | 0.000000 (0.00%) ⭕ |
| power__total | 0.002087 | 0.002087 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 108 | 108 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.005393 | -0.005393 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.005393 | -0.005393 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.010822 | -0.010822 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.010822 | -0.010822 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 36 | 36 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.006602 | -0.006602 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.006602 | -0.006602 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.004825 | 0.004825 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.004825 | 0.004825 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.009575 | 0.009575 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.009575 | 0.009575 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 36 | 36 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.005834 | 0.005834 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.005834 | 0.005834 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.004847 | -0.004847 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.004847 | -0.004847 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.009745 | -0.009745 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.009745 | -0.009745 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 36 | 36 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.005923 | -0.005923 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.005923 | -0.005923 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_TCC32
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | -0.022723 | -0.022723 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | -0.022723 | -0.022723 | 0.000000 (0.00%) ⭕ |
| design__core__area | 11911.400000 | 11911.400000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 15858.600000 | 15858.600000 | 0.000000 (0.00%) ⭕ |
| design__instance__area | 8951.080000 | 8951.080000 | 0.000000 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 27 | 27 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000457 | 0.000457 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.002210 | 0.002210 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.001085 | 0.001085 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000804 | 0.000804 | 0.000000 (0.00%) ⭕ |
| power__total | 0.001889 | 0.001889 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.035196 | -0.035196 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.035196 | -0.035196 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.052211 | -0.052211 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.052211 | -0.052211 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.039968 | -0.039968 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.039968 | -0.039968 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.022723 | -0.022723 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.022723 | -0.022723 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.038585 | -0.038585 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.038585 | -0.038585 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.027440 | -0.027440 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.027440 | -0.027440 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.026344 | -0.026344 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.026344 | -0.026344 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.042854 | -0.042854 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.042854 | -0.042854 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.031087 | -0.031087 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.031087 | -0.031087 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_UART
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.172322 | 0.172322 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.172322 | 0.172322 | 0.000000 (0.00%) ⭕ |
| design__core__area | 24176.900000 | 24176.900000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 29791.400000 | 29791.400000 | 0.000000 (0.00%) ⭕ |
| design__instance__area | 18278.800000 | 18278.800000 | 0.000000 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 171 | 171 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000840 | 0.000840 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.003280 | 0.003280 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.002764 | 0.002764 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.001214 | 0.001214 | 0.000000 (0.00%) ⭕ |
| power__total | 0.003978 | 0.003978 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.091555 | 0.091555 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.091555 | 0.091555 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 19 | 19 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.172322 | 0.172322 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.172322 | 0.172322 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 19 | 19 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.116491 | 0.116491 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.116491 | 0.116491 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 19 | 19 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.084016 | 0.084016 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.084016 | 0.084016 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 19 | 19 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.159939 | 0.159939 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.159939 | 0.159939 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 19 | 19 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.107535 | 0.107535 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.107535 | 0.107535 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 19 | 19 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.087235 | 0.087235 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.087235 | 0.087235 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 19 | 19 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.165592 | 0.165592 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.165592 | 0.165592 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 19 | 19 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.111446 | 0.111446 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.111446 | 0.111446 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 19 | 19 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_CLK_RST
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | -0.752393 | -0.752393 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | -0.745985 | -0.745985 | 0.000000 (0.00%) ⭕ |
| design__core__area | 9240.110000 | 9240.110000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 12880.800000 | 12880.800000 | 0.000000 (0.00%) ⭕ |
| design__instance__area | 5172.460000 | 5172.460000 | 0.000000 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 6 | 6 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 36 | 36 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 396 | 396 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000020 | 0.000020 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.000116 | 0.000116 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.000337 | 0.000337 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000209 | 0.000209 | 0.000000 (0.00%) ⭕ |
| power__total | 0.000547 | 0.000547 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.752395 | -0.752395 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.745985 | -0.745985 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 4 | 4 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -2.678984 | -2.678984 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | -2.673982 | -2.673982 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 132 | 132 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -1.437249 | -1.437249 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | -1.434542 | -1.434542 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 4 | 4 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.752393 | -0.752393 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.746095 | -0.746095 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 4 | 4 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -2.656407 | -2.656407 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | -2.651417 | -2.651417 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 132 | 132 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -1.432484 | -1.432484 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | -1.429700 | -1.429700 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 4 | 4 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.756637 | -0.756637 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.750282 | -0.750282 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -2.672622 | -2.672622 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -2.667672 | -2.667672 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 132 | 132 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -1.439419 | -1.439419 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -1.436625 | -1.436625 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 4 | 4 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_DMAC_AHBL
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 5 | 5 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 5 | 5 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 1.853186 | 1.853186 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 3.187736 | 3.187736 | 0.000000 (0.00%) ⭕ |
| design__core__area | 19398.600000 | 19398.600000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 24435.400000 | 24435.400000 | 0.000000 (0.00%) ⭕ |
| design__instance__area | 15257.100000 | 15257.100000 | 0.000000 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 90 | 90 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 3 | 3 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000415 | 0.000415 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.001830 | 0.001830 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.001238 | 0.001238 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000548 | 0.000548 | 0.000000 (0.00%) ⭕ |
| power__total | 0.001786 | 0.001786 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 90 | 90 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.617577 | 0.617577 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 1.079920 | 1.079920 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 10 | 10 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | 1.853186 | 1.853186 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 3.187736 | 3.187736 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 10 | 10 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 31 | 31 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.962223 | 0.962223 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 1.677143 | 1.677143 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 10 | 10 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.592125 | 0.592125 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 1.040257 | 1.040257 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 10 | 10 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | 1.789279 | 1.789279 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 3.079308 | 3.079308 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 10 | 10 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 29 | 29 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.925431 | 0.925431 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 1.612378 | 1.612378 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 10 | 10 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.604715 | 0.604715 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 1.060357 | 1.060357 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 10 | 10 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 1.821405 | 1.821405 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 3.131479 | 3.131479 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 10 | 10 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 30 | 30 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.943612 | 0.943612 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 1.645099 | 1.645099 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 10 | 10 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_SPI_XIP_CACHE
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 37 | 37 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 52 | 52 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.153325 | 0.153325 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.153325 | 0.153325 | 0.000000 (0.00%) ⭕ |
| design__core__area | 175921 | 175921 | 0 (0.00%) ⭕ |
| design__die__area | 190438 | 190438 | 0 (0.00%) ⭕ |
| design__instance__area | 124821 | 124821 | 0 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 1791 | 1791 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 510 | 510 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000355 | 0.000355 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.001820 | 0.001820 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.013523 | 0.013523 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.005717 | 0.005717 | 0.000000 (0.00%) ⭕ |
| power__total | 0.019240 | 0.019240 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 96 | 96 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.119710 | 0.119710 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.119710 | 0.119710 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 199 | 199 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.247569 | -0.247569 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.247569 | -0.247569 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 199 | 199 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 181 | 181 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.153325 | 0.153325 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.153325 | 0.153325 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 199 | 199 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.106706 | 0.106706 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.106706 | 0.106706 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 199 | 199 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.215666 | -0.215666 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.215666 | -0.215666 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 199 | 199 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 156 | 156 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 32 | 32 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.137153 | 0.137153 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.137153 | 0.137153 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 199 | 199 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.112221 | 0.112221 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.112221 | 0.112221 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 199 | 199 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.230550 | -0.230550 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.230550 | -0.230550 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 199 | 199 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 171 | 171 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.144133 | 0.144133 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.144133 | 0.144133 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 199 | 199 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_user_project_wrapper
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | -3.192036 | -3.192036 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.563769 | 0.563769 | 0.000000 (0.00%) ⭕ |
| design__core__area | 10174000 | 10174000 | 0 (0.00%) ⭕ |
| design__die__area | 10278400 | 10278400 | 0 (0.00%) ⭕ |
| design__instance__area | 656000 | 656000 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 8883 | 8883 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0 | 0 | 0 (0.00%) ⭕ |
| ir__drop__worst | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.033509 | 0.033509 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.044592 | 0.044592 | 0.000000 (0.00%) ⭕ |
| power__total | 0.078102 | 0.078102 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.212687 | -3.212687 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.220629 | 0.220629 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.549167 | -3.549167 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.563769 | 0.563769 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.316998 | -3.316998 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.326835 | 0.326835 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.192036 | -3.192036 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.199175 | 0.199175 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.501814 | -3.501814 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.514776 | 0.514776 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.286248 | -3.286248 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.295534 | 0.295534 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.200716 | -3.200716 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.208493 | 0.208493 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.523835 | -3.523835 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.537898 | 0.537898 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.299828 | -3.299828 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.309661 | 0.309661 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/caravel_upw
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__core__area | 10174000 | 10174000 | 0 (0.00%) ⭕ |
| design__die__area | 10278400 | 10278400 | 0 (0.00%) ⭕ |
| design__instance__area | 1080000 | 1080000 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 40 | 40 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 135 | 135 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0 | 0 | 0 (0.00%) ⭕ |
| ir__drop__worst | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 4 | 4 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 5 | 5 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 5 | 5 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 5 | 5 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 5 | 5 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 5 | 5 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 5 | 5 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/gcd
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 4 | 4 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 4 | 4 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.022476 | 0.022476 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.022476 | 0.022476 | 0.000000 (0.00%) ⭕ |
| design__core__area | 67039.300000 | 67039.300000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 78425.200000 | 78425.200000 | 0.000000 (0.00%) ⭕ |
| design__instance__area | 4513.080000 | 4513.080000 | 0.000000 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 6 | 6 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000003 | 0.000003 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.000129 | 0.000129 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.000421 | 0.000421 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000341 | 0.000341 | 0.000000 (0.00%) ⭕ |
| power__total | 0.000762 | 0.000762 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.012381 | 0.012381 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.012381 | 0.012381 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.022476 | 0.022476 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.022476 | 0.022476 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.014994 | 0.014994 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.014994 | 0.014994 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.010479 | 0.010479 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.010479 | 0.010479 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.020185 | 0.020185 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.020185 | 0.020185 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.013144 | 0.013144 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.013144 | 0.013144 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.011001 | 0.011001 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.011001 | 0.011001 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.020995 | 0.020995 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.020995 | 0.020995 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.013638 | 0.013638 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.013638 | 0.013638 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/inverter
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| design__core__area | 1051.010000 | 1051.010000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 2500 | 2500 | 0 (0.00%) ⭕ |
| design__instance__area | 18.768000 | 18.768000 | 0.000000 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/io_placer
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__core__area | 10174000 | 10174000 | 0 (0.00%) ⭕ |
| design__die__area | 10278400 | 10278400 | 0 (0.00%) ⭕ |
| design__instance__area | 1080000 | 1080000 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 38 | 38 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 135 | 135 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0 | 0 | 0 (0.00%) ⭕ |
| ir__drop__worst | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 4 | 4 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 5 | 5 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 5 | 5 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 5 | 5 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 5 | 5 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 5 | 5 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 5 | 5 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 15 | 15 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/manual_macro_placement_test
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.035729 | 0.035729 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.035729 | 0.035729 | 0.000000 (0.00%) ⭕ |
| design__core__area | 80146.900000 | 80146.900000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 90000 | 90000 | 0 (0.00%) ⭕ |
| design__instance__area | 23795.800000 | 23795.800000 | 0.000000 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 288 | 288 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.000114 | 0.000114 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000045 | 0.000045 | 0.000000 (0.00%) ⭕ |
| power__total | 0.000159 | 0.000159 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.035655 | 0.035655 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.035655 | 0.035655 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 32 | 32 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.035393 | 0.035393 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.035393 | 0.035393 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.035729 | 0.035729 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.035729 | 0.035729 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 32 | 32 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.014315 | 0.014315 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.014315 | 0.014315 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 32 | 32 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.013603 | 0.013603 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.013603 | 0.013603 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 32 | 32 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.014021 | 0.014021 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.014021 | 0.014021 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 32 | 32 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.020170 | 0.020170 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.020170 | 0.020170 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 32 | 32 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.019341 | 0.019341 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.019341 | 0.019341 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.019844 | 0.019844 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.019844 | 0.019844 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 32 | 32 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/spm
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.007846 | 0.007846 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.007846 | 0.007846 | 0.000000 (0.00%) ⭕ |
| design__core__area | 8092.760000 | 8092.760000 | 0.000000 (0.00%) ⭕ |
| design__die__area | 11327.400000 | 11327.400000 | 0.000000 (0.00%) ⭕ |
| design__instance__area | 3595.950000 | 3595.950000 | 0.000000 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000198 | 0.000198 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.001290 | 0.001290 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.000746 | 0.000746 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000360 | 0.000360 | 0.000000 (0.00%) ⭕ |
| power__total | 0.001106 | 0.001106 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.007846 | 0.007846 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.007846 | 0.007846 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.014450 | -0.014450 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.014450 | -0.014450 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.009884 | -0.009884 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.009884 | -0.009884 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.006610 | -0.006610 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.006610 | -0.006610 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.012586 | -0.012586 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.012586 | -0.012586 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.008179 | -0.008179 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.008179 | -0.008179 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.007341 | 0.007341 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.007341 | 0.007341 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.013365 | -0.013365 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.013365 | -0.013365 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.008779 | -0.008779 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.008779 | -0.008779 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/test_sram_macro
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 39 | 39 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 40 | 40 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | -0.266845 | -0.266845 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | -0.266845 | -0.266845 | 0.000000 (0.00%) ⭕ |
| design__core__area | 906252 | 906252 | 0 (0.00%) ⭕ |
| design__die__area | 937500 | 937500 | 0 (0.00%) ⭕ |
| design__instance__area | 395875 | 395875 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 21 | 21 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 9 | 9 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 690 | 690 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000003 | 0.000003 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.000543 | 0.000543 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 5666674 | 5666674 | 0 (0.00%) ⭕ |
| power__internal__total | 0.001780 | 0.001780 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000038 | 0.000038 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000220 | 0.000220 | 0.000000 (0.00%) ⭕ |
| power__total | 0.002039 | 0.002039 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.304744 | -0.304744 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.304744 | -0.304744 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 31 | 31 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.715443 | -0.715443 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.715443 | -0.715443 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 125 | 125 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.462190 | -0.462190 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.462190 | -0.462190 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 97 | 97 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.266845 | -0.266845 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.266845 | -0.266845 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 26 | 26 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.608936 | -0.608936 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.608936 | -0.608936 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 113 | 113 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.387878 | -0.387878 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.387878 | -0.387878 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 63 | 63 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.288855 | -0.288855 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.288855 | -0.288855 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 26 | 26 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.665845 | -0.665845 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.665845 | -0.665845 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 118 | 118 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.427249 | -0.427249 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.427249 | -0.427249 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 91 | 91 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
sky130A/sky130_fd_sc_hd/user_proj_timer
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 4 | 4 | 0 (0.00%) ⭕ |
| antenna__violating__pins | 4 | 4 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold | 0.014164 | 0.014164 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup | 0.014164 | 0.014164 | 0.000000 (0.00%) ⭕ |
| design__core__area | 655604 | 655604 | 0 (0.00%) ⭕ |
| design__die__area | 700000 | 700000 | 0 (0.00%) ⭕ |
| design__instance__area | 17767 | 17767 | 0 (0.00%) ⭕ |
| design__lint_errors__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count | 27 | 27 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count | 11 | 11 | 0 (0.00%) ⭕ |
| ir__drop__avg | 0.000001 | 0.000001 | 0.000000 (0.00%) ⭕ |
| ir__drop__worst | 0.000151 | 0.000151 | 0.000000 (0.00%) ⭕ |
| ir__voltage__worst | 1.800000 | 1.800000 | 0.000000 (0.00%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| power__internal__total | 0.000329 | 0.000329 | 0.000000 (0.00%) ⭕ |
| power__leakage__total | 0.000000 | 0.000000 | 0.000000 (0.00%) ⭕ |
| power__switching__total | 0.000134 | 0.000134 | 0.000000 (0.00%) ⭕ |
| power__total | 0.000463 | 0.000463 | 0.000000 (0.00%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.00%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.012214 | 0.012214 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.012214 | 0.012214 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.022772 | -0.022772 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.022772 | -0.022772 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 5 | 5 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.014164 | 0.014164 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.014164 | 0.014164 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.009566 | -0.009566 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.009566 | -0.009566 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.019311 | -0.019311 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.019311 | -0.019311 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.011641 | -0.011641 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.011641 | -0.011641 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.010363 | -0.010363 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.010363 | -0.010363 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.020732 | -0.020732 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.020732 | -0.020732 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.00%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.012491 | -0.012491 | 0.000000 (0.00%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.012491 | -0.012491 | 0.000000 (0.00%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 3 | 3 | 0 (0.00%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.00%) ⭕ |