gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/APU
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.6478 | 0.6478 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2258 | 0.2258 | 0.0000 (0.0000%) ⭕ |
design__core__area | 284217 | 284217 | 0 (0.0000%) ⭕ |
design__die__area | 308622 | 308622 | 0 (0.0000%) ⭕ |
design__instance__area | 108074 | 108074 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 139 | 139 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0016 | 0.0016 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0091 | 0.0091 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0049 | 0.0049 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0140 | 0.0140 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.2374 | 0.2374 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2374 | 0.2374 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 139 | 139 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.6478 | 0.6478 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.6478 | 0.6478 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 139 | 139 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.3645 | 0.3645 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.3645 | 0.3645 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 139 | 139 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.2258 | 0.2258 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2258 | 0.2258 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 139 | 139 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.6199 | 0.6199 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.6199 | 0.6199 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 139 | 139 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.3477 | 0.3477 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.3477 | 0.3477 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 139 | 139 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.2312 | 0.2312 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2312 | 0.2312 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 139 | 139 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.6329 | 0.6329 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.6329 | 0.6329 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 139 | 139 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.3557 | 0.3557 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.3557 | 0.3557 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 139 | 139 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/blink
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.0037 | -0.0037 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.0085 | -0.0085 | 0.0000 (0.0000%) ⭕ |
design__core__area | 6146.5600 | 6146.5600 | 0.0000 (0.0000%) ⭕ |
design__die__area | 10108.6000 | 10108.6000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 4151.1200 | 4151.1200 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0013 | 0.0013 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0055 | 0.0055 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0028 | 0.0028 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.0043 | -0.0043 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.0043 | -0.0043 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.0085 | -0.0085 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.0085 | -0.0085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.0056 | -0.0056 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.0056 | -0.0056 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.0037 | -0.0037 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | -0.0037 | -0.0037 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.0074 | -0.0074 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.0074 | -0.0074 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.0048 | -0.0048 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.0048 | -0.0048 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.0040 | -0.0040 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.0040 | -0.0040 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.0079 | -0.0079 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.0079 | -0.0079 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.0052 | -0.0052 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.0052 | -0.0052 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/cell_inverter
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 8.7808 | 8.7808 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/inverter
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 570.7520 | 570.7520 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
design__instance__area | 57.0752 | 57.0752 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch_bad
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch_good
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/spm
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0119 | 0.0119 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.0299 | -0.0299 | 0.0000 (0.0000%) ⭕ |
design__core__area | 21280.3000 | 21280.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 28670.3000 | 28670.3000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 11634.6000 | 11634.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0023 | 0.0023 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0103 | 0.0103 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0071 | 0.0071 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0021 | 0.0021 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0093 | 0.0093 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.0119 | 0.0119 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.0119 | 0.0119 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.0299 | -0.0299 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.0299 | -0.0299 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.0170 | -0.0170 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.0170 | -0.0170 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.0099 | -0.0099 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | -0.0099 | -0.0099 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.0267 | -0.0267 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.0267 | -0.0267 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.0151 | -0.0151 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.0151 | -0.0151 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.0108 | 0.0108 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.0108 | 0.0108 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.0280 | -0.0280 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.0280 | -0.0280 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.0159 | -0.0159 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.0159 | -0.0159 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.0398 | -0.0398 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.1121 | -0.1121 | 0.0000 (0.0000%) ⭕ |
design__core__area | 59885.1000 | 59885.1000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 72420.7000 | 72420.7000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 31496.7000 | 31496.7000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0014 | 0.0014 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0064 | 0.0064 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0156 | 0.0156 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0053 | 0.0053 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0209 | 0.0209 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.0430 | -0.0430 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.0430 | -0.0430 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.1121 | -0.1121 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.1121 | -0.1121 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.0646 | -0.0646 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.0646 | -0.0646 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.0398 | -0.0398 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | -0.0398 | -0.0398 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.1046 | -0.1046 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.1046 | -0.1046 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.0601 | -0.0601 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.0601 | -0.0601 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.0412 | -0.0412 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.0412 | -0.0412 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.1080 | -0.1080 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.1080 | -0.1080 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.0622 | -0.0622 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.0622 | -0.0622 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb_cdc_core
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.1819 | -0.1819 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.5147 | -0.5147 | 0.0000 (0.0000%) ⭕ |
design__core__area | 157640 | 157640 | 0 (0.0000%) ⭕ |
design__die__area | 177207 | 177207 | 0 (0.0000%) ⭕ |
design__instance__area | 73585.3000 | 73585.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 82 | 82 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0020 | 0.0020 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0143 | 0.0143 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0556 | 0.0556 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0206 | 0.0206 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0762 | 0.0762 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | -0.0383 | -0.0383 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | -0.0383 | -0.0383 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 1 | 1 | 0 (0.0000%) ⭕ |
timing__setup__tns | -109.6923 | -109.6923 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -3.0334 | -3.0334 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 245 | 245 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 278 | 278 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.1868 | -0.1868 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.1868 | -0.1868 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 82 | 82 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.5147 | -0.5147 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.5147 | -0.5147 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 82 | 82 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | -0.0383 | -0.0383 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | -0.0383 | -0.0383 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | -109.6923 | -109.6923 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | -3.0334 | -3.0334 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 100 | 100 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 111 | 111 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2879 | -0.2879 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.2879 | -0.2879 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 82 | 82 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.1819 | -0.1819 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | -0.1819 | -0.1819 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 82 | 82 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.5034 | -0.5034 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.5034 | -0.5034 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 82 | 82 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | -80.0589 | -80.0589 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | -2.7811 | -2.7811 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 63 | 63 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 74 | 74 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2808 | -0.2808 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.2808 | -0.2808 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 82 | 82 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.1841 | -0.1841 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.1841 | -0.1841 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 82 | 82 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.5085 | -0.5085 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.5085 | -0.5085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 82 | 82 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | -91.6986 | -91.6986 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | -2.8966 | -2.8966 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 82 | 82 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 93 | 93 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2842 | -0.2842 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.2842 | -0.2842 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 82 | 82 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/wbqspiflash
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.5209 | 0.5209 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.5259 | -0.5259 | 0.0000 (0.0000%) ⭕ |
design__core__area | 94345.3000 | 94345.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 109560 | 109560 | 0 (0.0000%) ⭕ |
design__instance__area | 67361.9000 | 67361.9000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0131 | 0.0131 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0452 | 0.0452 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9500 | 4.9500 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.1154 | 0.1154 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0852 | 0.0852 | 0.0000 (0.0000%) ⭕ |
power__total | 0.2005 | 0.2005 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -428.0901 | -428.0901 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -4.2895 | -4.2895 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 444 | 444 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 446 | 446 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.1905 | -0.1905 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.1905 | -0.1905 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.5259 | -0.5259 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.5259 | -0.5259 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | -428.0901 | -428.0901 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | -4.2895 | -4.2895 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 148 | 148 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 149 | 149 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2941 | -0.2941 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.2941 | -0.2941 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.1855 | 0.1855 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.1855 | 0.1855 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.5170 | 0.5170 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.5170 | 0.5170 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | -340.7740 | -340.7740 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | -3.4117 | -3.4117 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 148 | 148 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 148 | 148 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.2877 | 0.2877 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2877 | 0.2877 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.1872 | -0.1872 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.1872 | -0.1872 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.5209 | 0.5209 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.5209 | 0.5209 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | -380.1234 | -380.1234 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | -3.8101 | -3.8101 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 148 | 148 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 149 | 149 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.2900 | 0.2900 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2900 | 0.2900 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/zipdiv
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.1317 | 0.1317 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0461 | 0.0461 | 0.0000 (0.0000%) ⭕ |
design__core__area | 73310.9000 | 73310.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 86150 | 86150 | 0 (0.0000%) ⭕ |
design__instance__area | 35410.8000 | 35410.8000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0019 | 0.0019 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0092 | 0.0092 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0195 | 0.0195 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0105 | 0.0105 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0300 | 0.0300 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -298.4356 | -298.4356 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -6.7195 | -6.7195 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 202 | 202 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 202 | 202 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.0517 | 0.0517 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.0517 | 0.0517 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.1317 | 0.1317 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.1317 | 0.1317 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | -298.4356 | -298.4356 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | -6.7195 | -6.7195 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 68 | 68 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 68 | 68 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.0767 | 0.0767 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.0767 | 0.0767 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.0461 | 0.0461 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.0461 | 0.0461 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.1192 | 0.1192 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.1192 | 0.1192 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | -277.6584 | -277.6584 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | -6.4319 | -6.4319 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 67 | 67 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 67 | 67 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.0689 | 0.0689 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.0689 | 0.0689 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.0487 | 0.0487 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.0487 | 0.0487 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.1250 | 0.1250 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.1250 | 0.1250 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | -287.0650 | -287.0650 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | -6.5615 | -6.5615 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 67 | 67 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 67 | 67 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.0725 | 0.0725 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.0725 | 0.0725 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/APU
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 3 | 3 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 3 | 3 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.3672 | 0.3672 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.1399 | 0.1399 | 0.0000 (0.0000%) ⭕ |
design__core__area | 83157.3000 | 83157.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 92941.4000 | 92941.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 32647.6000 | 32647.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 37 | 37 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0011 | 0.0011 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0021 | 0.0021 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.1507 | 0.1507 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1507 | 0.1507 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.3672 | 0.3672 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.3672 | 0.3672 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 37 | 37 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.2164 | 0.2164 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2164 | 0.2164 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.1399 | 0.1399 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1399 | 0.1399 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.3477 | 0.3477 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.3477 | 0.3477 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.2026 | 0.2026 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2026 | 0.2026 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.1443 | 0.1443 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1443 | 0.1443 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.3559 | 0.3559 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.3559 | 0.3559 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.2084 | 0.2084 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2084 | 0.2084 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_GPIO
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.0027 | -0.0027 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.0072 | -0.0072 | 0.0000 (0.0000%) ⭕ |
design__core__area | 1670.3500 | 1670.3500 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2700.3500 | 2700.3500 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 1345.0400 | 1345.0400 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0033 | -0.0033 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0033 | -0.0033 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0072 | -0.0072 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0072 | -0.0072 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0041 | -0.0041 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0041 | -0.0041 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0027 | -0.0027 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0027 | -0.0027 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0061 | -0.0061 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0061 | -0.0061 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0034 | -0.0034 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0034 | -0.0034 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0029 | -0.0029 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0029 | -0.0029 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0064 | -0.0064 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0064 | -0.0064 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0036 | -0.0036 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0036 | -0.0036 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_PSRAM_CTRL_V2
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.0139 | -0.0139 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.0331 | -0.0331 | 0.0000 (0.0000%) ⭕ |
design__core__area | 6794.0200 | 6794.0200 | 0.0000 (0.0000%) ⭕ |
design__die__area | 9934.3000 | 9934.3000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 5751.7700 | 5751.7700 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0024 | 0.0024 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0011 | 0.0011 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0023 | 0.0023 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -4.7181 | -4.7181 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -0.6874 | -0.6874 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 60 | 60 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0164 | -0.0164 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0164 | -0.0164 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0331 | -0.0331 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0331 | -0.0331 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | -4.7181 | -4.7181 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | -0.6874 | -0.6874 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 36 | 36 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0207 | -0.0207 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0207 | -0.0207 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0139 | -0.0139 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0139 | -0.0139 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0289 | -0.0289 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0289 | -0.0289 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | -1.3806 | -1.3806 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | -0.4679 | -0.4679 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0179 | -0.0179 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0179 | -0.0179 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0147 | -0.0147 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0147 | -0.0147 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0307 | -0.0307 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0307 | -0.0307 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | -2.1405 | -2.1405 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | -0.5743 | -0.5743 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 20 | 20 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0188 | -0.0188 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0188 | -0.0188 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_TCC32
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0345 | 0.0345 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0160 | 0.0160 | 0.0000 (0.0000%) ⭕ |
design__core__area | 11369.7000 | 11369.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 15327.4000 | 15327.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 9212.5900 | 9212.5900 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0015 | 0.0015 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0020 | 0.0020 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0172 | 0.0172 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0172 | 0.0172 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0345 | 0.0345 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0345 | 0.0345 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0220 | 0.0220 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0220 | 0.0220 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0160 | 0.0160 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0160 | 0.0160 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0324 | 0.0324 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0324 | 0.0324 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0209 | 0.0209 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0209 | 0.0209 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0165 | 0.0165 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0165 | 0.0165 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0335 | 0.0335 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0335 | 0.0335 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0214 | 0.0214 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0214 | 0.0214 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_UART
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 3 | 3 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 3 | 3 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0737 | 0.0737 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0287 | 0.0287 | 0.0000 (0.0000%) ⭕ |
design__core__area | 22502.8000 | 22502.8000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 27887 | 27887 | 0 (0.0000%) ⭕ |
design__instance__area | 19523.7000 | 19523.7000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0039 | 0.0039 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0031 | 0.0031 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0016 | 0.0016 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0047 | 0.0047 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0365 | 0.0365 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0365 | 0.0365 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0737 | 0.0737 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0737 | 0.0737 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0455 | 0.0455 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0455 | 0.0455 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0287 | 0.0287 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0287 | 0.0287 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0664 | 0.0664 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0664 | 0.0664 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0381 | 0.0381 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0381 | 0.0381 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0314 | 0.0314 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0314 | 0.0314 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0683 | 0.0683 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0683 | 0.0683 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0396 | 0.0396 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0396 | 0.0396 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_CLK_RST
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.7515 | -0.7515 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -2.6726 | -2.6726 | 0.0000 (0.0000%) ⭕ |
design__core__area | 9240.1100 | 9240.1100 | 0.0000 (0.0000%) ⭕ |
design__die__area | 12880.8000 | 12880.8000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 5172.4600 | 5172.4600 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 132 | 132 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.7544 | -0.7544 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.7481 | -0.7481 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -2.6775 | -2.6775 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -2.6726 | -2.6726 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 132 | 132 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -1.4388 | -1.4388 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -1.4361 | -1.4361 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.7515 | -0.7515 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.7452 | -0.7452 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -2.6522 | -2.6522 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -2.6472 | -2.6472 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 132 | 132 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -1.4310 | -1.4310 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -1.4283 | -1.4283 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.7564 | -0.7564 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.7501 | -0.7501 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -2.6688 | -2.6688 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -2.6639 | -2.6639 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 132 | 132 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -1.4381 | -1.4381 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -1.4354 | -1.4354 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_DMAC_AHBL
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 1.8263 | 1.8263 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 1.0386 | 1.0386 | 0.0000 (0.0000%) ⭕ |
design__core__area | 19398.6000 | 19398.6000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 24435.4000 | 24435.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 15175.8000 | 15175.8000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0020 | 0.0020 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -75.8709 | -75.8709 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -4.0105 | -4.0105 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 88 | 88 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.6081 | 0.6081 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 1.0796 | 1.0796 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 1.8263 | 1.8263 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 3.2217 | 3.2217 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | -75.8709 | -75.8709 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | -4.0105 | -4.0105 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 30 | 30 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.9474 | 0.9474 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 1.6761 | 1.6761 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.5825 | 0.5825 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 1.0386 | 1.0386 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 1.7639 | 1.7639 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 3.0996 | 3.0996 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | -67.4476 | -67.4476 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | -3.7031 | -3.7031 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 29 | 29 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.9106 | 0.9106 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 1.6104 | 1.6104 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.5942 | 0.5942 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 1.0587 | 1.0587 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 1.7922 | 1.7922 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 3.1668 | 3.1668 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | -71.2845 | -71.2845 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | -3.8544 | -3.8544 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 29 | 29 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.9281 | 0.9281 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 1.6431 | 1.6431 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_SPI_XIP_CACHE
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 31 | 31 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 35 | 35 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.1450 | 0.1450 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.1591 | -0.1591 | 0.0000 (0.0000%) ⭕ |
design__core__area | 175921 | 175921 | 0 (0.0000%) ⭕ |
design__die__area | 190438 | 190438 | 0 (0.0000%) ⭕ |
design__instance__area | 147036 | 147036 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 29 | 29 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 216 | 216 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 266 | 266 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0148 | 0.0148 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0066 | 0.0066 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0214 | 0.0214 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -63.9409 | -63.9409 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -2.6092 | -2.6092 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 96 | 96 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0967 | -0.0967 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0967 | -0.0967 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 29 | 29 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 216 | 216 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.1591 | -0.1591 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.1591 | -0.1591 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 29 | 29 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 216 | 216 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 266 | 266 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | -63.9409 | -63.9409 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | -2.6092 | -2.6092 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.1178 | -0.1178 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.1178 | -0.1178 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 29 | 29 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 216 | 216 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 85 | 85 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0600 | -0.0600 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0600 | -0.0600 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 216 | 216 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.1342 | 0.1342 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.1342 | 0.1342 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 216 | 216 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 243 | 243 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | -39.4486 | -39.4486 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | -1.8028 | -1.8028 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0825 | 0.0825 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0825 | 0.0825 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 216 | 216 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0730 | -0.0730 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0730 | -0.0730 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 216 | 216 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.1450 | 0.1450 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.1450 | 0.1450 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 216 | 216 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 256 | 256 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | -52.0311 | -52.0311 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | -2.2224 | -2.2224 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0914 | -0.0914 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0914 | -0.0914 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 216 | 216 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_upw_new
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -3.1920 | -3.1920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.1992 | 0.1992 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 656000 | 656000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0094 | 0.0094 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0128 | 0.0128 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 207 | 207 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.2127 | -3.2127 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2206 | 0.2206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.5492 | -3.5492 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.5638 | 0.5638 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.3170 | -3.3170 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.3268 | 0.3268 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.1920 | -3.1920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1992 | 0.1992 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.5018 | -3.5018 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.5148 | 0.5148 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.2862 | -3.2862 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2955 | 0.2955 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.2007 | -3.2007 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2085 | 0.2085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.5238 | -3.5238 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.5379 | 0.5379 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.2998 | -3.2998 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.3097 | 0.3097 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_upw_old
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -3.1920 | -3.1920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.1992 | 0.1992 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 656000 | 656000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0094 | 0.0094 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0128 | 0.0128 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 207 | 207 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.2127 | -3.2127 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2206 | 0.2206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.5492 | -3.5492 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.5638 | 0.5638 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.3170 | -3.3170 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.3268 | 0.3268 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.1920 | -3.1920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1992 | 0.1992 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.5018 | -3.5018 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.5148 | 0.5148 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.2862 | -3.2862 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2955 | 0.2955 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.2007 | -3.2007 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2085 | 0.2085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.5238 | -3.5238 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.5379 | 0.5379 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.2998 | -3.2998 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.3097 | 0.3097 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/blink
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0066 | 0.0066 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0027 | 0.0027 | 0.0000 (0.0000%) ⭕ |
design__core__area | 2387.2900 | 2387.2900 | 0.0000 (0.0000%) ⭕ |
design__die__area | 4273.3200 | 4273.3200 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 1393.8400 | 1393.8400 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0039 | 0.0039 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0039 | 0.0039 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0066 | 0.0066 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0066 | 0.0066 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0045 | 0.0045 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0045 | 0.0045 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0027 | 0.0027 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0027 | 0.0027 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0053 | 0.0053 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0053 | 0.0053 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0030 | 0.0030 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0030 | 0.0030 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0057 | 0.0057 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0057 | 0.0057 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0036 | 0.0036 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0036 | 0.0036 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/caravel_upw
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 1080000 | 1080000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 15 | 15 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 240 | 240 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/cell_inverter
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/dual_spm
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0112 | 0.0112 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.0104 | -0.0104 | 0.0000 (0.0000%) ⭕ |
design__core__area | 232536 | 232536 | 0 (0.0000%) ⭕ |
design__die__area | 250000 | 250000 | 0 (0.0000%) ⭕ |
design__instance__area | 22872.3000 | 22872.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0007 | 0.0007 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0025 | 0.0025 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0065 | 0.0065 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0065 | 0.0065 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0112 | 0.0112 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0112 | 0.0112 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0083 | 0.0083 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0083 | 0.0083 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0055 | 0.0055 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0055 | 0.0055 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0101 | 0.0101 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0101 | 0.0101 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0072 | 0.0072 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0072 | 0.0072 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0058 | 0.0058 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0058 | 0.0058 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0104 | -0.0104 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0104 | -0.0104 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0075 | 0.0075 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0075 | 0.0075 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/gcd
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0121 | 0.0121 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0052 | 0.0052 | 0.0000 (0.0000%) ⭕ |
design__core__area | 67039.3000 | 67039.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 78425.2000 | 78425.2000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 4499.3200 | 4499.3200 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0076 | 0.0076 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0076 | 0.0076 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0121 | 0.0121 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0121 | 0.0121 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0092 | 0.0092 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0092 | 0.0092 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0052 | 0.0052 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0052 | 0.0052 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0106 | 0.0106 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0106 | 0.0106 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0067 | 0.0067 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0067 | 0.0067 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0058 | 0.0058 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0058 | 0.0058 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0108 | 0.0108 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0108 | 0.0108 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0074 | 0.0074 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0074 | 0.0074 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/inverter
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 1051.0100 | 1051.0100 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
design__instance__area | 18.7680 | 18.7680 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/io_placer
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 1080000 | 1080000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 15 | 15 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 240 | 240 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch_bad
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch_good
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/manual_macro_placement_test
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
design__core__area | 80146.9000 | 80146.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 90000 | 90000 | 0 (0.0000%) ⭕ |
design__instance__area | 23540.6000 | 23540.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0354 | 0.0354 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0354 | 0.0354 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0143 | 0.0143 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0143 | 0.0143 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0140 | 0.0140 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0140 | 0.0140 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0202 | 0.0202 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0202 | 0.0202 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0193 | 0.0193 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0193 | 0.0193 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0198 | 0.0198 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0198 | 0.0198 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/s44
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.0055 | -0.0055 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.0115 | -0.0115 | 0.0000 (0.0000%) ⭕ |
design__core__area | 33280.7000 | 33280.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 39709.7000 | 39709.7000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 2611.2500 | 2611.2500 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0063 | -0.0063 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0063 | -0.0063 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0115 | -0.0115 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0115 | -0.0115 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0083 | -0.0083 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0083 | -0.0083 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0055 | -0.0055 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0055 | -0.0055 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0104 | -0.0104 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0104 | -0.0104 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0075 | -0.0075 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0075 | -0.0075 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0058 | -0.0058 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0058 | -0.0058 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0109 | -0.0109 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0109 | -0.0109 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0078 | -0.0078 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0078 | -0.0078 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/spm
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0228 | 0.0228 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0095 | 0.0095 | 0.0000 (0.0000%) ⭕ |
design__core__area | 8051.4700 | 8051.4700 | 0.0000 (0.0000%) ⭕ |
design__die__area | 11317.8000 | 11317.8000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 3590.9400 | 3590.9400 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0017 | 0.0017 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0011 | 0.0011 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0144 | 0.0144 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0144 | 0.0144 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0228 | 0.0228 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0228 | 0.0228 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0172 | 0.0172 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0172 | 0.0172 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0095 | 0.0095 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0095 | 0.0095 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0170 | 0.0170 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0170 | 0.0170 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0122 | 0.0122 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0122 | 0.0122 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0110 | 0.0110 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0110 | 0.0110 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0190 | 0.0190 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0190 | 0.0190 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0138 | 0.0138 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0138 | 0.0138 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/test_sram_macro
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 18 | 18 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 18 | 18 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.1393 | -0.1393 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.4395 | -0.4395 | 0.0000 (0.0000%) ⭕ |
design__core__area | 906252 | 906252 | 0 (0.0000%) ⭕ |
design__die__area | 937500 | 937500 | 0 (0.0000%) ⭕ |
design__instance__area | 395673 | 395673 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 18 | 18 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 173 | 173 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 5666674 | 5666674 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0020 | 0.0020 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1393 | -0.1393 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.1393 | -0.1393 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 38 | 38 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.4395 | -0.4395 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.4395 | -0.4395 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 18 | 18 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 173 | 173 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2589 | -0.2589 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.2589 | -0.2589 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 105 | 105 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.1491 | -0.1491 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.1491 | -0.1491 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 24 | 24 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.3893 | -0.3893 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.3893 | -0.3893 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 130 | 130 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2436 | -0.2436 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.2436 | -0.2436 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 62 | 62 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1470 | -0.1470 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.1470 | -0.1470 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 33 | 33 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.4181 | -0.4181 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.4181 | -0.4181 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 148 | 148 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2566 | -0.2566 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.2566 | -0.2566 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 98 | 98 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.0287 | -0.0287 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.0632 | -0.0632 | 0.0000 (0.0000%) ⭕ |
design__core__area | 24891.4000 | 24891.4000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 30400.6000 | 30400.6000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 11969 | 11969 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0014 | 0.0014 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0325 | -0.0325 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0325 | -0.0325 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0632 | -0.0632 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0632 | -0.0632 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0416 | -0.0416 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0416 | -0.0416 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0287 | -0.0287 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0287 | -0.0287 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0575 | -0.0575 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0575 | -0.0575 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0369 | -0.0369 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0369 | -0.0369 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0302 | -0.0302 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0302 | -0.0302 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0602 | -0.0602 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0602 | -0.0602 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0389 | -0.0389 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0389 | -0.0389 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb_cdc_core
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0806 | 0.0806 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0339 | 0.0339 | 0.0000 (0.0000%) ⭕ |
design__core__area | 62620.1000 | 62620.1000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 71190.9000 | 71190.9000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 22366.5000 | 22366.5000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0015 | 0.0015 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0021 | 0.0021 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0381 | 0.0381 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0381 | 0.0381 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0806 | 0.0806 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0806 | 0.0806 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0496 | 0.0496 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0496 | 0.0496 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0339 | 0.0339 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0339 | 0.0339 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0728 | 0.0728 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0728 | 0.0728 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0445 | 0.0445 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0445 | 0.0445 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0765 | 0.0765 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0765 | 0.0765 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0467 | 0.0467 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0467 | 0.0467 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/user_proj_timer
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.0098 | -0.0098 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.0225 | -0.0225 | 0.0000 (0.0000%) ⭕ |
design__core__area | 655604 | 655604 | 0 (0.0000%) ⭕ |
design__die__area | 700000 | 700000 | 0 (0.0000%) ⭕ |
design__instance__area | 17767 | 17767 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 5 | 5 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0121 | -0.0121 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0121 | -0.0121 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0225 | -0.0225 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0225 | -0.0225 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0144 | -0.0144 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0144 | -0.0144 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0098 | -0.0098 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0098 | -0.0098 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0191 | -0.0191 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0191 | -0.0191 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0119 | -0.0119 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0119 | -0.0119 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0106 | -0.0106 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0106 | -0.0106 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0206 | -0.0206 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0206 | -0.0206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0128 | -0.0128 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0128 | -0.0128 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/wbqspiflash
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 3 | 3 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 3 | 3 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.3231 | 0.3231 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.1199 | 0.1199 | 0.0000 (0.0000%) ⭕ |
design__core__area | 74571.5000 | 74571.5000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 84643.5000 | 84643.5000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 27371.3000 | 27371.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 46 | 46 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 48 | 48 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0019 | 0.0019 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0029 | 0.0029 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0028 | 0.0028 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0058 | 0.0058 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.1262 | 0.1262 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1262 | 0.1262 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 46 | 46 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.3231 | 0.3231 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.3231 | 0.3231 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 46 | 46 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 48 | 48 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.1849 | 0.1849 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.1849 | 0.1849 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 46 | 46 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.1199 | 0.1199 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1199 | 0.1199 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 46 | 46 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.3090 | 0.3090 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.3090 | 0.3090 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 46 | 46 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 13 | 13 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.1760 | 0.1760 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.1760 | 0.1760 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 46 | 46 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.1228 | 0.1228 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1228 | 0.1228 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 46 | 46 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.3156 | 0.3156 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.3156 | 0.3156 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 46 | 46 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 25 | 25 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.1803 | 0.1803 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.1803 | 0.1803 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 46 | 46 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/xtea
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0572 | 0.0572 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0235 | 0.0235 | 0.0000 (0.0000%) ⭕ |
design__core__area | 46358.2000 | 46358.2000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 54022.9000 | 54022.9000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 24113.1000 | 24113.1000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 11 | 11 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0041 | 0.0041 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0082 | 0.0082 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0099 | 0.0099 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0180 | 0.0180 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -211.4914 | -211.4914 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -6.8976 | -6.8976 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 187 | 187 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 187 | 187 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0276 | 0.0276 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0276 | 0.0276 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0572 | 0.0572 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0572 | 0.0572 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 11 | 11 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | -211.4914 | -211.4914 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | -6.8976 | -6.8976 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 63 | 63 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 63 | 63 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0362 | 0.0362 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0362 | 0.0362 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0235 | 0.0235 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0235 | 0.0235 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0498 | 0.0498 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0498 | 0.0498 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | -194.9052 | -194.9052 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | -6.6469 | -6.6469 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 62 | 62 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 62 | 62 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0312 | 0.0312 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0312 | 0.0312 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0252 | 0.0252 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0252 | 0.0252 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0529 | 0.0529 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0529 | 0.0529 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | -202.9236 | -202.9236 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | -6.7582 | -6.7582 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 62 | 62 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 62 | 62 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0335 | 0.0335 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0335 | 0.0335 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/zipdiv
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.0344 | -0.0344 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -0.0757 | -0.0757 | 0.0000 (0.0000%) ⭕ |
design__core__area | 29796.1000 | 29796.1000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 36193 | 36193 | 0 (0.0000%) ⭕ |
design__instance__area | 13067.5000 | 13067.5000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 16 | 16 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 12 | 12 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0388 | -0.0388 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0388 | -0.0388 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 16 | 16 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0757 | -0.0757 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0757 | -0.0757 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 16 | 16 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0502 | -0.0502 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0502 | -0.0502 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 16 | 16 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0344 | -0.0344 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0344 | -0.0344 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 16 | 16 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0689 | -0.0689 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0689 | -0.0689 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 16 | 16 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0450 | -0.0450 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0450 | -0.0450 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 16 | 16 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0360 | -0.0360 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0360 | -0.0360 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 16 | 16 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0717 | -0.0717 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0717 | -0.0717 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 16 | 16 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0470 | -0.0470 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0470 | -0.0470 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 16 | 16 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |