gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/APU
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.2297 | 0.2251 | -0.0047 (-2.0277%) ❗ |
design__max_cap_violation__count | 14 | 16 | 2 (+14.2857%) ❗ |
design__max_slew_violation__count | 10 | 34 | 24 (+240.0000%) ❗ |
ir__drop__avg | 0.0000 | 0.0001 | 0.0000 (+15.1724%) ❗ |
ir__drop__worst | 0.0002 | 0.0003 | 0.0001 (+45.4545%) ❗ |
power__internal__total | 0.0103 | 0.0112 | 0.0009 (+9.0971%) ❗ |
power__switching__total | 0.0054 | 0.0068 | 0.0015 (+27.1213%) ❗ |
power__total | 0.0157 | 0.0180 | 0.0024 (+15.2948%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2428 | 0.2373 | -0.0056 (-2.3015%) ❗ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.6566 | 0.6278 | -0.0288 (-4.3912%) ❗ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 14 | 16 | 2 (+14.2857%) ❗ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 10 | 34 | 24 (+240.0000%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.3707 | 0.3578 | -0.0129 (-3.4872%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2297 | 0.2251 | -0.0047 (-2.0277%) ❗ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.6257 | 0.6057 | -0.0200 (-3.2030%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.3522 | 0.3421 | -0.0100 (-2.8474%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2357 | 0.2307 | -0.0050 (-2.1369%) ❗ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.6399 | 0.6147 | -0.0252 (-3.9439%) ❗ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 10 | 30 | 20 (+200.0000%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.3606 | 0.3493 | -0.0113 (-3.1333%) ❗ |
clock__skew__worst_hold | 0.6566 | 0.6278 | -0.0288 (-4.3912%) ⭕ |
design__instance__area | 112458 | 103903 | -8555 (-7.6073%) ⭕ |
design__max_fanout_violation__count | 167 | 146 | -21 (-12.5749%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-5.7061%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.2428 | 0.2373 | -0.0056 (-2.3015%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 167 | 146 | -21 (-12.5749%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.6566 | 0.6278 | -0.0288 (-4.3912%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 167 | 146 | -21 (-12.5749%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.3707 | 0.3578 | -0.0129 (-3.4872%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 167 | 146 | -21 (-12.5749%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.2297 | 0.2251 | -0.0047 (-2.0277%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 10 | 9 | -1 (-10.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 167 | 146 | -21 (-12.5749%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.6257 | 0.6057 | -0.0200 (-3.2030%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 11 | 9 | -2 (-18.1818%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 167 | 146 | -21 (-12.5749%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 10 | 8 | -2 (-20.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.3522 | 0.3421 | -0.0100 (-2.8474%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 10 | 9 | -1 (-10.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 167 | 146 | -21 (-12.5749%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.2357 | 0.2307 | -0.0050 (-2.1369%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 12 | 10 | -2 (-16.6667%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 167 | 146 | -21 (-12.5749%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.6399 | 0.6147 | -0.0252 (-3.9439%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 13 | 11 | -2 (-15.3846%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 167 | 146 | -21 (-12.5749%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.3606 | 0.3493 | -0.0113 (-3.1333%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 12 | 10 | -2 (-16.6667%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 167 | 146 | -21 (-12.5749%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 289314 | 289314 | 0 (0.0000%) ⭕ |
design__die__area | 315191 | 315191 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/blink
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | 0.0000 | -0.8788 | -0.8788 |
timing__setup__wns | 0.0000 | -0.5067 | -0.5067 |
timing__setup_r2r_vio__count | 0 | 6 | 6 |
timing__setup_vio__count | 0 | 6 | 6 |
timing__setup__tns__corner:max_ss_125C_4v50 | 0.0000 | -0.8788 | -0.8788 |
timing__setup__wns__corner:max_ss_125C_4v50 | 0.0000 | -0.5067 | -0.5067 |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 2 | 2 |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 2 | 2 |
timing__setup__tns__corner:min_ss_125C_4v50 | 0.0000 | -0.4552 | -0.4552 |
timing__setup__wns__corner:min_ss_125C_4v50 | 0.0000 | -0.2738 | -0.2738 |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 2 | 2 |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 2 | 2 |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0.0000 | -0.6475 | -0.6475 |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0.0000 | -0.3797 | -0.3797 |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 2 | 2 |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 2 | 2 |
clock__skew__worst_hold | -0.0016 | 0.0106 | 0.0122 (-781.5384%) ❗ |
power__internal__total | 0.0028 | 0.0028 | 0.0000 (+0.1091%) ❗ |
power__switching__total | 0.0006 | 0.0006 | 0.0000 (+1.0358%) ❗ |
power__total | 0.0034 | 0.0034 | 0.0000 (+0.2671%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.0023 | 0.0039 | 0.0063 (-270.4313%) ❗ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.0049 | 0.0106 | 0.0156 (-314.9365%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.0031 | 0.0060 | 0.0091 (-293.0980%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.0016 | 0.0026 | 0.0041 (-265.5282%) ❗ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.0033 | 0.0071 | 0.0103 (-316.2886%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.0021 | 0.0040 | 0.0060 (-291.0061%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.0019 | 0.0032 | 0.0051 (-268.3842%) ❗ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.0040 | 0.0087 | 0.0128 (-315.4614%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.0026 | 0.0049 | 0.0075 (-292.0765%) ❗ |
clock__skew__worst_setup | -0.0049 | 0.0026 | 0.0075 (-152.2025%) ⭕ |
design__instance__area | 4201.6100 | 3896.4800 | -305.1300 (-7.2622%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | -0.0000 (-12.9252%) ⭕ |
ir__drop__worst | 0.0012 | 0.0008 | -0.0004 (-31.2712%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-9.5620%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.0023 | 0.0039 | 0.0063 (-270.4313%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.0049 | 0.0106 | 0.0156 (-314.9365%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.0031 | 0.0060 | 0.0091 (-293.0980%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | -0.0016 | 0.0026 | 0.0041 (-265.5282%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.0033 | 0.0071 | 0.0103 (-316.2886%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.0021 | 0.0040 | 0.0060 (-291.0061%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.0019 | 0.0032 | 0.0051 (-268.3842%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.0040 | 0.0087 | 0.0128 (-315.4614%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.0026 | 0.0049 | 0.0075 (-292.0765%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 6868.7800 | 6868.7800 | 0.0000 (0.0000%) ⭕ |
design__die__area | 11201.3000 | 11201.3000 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/cell_inverter
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 8.7808 | 8.7808 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/inverter
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 570.7520 | 570.7520 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
design__instance__area | 57.0752 | 57.0752 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch_bad
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch_good
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/spm
Metric | Before | After | Delta |
---|---|---|---|
ir__drop__avg | 0.0004 | 0.0005 | 0.0000 (+6.7416%) ❗ |
ir__drop__worst | 0.0012 | 0.0015 | 0.0004 (+29.4118%) ❗ |
power__switching__total | 0.0021 | 0.0023 | 0.0001 (+6.2720%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.0064 | -0.0042 | 0.0021 (-33.5993%) ❗ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.0168 | -0.0108 | 0.0060 (-35.8892%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.0096 | -0.0063 | 0.0033 (-34.7074%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.0051 | -0.0036 | -0.0087 (-169.6740%) ❗ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.0126 | -0.0090 | 0.0036 (-28.3856%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.0072 | -0.0053 | 0.0019 (-26.9345%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.0057 | -0.0039 | -0.0095 (-168.0060%) ❗ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.0146 | -0.0098 | 0.0047 (-32.5449%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.0083 | -0.0057 | 0.0026 (-31.2391%) ❗ |
clock__skew__worst_hold | 0.0057 | -0.0036 | -0.0092 (-162.6443%) ⭕ |
clock__skew__worst_setup | -0.0168 | -0.0108 | 0.0060 (-35.8892%) ⭕ |
design__instance__area | 11691.6000 | 11461.1000 | -230.5000 (-1.9715%) ⭕ |
power__internal__total | 0.0072 | 0.0069 | -0.0003 (-4.3858%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-0.4647%) ⭕ |
power__total | 0.0093 | 0.0091 | -0.0002 (-1.9434%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.0064 | -0.0042 | 0.0021 (-33.5993%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.0168 | -0.0108 | 0.0060 (-35.8892%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.0096 | -0.0063 | 0.0033 (-34.7074%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.0051 | -0.0036 | -0.0087 (-169.6740%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.0126 | -0.0090 | 0.0036 (-28.3856%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.0072 | -0.0053 | 0.0019 (-26.9345%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.0057 | -0.0039 | -0.0095 (-168.0060%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.0146 | -0.0098 | 0.0047 (-32.5449%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.0083 | -0.0057 | 0.0026 (-31.2391%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 21280.3000 | 21280.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 28670.3000 | 28670.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | 0.0000 | -9.4926 | -9.4926 |
timing__setup__wns | 0.0000 | -0.9565 | -0.9565 |
timing__setup_r2r_vio__count | 0 | 39 | 39 |
timing__setup_vio__count | 0 | 42 | 42 |
timing__setup__tns__corner:max_ss_125C_4v50 | 0.0000 | -9.4926 | -9.4926 |
timing__setup__wns__corner:max_ss_125C_4v50 | 0.0000 | -0.9565 | -0.9565 |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 20 | 20 |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 21 | 21 |
timing__setup__tns__corner:min_ss_125C_4v50 | 0.0000 | -0.6195 | -0.6195 |
timing__setup__wns__corner:min_ss_125C_4v50 | 0.0000 | -0.6195 | -0.6195 |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 1 | 1 |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0.0000 | -2.5034 | -2.5034 |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0.0000 | -0.7738 | -0.7738 |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 19 | 19 |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 20 | 20 |
clock__skew__worst_setup | -0.0448 | -0.0662 | -0.0214 (+47.9048%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.1908%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.0186 | -0.0239 | -0.0053 (+28.2345%) ❗ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.0448 | -0.0662 | -0.0214 (+47.9048%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.0270 | -0.0374 | -0.0105 (+38.7417%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | -0.0146 | -0.0191 | -0.0045 (+30.9050%) ❗ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.0350 | -0.0523 | -0.0174 (+49.7137%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.0211 | -0.0298 | -0.0087 (+40.9968%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.0165 | -0.0213 | -0.0047 (+28.6784%) ❗ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.0397 | -0.0587 | -0.0190 (+47.8587%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.0239 | -0.0333 | -0.0093 (+38.9472%) ❗ |
clock__skew__worst_hold | -0.0146 | -0.0191 | -0.0045 (+30.9050%) ⭕ |
design__instance__area | 31231.1000 | 30339.9000 | -891.2000 (-2.8536%) ⭕ |
design__max_fanout_violation__count | 14 | 13 | -1 (-7.1429%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | -0.0000 (-4.3796%) ⭕ |
ir__drop__worst | 0.0009 | 0.0008 | -0.0000 (-4.1332%) ⭕ |
power__internal__total | 0.0164 | 0.0153 | -0.0010 (-6.3223%) ⭕ |
power__switching__total | 0.0059 | 0.0059 | -0.0000 (-0.7714%) ⭕ |
power__total | 0.0223 | 0.0212 | -0.0011 (-4.8517%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.0186 | -0.0239 | -0.0053 (+28.2345%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 14 | 13 | -1 (-7.1429%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.0448 | -0.0662 | -0.0214 (+47.9048%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 14 | 13 | -1 (-7.1429%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.0270 | -0.0374 | -0.0105 (+38.7417%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 14 | 13 | -1 (-7.1429%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.0146 | -0.0191 | -0.0045 (+30.9050%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 14 | 13 | -1 (-7.1429%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.0350 | -0.0523 | -0.0174 (+49.7137%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 14 | 13 | -1 (-7.1429%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.0211 | -0.0298 | -0.0087 (+40.9968%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 14 | 13 | -1 (-7.1429%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.0165 | -0.0213 | -0.0047 (+28.6784%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 14 | 13 | -1 (-7.1429%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.0397 | -0.0587 | -0.0190 (+47.8587%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 14 | 13 | -1 (-7.1429%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.0239 | -0.0333 | -0.0093 (+38.9472%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 14 | 13 | -1 (-7.1429%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 60989.2000 | 60989.2000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 72485.3000 | 72485.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb_cdc_core
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | -93.4855 | -209.8902 | -116.4047 (+124.5163%) |
timing__setup__wns | -3.1421 | -6.0603 | -2.9181 (+92.8709%) |
timing__setup_r2r_vio__count | 175 | 316 | 141 (+80.5714%) |
timing__setup_vio__count | 208 | 349 | 141 (+67.7885%) |
timing__setup__tns__corner:max_ss_125C_4v50 | -93.4855 | -209.8902 | -116.4047 (+124.5163%) |
timing__setup__wns__corner:max_ss_125C_4v50 | -3.1421 | -6.0603 | -2.9181 (+92.8709%) |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 63 | 127 | 64 (+101.5873%) |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 74 | 138 | 64 (+86.4865%) |
timing__setup__tns__corner:min_ss_125C_4v50 | -72.7072 | -162.0056 | -89.2984 (+122.8193%) |
timing__setup__wns__corner:min_ss_125C_4v50 | -2.8096 | -5.5332 | -2.7236 (+96.9367%) |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 55 | 78 | 23 (+41.8182%) |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 66 | 89 | 23 (+34.8485%) |
timing__setup__tns__corner:nom_ss_125C_4v50 | -81.7656 | -179.8416 | -98.0760 (+119.9479%) |
timing__setup__wns__corner:nom_ss_125C_4v50 | -2.9613 | -5.7738 | -2.8125 (+94.9750%) |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 57 | 111 | 54 (+94.7368%) |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 68 | 122 | 54 (+79.4118%) |
clock__skew__worst_setup | 0.2038 | 0.1914 | -0.0124 (-6.0640%) ❗ |
ir__drop__worst | 0.0014 | 0.0019 | 0.0004 (+28.2759%) ❗ |
power__switching__total | 0.0206 | 0.0226 | 0.0020 (+9.9532%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2128 | 0.1965 | -0.0163 (-7.6431%) ❗ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.5828 | 0.5506 | -0.0322 (-5.5214%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.3271 | 0.3056 | -0.0215 (-6.5774%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2038 | 0.1914 | -0.0124 (-6.0640%) ❗ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.5617 | 0.5372 | -0.0246 (-4.3727%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.3144 | 0.2979 | -0.0165 (-5.2408%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2080 | 0.1938 | -0.0142 (-6.8322%) ❗ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.5714 | 0.5433 | -0.0280 (-4.9084%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.3204 | 0.3015 | -0.0189 (-5.9026%) ❗ |
clock__skew__worst_hold | 0.5828 | 0.5506 | -0.0322 (-5.5214%) ⭕ |
design__instance__area | 73594.1000 | 68086.3000 | -5507.8000 (-7.4840%) ⭕ |
design__max_fanout_violation__count | 77 | 66 | -11 (-14.2857%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | -0.0000 (-5.3269%) ⭕ |
power__internal__total | 0.0574 | 0.0544 | -0.0029 (-5.1313%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-8.5468%) ⭕ |
power__total | 0.0779 | 0.0770 | -0.0009 (-1.1468%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.2128 | 0.1965 | -0.0163 (-7.6431%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 77 | 66 | -11 (-14.2857%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.5828 | 0.5506 | -0.0322 (-5.5214%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 77 | 66 | -11 (-14.2857%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.3271 | 0.3056 | -0.0215 (-6.5774%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 77 | 66 | -11 (-14.2857%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.2038 | 0.1914 | -0.0124 (-6.0640%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 77 | 66 | -11 (-14.2857%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.5617 | 0.5372 | -0.0246 (-4.3727%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 77 | 66 | -11 (-14.2857%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.3144 | 0.2979 | -0.0165 (-5.2408%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 77 | 66 | -11 (-14.2857%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.2080 | 0.1938 | -0.0142 (-6.8322%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 77 | 66 | -11 (-14.2857%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.5714 | 0.5433 | -0.0280 (-4.9084%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 77 | 66 | -11 (-14.2857%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.3204 | 0.3015 | -0.0189 (-5.9026%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 77 | 66 | -11 (-14.2857%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 157861 | 157861 | 0 (0.0000%) ⭕ |
design__die__area | 177413 | 177413 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/wbqspiflash
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | -500.9202 | -967.1923 | -466.2721 (+93.0831%) |
timing__setup__wns | -4.9735 | -7.6832 | -2.7096 (+54.4803%) |
timing__setup_r2r_vio__count | 446 | 567 | 121 (+27.1300%) |
timing__setup_vio__count | 446 | 570 | 124 (+27.8027%) |
timing__setup__tns__corner:max_ss_125C_4v50 | -500.9202 | -967.1923 | -466.2721 (+93.0831%) |
timing__setup__wns__corner:max_ss_125C_4v50 | -4.9735 | -7.6832 | -2.7096 (+54.4803%) |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 149 | 190 | 41 (+27.5168%) |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 149 | 191 | 42 (+28.1879%) |
timing__setup__tns__corner:min_ss_125C_4v50 | -417.1571 | -822.7727 | -405.6156 (+97.2333%) |
timing__setup__wns__corner:min_ss_125C_4v50 | -4.0878 | -6.7058 | -2.6181 (+64.0459%) |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 148 | 187 | 39 (+26.3514%) |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 148 | 188 | 40 (+27.0270%) |
timing__setup__tns__corner:nom_ss_125C_4v50 | -455.1385 | -887.9757 | -432.8372 (+95.1001%) |
timing__setup__wns__corner:nom_ss_125C_4v50 | -4.4888 | -7.1476 | -2.6588 (+59.2330%) |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 149 | 190 | 41 (+27.5168%) |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 149 | 191 | 42 (+28.1879%) |
clock__skew__worst_hold | 0.4961 | 0.5895 | 0.0935 (+18.8435%) ❗ |
design__max_cap_violation__count | 2 | 4 | 2 (+100.0000%) ❗ |
design__max_fanout_violation__count | 0 | 8 | 8 ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.1808 | 0.2133 | 0.0326 (+18.0176%) ❗ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 4 | 3 (+300.0000%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 0 | 8 | 8 ❗ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.4961 | 0.5895 | 0.0935 (+18.8435%) ❗ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 2 | 4 | 2 (+100.0000%) ❗ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 0 | 8 | 8 ❗ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.2781 | 0.3295 | 0.0514 (+18.4752%) ❗ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 4 | 3 (+300.0000%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 0 | 8 | 8 ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.1754 | 0.2049 | 0.0295 (+16.8102%) ❗ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 4 | 3 (+300.0000%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 0 | 8 | 8 ❗ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.4836 | 0.5672 | 0.0836 (+17.2910%) ❗ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 4 | 3 (+300.0000%) ❗ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 0 | 8 | 8 ❗ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.2705 | 0.3167 | 0.0462 (+17.0802%) ❗ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 4 | 3 (+300.0000%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 0 | 8 | 8 ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.1779 | 0.2087 | 0.0309 (+17.3476%) ❗ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 4 | 3 (+300.0000%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 0 | 8 | 8 ❗ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.4893 | 0.5773 | 0.0881 (+17.9988%) ❗ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 4 | 3 (+300.0000%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 0 | 8 | 8 ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.2740 | 0.3225 | 0.0485 (+17.7093%) ❗ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 4 | 3 (+300.0000%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 0 | 8 | 8 ❗ |
clock__skew__worst_setup | 0.1754 | 0.2049 | 0.0295 (+16.8102%) ⭕ |
design__instance__area | 70804.0000 | 61915.6000 | -8888.4000 (-12.5535%) ⭕ |
ir__drop__avg | 0.0013 | 0.0010 | -0.0003 (-23.7302%) ⭕ |
ir__drop__worst | 0.0024 | 0.0024 | -0.0001 (-2.8926%) ⭕ |
power__internal__total | 0.1103 | 0.0803 | -0.0300 (-27.1755%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-10.7074%) ⭕ |
power__switching__total | 0.0803 | 0.0689 | -0.0114 (-14.2034%) ⭕ |
power__total | 0.1906 | 0.1492 | -0.0414 (-21.7082%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.1808 | 0.2133 | 0.0326 (+18.0176%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.4961 | 0.5895 | 0.0935 (+18.8435%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2781 | 0.3295 | 0.0514 (+18.4752%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.1754 | 0.2049 | 0.0295 (+16.8102%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.4836 | 0.5672 | 0.0836 (+17.2910%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 2 | 0 | -2 (-100.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2705 | 0.3167 | 0.0462 (+17.0802%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.1779 | 0.2087 | 0.0309 (+17.3476%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.4893 | 0.5773 | 0.0881 (+17.9988%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2740 | 0.3225 | 0.0485 (+17.7093%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 104224 | 104224 | 0 (0.0000%) ⭕ |
design__die__area | 120173 | 120173 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/zipdiv
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | -226.0773 | -513.2404 | -287.1631 (+127.0199%) |
timing__setup__wns | -4.8313 | -9.2270 | -4.3957 (+90.9853%) |
timing__setup_r2r_vio__count | 186 | 317 | 131 (+70.4301%) |
timing__setup_vio__count | 186 | 419 | 233 (+125.2688%) |
timing__setup__tns__corner:max_ss_125C_4v50 | -226.0773 | -513.2404 | -287.1631 (+127.0199%) |
timing__setup__wns__corner:max_ss_125C_4v50 | -4.8313 | -9.2270 | -4.3957 (+90.9853%) |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 63 | 82 | 19 (+30.1587%) |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 63 | 119 | 56 (+88.8889%) |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | -10.4045 | -10.4045 |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | -0.5289 | -0.5289 |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 33 | 33 |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 33 | 33 |
timing__setup__tns__corner:min_ss_125C_4v50 | -207.2639 | -451.8994 | -244.6355 (+118.0309%) |
timing__setup__wns__corner:min_ss_125C_4v50 | -4.4112 | -8.5345 | -4.1233 (+93.4745%) |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 61 | 82 | 21 (+34.4262%) |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 61 | 110 | 49 (+80.3279%) |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | -0.2524 | -0.2524 |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | -0.1354 | -0.1354 |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 8 | 8 |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 8 | 8 |
timing__setup__tns__corner:nom_ss_125C_4v50 | -215.7482 | -479.1826 | -263.4344 (+122.1027%) |
timing__setup__wns__corner:nom_ss_125C_4v50 | -4.5978 | -8.8486 | -4.2508 (+92.4517%) |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 62 | 82 | 20 (+32.2581%) |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 62 | 119 | 57 (+91.9355%) |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | -3.8501 | -3.8501 |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | -0.3140 | -0.3140 |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 30 | 30 |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 30 | 30 |
clock__skew__worst_setup | -0.0546 | -0.0602 | -0.0056 (+10.3097%) ❗ |
design__instance__area | 36176.9000 | 36532.5000 | 355.6000 (+0.9829%) ❗ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (+2.0672%) ❗ |
ir__drop__worst | 0.0014 | 0.0018 | 0.0004 (+28.2609%) ❗ |
power__internal__total | 0.0206 | 0.0216 | 0.0010 (+4.8188%) ❗ |
power__switching__total | 0.0112 | 0.0128 | 0.0016 (+14.6102%) ❗ |
power__total | 0.0317 | 0.0344 | 0.0026 (+8.2646%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.0230 | -0.0258 | -0.0028 (+12.1053%) ❗ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.0546 | -0.0602 | -0.0056 (+10.3097%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.0330 | -0.0367 | -0.0037 (+11.0499%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | -0.0194 | -0.0194 | -0.0000 (+0.0370%) ❗ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.0468 | -0.0478 | -0.0010 (+2.1969%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.0280 | -0.0282 | -0.0002 (+0.6793%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.0210 | -0.0223 | -0.0013 (+6.0526%) ❗ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.0503 | -0.0525 | -0.0022 (+4.3801%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.0303 | -0.0319 | -0.0015 (+5.0882%) ❗ |
clock__skew__worst_hold | -0.0194 | -0.0194 | -0.0000 (+0.0370%) ⭕ |
design__max_fanout_violation__count | 8 | 7 | -1 (-12.5000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-5.0321%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.0230 | -0.0258 | -0.0028 (+12.1053%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 8 | 7 | -1 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.0546 | -0.0602 | -0.0056 (+10.3097%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 8 | 7 | -1 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.0330 | -0.0367 | -0.0037 (+11.0499%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 8 | 7 | -1 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.0194 | -0.0194 | -0.0000 (+0.0370%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 8 | 7 | -1 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.0468 | -0.0478 | -0.0010 (+2.1969%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 8 | 7 | -1 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.0280 | -0.0282 | -0.0002 (+0.6793%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 8 | 7 | -1 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.0210 | -0.0223 | -0.0013 (+6.0526%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 8 | 7 | -1 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.0503 | -0.0525 | -0.0022 (+4.3801%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 8 | 7 | -1 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.0303 | -0.0319 | -0.0015 (+5.0882%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 8 | 7 | -1 (-12.5000%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 78085.5000 | 78085.5000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 92022.9000 | 92022.9000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/APU
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.1293 | 0.1278 | -0.0015 (-1.1817%) ❗ |
ir__drop__avg | 0.0001 | 0.0002 | 0.0001 (+74.0385%) ❗ |
ir__drop__worst | 0.0009 | 0.0010 | 0.0001 (+14.5833%) ❗ |
power__internal__total | 0.0023 | 0.0028 | 0.0005 (+20.7078%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+6.5022%) ❗ |
power__switching__total | 0.0013 | 0.0022 | 0.0009 (+66.3606%) ❗ |
power__total | 0.0036 | 0.0050 | 0.0014 (+37.1575%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1388 | 0.1333 | -0.0055 (-3.9662%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.3638 | 0.3541 | -0.0098 (-2.6834%) ❗ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 4 | 7 | 3 (+75.0000%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2041 | 0.1974 | -0.0067 (-3.2797%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1293 | 0.1278 | -0.0015 (-1.1817%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.3424 | 0.3408 | -0.0016 (-0.4598%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.1911 | 0.1900 | -0.0010 (-0.5461%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1335 | 0.1304 | -0.0031 (-2.3196%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.3515 | 0.3471 | -0.0043 (-1.2355%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.1967 | 0.1938 | -0.0029 (-1.4873%) ❗ |
antenna__violating__nets | 3 | 0 | -3 (-100.0000%) ⭕ |
antenna__violating__pins | 4 | 0 | -4 (-100.0000%) ⭕ |
clock__skew__worst_hold | 0.3638 | 0.3541 | -0.0098 (-2.6834%) ⭕ |
design__instance__area | 32909.1000 | 32457.4000 | -451.7000 (-1.3726%) ⭕ |
design__max_fanout_violation__count | 46 | 45 | -1 (-2.1739%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.1388 | 0.1333 | -0.0055 (-3.9662%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 46 | 45 | -1 (-2.1739%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.3638 | 0.3541 | -0.0098 (-2.6834%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 46 | 45 | -1 (-2.1739%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.2041 | 0.1974 | -0.0067 (-3.2797%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 46 | 45 | -1 (-2.1739%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.1293 | 0.1278 | -0.0015 (-1.1817%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 46 | 45 | -1 (-2.1739%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.3424 | 0.3408 | -0.0016 (-0.4598%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 46 | 45 | -1 (-2.1739%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 7 | 0 | -7 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.1911 | 0.1900 | -0.0010 (-0.5461%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 46 | 45 | -1 (-2.1739%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.1335 | 0.1304 | -0.0031 (-2.3196%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 46 | 45 | -1 (-2.1739%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.3515 | 0.3471 | -0.0043 (-1.2355%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 46 | 45 | -1 (-2.1739%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 7 | 0 | -7 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.1967 | 0.1938 | -0.0029 (-1.4873%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 46 | 45 | -1 (-2.1739%) ⭕ |
design__core__area | 83157.3000 | 83157.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 92959.7000 | 92959.7000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 7 | 7 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_GPIO
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.0013 | -0.0009 | -0.0022 (-174.7146%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0020 | -0.0009 | -0.0030 (-146.5372%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0028 | -0.0009 | -0.0037 (-131.3174%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0023 | -0.0009 | -0.0032 (-139.5706%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0013 | -0.0003 | -0.0015 (-122.9481%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0017 | -0.0003 | -0.0020 (-115.6830%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0015 | -0.0003 | -0.0018 (-119.0093%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0015 | -0.0004 | -0.0019 (-129.0142%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0021 | -0.0004 | -0.0025 (-119.1256%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0018 | -0.0004 | -0.0022 (-124.1367%) ❗ |
clock__skew__worst_hold | 0.0028 | -0.0003 | -0.0031 (-109.5290%) ⭕ |
design__instance__area | 1372.5700 | 1302.5000 | -70.0700 (-5.1050%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | -0.0000 (-3.9832%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | -0.0000 (-15.3846%) ⭕ |
power__internal__total | 0.0002 | 0.0002 | -0.0000 (-13.8677%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-2.9985%) ⭕ |
power__switching__total | 0.0001 | 0.0001 | -0.0000 (-1.3169%) ⭕ |
power__total | 0.0003 | 0.0003 | -0.0000 (-10.4240%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0020 | -0.0009 | -0.0030 (-146.5372%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0028 | -0.0009 | -0.0037 (-131.3174%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0023 | -0.0009 | -0.0032 (-139.5706%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0013 | -0.0003 | -0.0015 (-122.9481%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0017 | -0.0003 | -0.0020 (-115.6830%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0015 | -0.0003 | -0.0018 (-119.0093%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0015 | -0.0004 | -0.0019 (-129.0142%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0021 | -0.0004 | -0.0025 (-119.1256%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0018 | -0.0004 | -0.0022 (-124.1367%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 1670.3500 | 1670.3500 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2700.3500 | 2700.3500 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_PSRAM_CTRL_V2
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | 0.0000 | -0.0556 | -0.0556 |
timing__setup__wns | 0.0000 | -0.0556 | -0.0556 |
timing__setup_vio__count | 0 | 1 | 1 |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | -0.0556 | -0.0556 |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | -0.0556 | -0.0556 |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 1 | 1 |
clock__skew__worst_hold | 0.0095 | 0.0157 | 0.0062 (+65.3196%) ❗ |
design__instance__area | 5667.9400 | 5746.7600 | 78.8200 (+1.3906%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+19.7380%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0052 | 0.0090 | 0.0038 (+74.4452%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0095 | 0.0157 | 0.0062 (+65.3196%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0060 | 0.0106 | 0.0046 (+76.7279%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0031 | 0.0062 | 0.0031 (+101.7254%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0069 | 0.0126 | 0.0057 (+81.6753%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0037 | 0.0075 | 0.0038 (+101.9040%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0037 | 0.0071 | 0.0033 (+89.5524%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0081 | 0.0139 | 0.0059 (+72.7768%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0045 | 0.0086 | 0.0041 (+89.9614%) ❗ |
clock__skew__worst_setup | 0.0031 | 0.0062 | 0.0031 (+101.7254%) ⭕ |
ir__drop__avg | 0.0003 | 0.0002 | -0.0001 (-31.5436%) ⭕ |
ir__drop__worst | 0.0010 | 0.0008 | -0.0002 (-22.8000%) ⭕ |
power__internal__total | 0.0008 | 0.0006 | -0.0002 (-27.1517%) ⭕ |
power__switching__total | 0.0009 | 0.0006 | -0.0003 (-34.0350%) ⭕ |
power__total | 0.0018 | 0.0012 | -0.0006 (-30.7823%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0052 | 0.0090 | 0.0038 (+74.4452%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0095 | 0.0157 | 0.0062 (+65.3196%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0060 | 0.0106 | 0.0046 (+76.7279%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0031 | 0.0062 | 0.0031 (+101.7254%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0069 | 0.0126 | 0.0057 (+81.6753%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0037 | 0.0075 | 0.0038 (+101.9040%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0037 | 0.0071 | 0.0033 (+89.5524%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0081 | 0.0139 | 0.0059 (+72.7768%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0045 | 0.0086 | 0.0041 (+89.9614%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 8051.4700 | 8051.4700 | 0.0000 (0.0000%) ⭕ |
design__die__area | 11311.4000 | 11311.4000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_TCC32
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | 0.0000 | -5.9680 | -5.9680 |
timing__setup__wns | 0.0000 | -1.7875 | -1.7875 |
timing__setup_vio__count | 0 | 18 | 18 |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | -5.9680 | -5.9680 |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | -1.7875 | -1.7875 |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 7 | 7 |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | -2.2685 | -2.2685 |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | -0.9713 | -0.9713 |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 5 | 5 |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | -4.1713 | -4.1713 |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | -1.4352 | -1.4352 |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 6 | 6 |
clock__skew__worst_hold | -0.0168 | 0.0248 | 0.0415 (-247.7352%) ❗ |
design__instance__area | 9311.4300 | 9424.0400 | 112.6100 (+1.2094%) ❗ |
design__max_fanout_violation__count | 2 | 3 | 1 (+50.0000%) ❗ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0001 (+14.3229%) ❗ |
ir__drop__worst | 0.0011 | 0.0014 | 0.0003 (+26.7857%) ❗ |
power__internal__total | 0.0013 | 0.0013 | 0.0000 (+2.6485%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+11.0373%) ❗ |
power__switching__total | 0.0009 | 0.0010 | 0.0000 (+4.8800%) ❗ |
power__total | 0.0022 | 0.0023 | 0.0001 (+3.5773%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0365 | 0.0151 | 0.0516 (-141.4138%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0470 | 0.0248 | 0.0718 (-152.6645%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0402 | 0.0180 | 0.0582 (-144.8563%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0168 | 0.0101 | 0.0269 (-160.1199%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0251 | -0.0208 | 0.0043 (-17.2910%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0185 | 0.0123 | 0.0308 (-166.7714%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0229 | 0.0122 | 0.0351 (-153.3422%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0308 | -0.0228 | 0.0081 (-26.2112%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0248 | 0.0148 | 0.0396 (-159.4910%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 3 | 1 (+50.0000%) ❗ |
antenna__violating__nets | 2 | 1 | -1 (-50.0000%) ⭕ |
antenna__violating__pins | 2 | 1 | -1 (-50.0000%) ⭕ |
clock__skew__worst_setup | -0.0470 | -0.0228 | 0.0243 (-51.6136%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0365 | 0.0151 | 0.0516 (-141.4138%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0470 | 0.0248 | 0.0718 (-152.6645%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0402 | 0.0180 | 0.0582 (-144.8563%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0168 | 0.0101 | 0.0269 (-160.1199%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0251 | -0.0208 | 0.0043 (-17.2910%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0185 | 0.0123 | 0.0308 (-166.7714%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0229 | 0.0122 | 0.0351 (-153.3422%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0308 | -0.0228 | 0.0081 (-26.2112%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0248 | 0.0148 | 0.0396 (-159.4910%) ⭕ |
design__core__area | 11369.7000 | 11369.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 15327.4000 | 15327.4000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_UART
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0282 | -0.0217 | 0.0065 (-23.0456%) ❗ |
design__max_fanout_violation__count | 20 | 27 | 7 (+35.0000%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+3.4530%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0340 | -0.0280 | 0.0060 (-17.6833%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 20 | 27 | 7 (+35.0000%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0670 | -0.0562 | 0.0108 (-16.1462%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 20 | 27 | 7 (+35.0000%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0459 | -0.0368 | 0.0091 (-19.7747%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 20 | 27 | 7 (+35.0000%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0282 | -0.0217 | 0.0065 (-23.0456%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 20 | 27 | 7 (+35.0000%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0560 | -0.0440 | 0.0120 (-21.4167%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 20 | 27 | 7 (+35.0000%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0383 | -0.0291 | 0.0092 (-23.9716%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 20 | 27 | 7 (+35.0000%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0309 | -0.0245 | 0.0064 (-20.8001%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 20 | 27 | 7 (+35.0000%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0611 | -0.0499 | 0.0112 (-18.3317%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 20 | 27 | 7 (+35.0000%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0417 | -0.0326 | 0.0090 (-21.6631%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 20 | 27 | 7 (+35.0000%) ❗ |
antenna__violating__nets | 5 | 4 | -1 (-20.0000%) ⭕ |
antenna__violating__pins | 5 | 4 | -1 (-20.0000%) ⭕ |
clock__skew__worst_setup | -0.0670 | -0.0562 | 0.0108 (-16.1462%) ⭕ |
design__instance__area | 19834.0000 | 18860.6000 | -973.4000 (-4.9077%) ⭕ |
ir__drop__avg | 0.0010 | 0.0005 | -0.0005 (-51.1765%) ⭕ |
ir__drop__worst | 0.0031 | 0.0016 | -0.0015 (-47.8827%) ⭕ |
power__internal__total | 0.0033 | 0.0021 | -0.0012 (-36.7455%) ⭕ |
power__switching__total | 0.0020 | 0.0008 | -0.0012 (-61.6019%) ⭕ |
power__total | 0.0053 | 0.0028 | -0.0024 (-46.0299%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0340 | -0.0280 | 0.0060 (-17.6833%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0670 | -0.0562 | 0.0108 (-16.1462%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0459 | -0.0368 | 0.0091 (-19.7747%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0282 | -0.0217 | 0.0065 (-23.0456%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0560 | -0.0440 | 0.0120 (-21.4167%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0383 | -0.0291 | 0.0092 (-23.9716%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0309 | -0.0245 | 0.0064 (-20.8001%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0611 | -0.0499 | 0.0112 (-18.3317%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0417 | -0.0326 | 0.0090 (-21.6631%) ⭕ |
design__core__area | 22434 | 22434 | 0 (0.0000%) ⭕ |
design__die__area | 27763.5000 | 27763.5000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_CLK_RST
Metric | Before | After | Delta |
---|---|---|---|
timing__hold__tns | 0.0000 | -1.3419 | -1.3419 |
timing__hold__wns | 0.0000 | -0.5520 | -0.5520 |
timing__hold_r2r_vio__count | 0 | 69 | 69 |
timing__hold_vio__count | 0 | 69 | 69 |
timing__setup__tns | 0.0000 | -0.3004 | -0.3004 |
timing__setup__wns | 0.0000 | -0.3004 | -0.3004 |
timing__setup_r2r_vio__count | 0 | 1 | 1 |
timing__setup_vio__count | 0 | 1 | 1 |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | -1.3419 | -1.3419 |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | -0.2194 | -0.2194 |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 65 | 65 |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 65 | 65 |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | -0.7924 | -0.7924 |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | -0.5520 | -0.5520 |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 2 | 2 |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 2 | 2 |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | -0.3004 | -0.3004 |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | -0.3004 | -0.3004 |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 1 | 1 |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 1 | 1 |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | -0.4582 | -0.4582 |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | -0.3036 | -0.3036 |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 2 | 2 |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 2 | 2 |
clock__skew__worst_hold | -0.7341 | -0.6870 | 0.0471 (-6.4181%) ❗ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (+0.3630%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.7409 | -0.6870 | 0.0539 (-7.2742%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -2.6369 | -2.4689 | 0.1681 (-6.3734%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -1.4197 | -1.3298 | 0.0899 (-6.3307%) ❗ |
clock__skew__worst_setup | -2.6342 | -2.4634 | 0.1708 (-6.4830%) ⭕ |
design__instance__area | 5215.0000 | 4764.5696 | -450.4304 (-8.6372%) ⭕ |
design__max_cap_violation__count | 2 | 0 | -2 (-100.0000%) ⭕ |
design__max_slew_violation__count | 133 | 0 | -133 (-100.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-16.6503%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | -0.0000 (-31.0885%) ⭕ |
power__total | 0.0001 | 0.0001 | -0.0000 (-8.8639%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.7347 | -0.6812 | 0.0534 (-7.2753%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -2.6319 | -2.4634 | 0.1685 (-6.4026%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 2 | 0 | -2 (-100.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 133 | 0 | -133 (-100.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -1.4171 | -1.3273 | 0.0899 (-6.3406%) ⭕ |
design__max_fanout_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_DMAC_AHBL
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | -79.4963 | -230.8924 | -151.3961 (+190.4443%) |
timing__setup__wns | -4.0882 | -10.4071 | -6.3189 (+154.5624%) |
timing__setup_r2r_vio__count | 0 | 31 | 31 |
timing__setup_vio__count | 87 | 255 | 168 (+193.1034%) |
timing__setup__tns__corner:max_ss_100C_1v60 | -79.4963 | -230.8924 | -151.3961 (+190.4443%) |
timing__setup__wns__corner:max_ss_100C_1v60 | -4.0882 | -10.4071 | -6.3189 (+154.5624%) |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 17 | 17 |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 29 | 80 | 51 (+175.8621%) |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | -12.3656 | -12.3656 |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | -1.6142 | -1.6142 |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 13 | 13 |
timing__setup__tns__corner:min_ss_100C_1v60 | -70.3514 | -209.5712 | -139.2198 (+197.8920%) |
timing__setup__wns__corner:min_ss_100C_1v60 | -3.7430 | -10.0030 | -6.2599 (+167.2429%) |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 7 | 7 |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 29 | 68 | 39 (+134.4828%) |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | -9.6475 | -9.6475 |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | -1.3839 | -1.3839 |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 12 | 12 |
timing__setup__tns__corner:nom_ss_100C_1v60 | -74.9984 | -219.8852 | -144.8868 (+193.1866%) |
timing__setup__wns__corner:nom_ss_100C_1v60 | -3.9246 | -10.2115 | -6.2869 (+160.1944%) |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 7 | 7 |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 29 | 70 | 41 (+141.3793%) |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | -11.0219 | -11.0219 |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | -1.5019 | -1.5019 |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 12 | 12 |
ir__drop__worst | 0.0013 | 0.0016 | 0.0003 (+21.5385%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+18.5151%) ❗ |
antenna__violating__nets | 1 | 0 | -1 (-100.0000%) ⭕ |
antenna__violating__pins | 1 | 0 | -1 (-100.0000%) ⭕ |
clock__skew__worst_hold | 1.8145 | 1.7234 | -0.0911 (-5.0211%) ⭕ |
clock__skew__worst_setup | 1.0219 | 1.2043 | 0.1824 (+17.8463%) ⭕ |
design__instance__area | 15324.7000 | 14311.2000 | -1013.5000 (-6.6135%) ⭕ |
design__max_slew_violation__count | 8 | 0 | -8 (-100.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | -0.0001 (-17.4041%) ⭕ |
power__internal__total | 0.0013 | 0.0012 | -0.0001 (-9.9939%) ⭕ |
power__switching__total | 0.0006 | 0.0005 | -0.0002 (-25.2943%) ⭕ |
power__total | 0.0019 | 0.0016 | -0.0003 (-14.9057%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.5986 | 0.5420 | -0.0566 (-9.4487%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 1.0570 | 1.2361 | 0.1792 (+16.9515%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 1.8145 | 1.7234 | -0.0911 (-5.0211%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 3.1627 | 3.9296 | 0.7670 (+24.2502%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 8 | 0 | -8 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.9383 | 0.8629 | -0.0754 (-8.0355%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 1.6482 | 1.9630 | 0.3148 (+19.1030%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.5759 | 0.5342 | -0.0417 (-7.2365%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 1.0219 | 1.2043 | 0.1824 (+17.8463%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 1.7513 | 1.7014 | -0.0499 (-2.8515%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 3.0623 | 3.8747 | 0.8124 (+26.5289%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 3 | 0 | -3 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.9036 | 0.8511 | -0.0525 (-5.8105%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 1.5914 | 1.9161 | 0.3247 (+20.4046%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.5868 | 0.5386 | -0.0482 (-8.2143%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 1.0405 | 1.2204 | 0.1800 (+17.2960%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 1.7820 | 1.7140 | -0.0681 (-3.8194%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 3.1164 | 3.9034 | 0.7870 (+25.2550%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 3 | 0 | -3 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.9203 | 0.8576 | -0.0627 (-6.8129%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 1.6209 | 1.9405 | 0.3195 (+19.7137%) ⭕ |
design__core__area | 19398.6000 | 19398.6000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 24521.5000 | 24521.5000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 12 | 12 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_SPI_XIP_CACHE
Metric | Before | After | Delta |
---|---|---|---|
timing__hold__tns | 0.0000 | -2.6558 | -2.6558 |
timing__hold__wns | 0.0000 | -0.3952 | -0.3952 |
timing__hold_vio__count | 0 | 21 | 21 |
timing__setup__tns | -56.5264 | -85.2211 | -28.6947 (+50.7634%) |
timing__setup__wns | -2.5397 | -3.0329 | -0.4931 (+19.4170%) |
timing__setup_vio__count | 96 | 159 | 63 (+65.6250%) |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | -2.6558 | -2.6558 |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | -0.3952 | -0.3952 |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 7 | 7 |
timing__setup__tns__corner:max_ss_100C_1v60 | -56.5264 | -85.2211 | -28.6947 (+50.7634%) |
timing__setup__wns__corner:max_ss_100C_1v60 | -2.5397 | -3.0329 | -0.4931 (+19.4170%) |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 32 | 53 | 21 (+65.6250%) |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | -1.4155 | -1.4155 |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | -0.2178 | -0.2178 |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 7 | 7 |
timing__setup__tns__corner:min_ss_100C_1v60 | -33.3136 | -55.4392 | -22.1256 (+66.4162%) |
timing__setup__wns__corner:min_ss_100C_1v60 | -1.5315 | -2.0324 | -0.5009 (+32.7064%) |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 32 | 53 | 21 (+65.6250%) |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | -2.1229 | -2.1229 |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | -0.3197 | -0.3197 |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 7 | 7 |
timing__setup__tns__corner:nom_ss_100C_1v60 | -45.0657 | -70.7838 | -25.7181 (+57.0681%) |
timing__setup__wns__corner:nom_ss_100C_1v60 | -2.0624 | -2.5636 | -0.5012 (+24.3013%) |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 32 | 53 | 21 (+65.6250%) |
antenna__violating__nets | 21 | 34 | 13 (+61.9048%) ❗ |
antenna__violating__pins | 29 | 41 | 12 (+41.3793%) ❗ |
clock__skew__worst_setup | 0.1546 | 0.0308 | -0.1238 (-80.0500%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+11.6547%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1664 | 0.0407 | -0.1258 (-75.5555%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.4376 | 0.0843 | -0.3532 (-80.7284%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2485 | 0.0560 | -0.1925 (-77.4662%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1546 | 0.0308 | -0.1238 (-80.0500%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.4088 | 0.0663 | -0.3425 (-83.7929%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2303 | 0.0427 | -0.1876 (-81.4547%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1590 | 0.0360 | -0.1230 (-77.3863%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.4203 | 0.0746 | -0.3457 (-82.2441%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2378 | 0.0495 | -0.1883 (-79.1838%) ❗ |
clock__skew__worst_hold | 0.4376 | 0.0843 | -0.3532 (-80.7284%) ⭕ |
design__instance__area | 148811 | 133991 | -14820 (-9.9589%) ⭕ |
design__max_cap_violation__count | 15 | 5 | -10 (-66.6667%) ⭕ |
design__max_fanout_violation__count | 208 | 182 | -26 (-12.5000%) ⭕ |
design__max_slew_violation__count | 149 | 58 | -91 (-61.0738%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | -0.0000 (-10.1754%) ⭕ |
ir__drop__worst | 0.0014 | 0.0011 | -0.0003 (-22.0588%) ⭕ |
power__internal__total | 0.0158 | 0.0151 | -0.0007 (-4.2498%) ⭕ |
power__switching__total | 0.0076 | 0.0066 | -0.0010 (-13.0492%) ⭕ |
power__total | 0.0234 | 0.0217 | -0.0017 (-7.1085%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.1664 | 0.0407 | -0.1258 (-75.5555%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 15 | 5 | -10 (-66.6667%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 208 | 182 | -26 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.4376 | 0.0843 | -0.3532 (-80.7284%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 14 | 5 | -9 (-64.2857%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 208 | 182 | -26 (-12.5000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 149 | 58 | -91 (-61.0738%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.2485 | 0.0560 | -0.1925 (-77.4662%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 14 | 5 | -9 (-64.2857%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 208 | 182 | -26 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.1546 | 0.0308 | -0.1238 (-80.0500%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 4 | 1 | -3 (-75.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 208 | 182 | -26 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.4088 | 0.0663 | -0.3425 (-83.7929%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 4 | 1 | -3 (-75.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 208 | 182 | -26 (-12.5000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 77 | 10 | -67 (-87.0130%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.2303 | 0.0427 | -0.1876 (-81.4547%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 4 | 1 | -3 (-75.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 208 | 182 | -26 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.1590 | 0.0360 | -0.1230 (-77.3863%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 7 | 5 | -2 (-28.5714%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 208 | 182 | -26 (-12.5000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.4203 | 0.0746 | -0.3457 (-82.2441%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 7 | 5 | -2 (-28.5714%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 208 | 182 | -26 (-12.5000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 126 | 20 | -106 (-84.1270%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.2378 | 0.0495 | -0.1883 (-79.1838%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 7 | 5 | -2 (-28.5714%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 208 | 182 | -26 (-12.5000%) ⭕ |
design__core__area | 208940 | 208940 | 0 (0.0000%) ⭕ |
design__die__area | 224462 | 224462 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_upw_new
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.3170 | -3.3170 | 0.0000 (-0.0001%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.3268 | 0.3268 | -0.0000 (-0.0005%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.5017 | -3.5017 | 0.0000 (-0.0002%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.5147 | 0.5147 | -0.0000 (-0.0011%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.5238 | -3.5238 | 0.0000 (-0.0001%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.5379 | 0.5379 | -0.0000 (-0.0003%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.2998 | -3.2998 | 0.0000 (-0.0000%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.3097 | 0.3097 | -0.0000 (-0.0001%) ❗ |
clock__skew__worst_hold | -3.1920 | -3.1920 | -0.0000 (+0.0000%) ⭕ |
clock__skew__worst_setup | 0.1992 | 0.1992 | 0.0000 (+0.0002%) ⭕ |
power__internal__total | 0.0094 | 0.0094 | -0.0000 (-0.0008%) ⭕ |
power__switching__total | 0.0033 | 0.0033 | -0.0000 (-0.0042%) ⭕ |
power__total | 0.0128 | 0.0128 | -0.0000 (-0.0017%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.5492 | -3.5492 | -0.0000 (+0.0001%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.5638 | 0.5638 | 0.0000 (+0.0002%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.1920 | -3.1920 | -0.0000 (+0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1992 | 0.1992 | 0.0000 (+0.0002%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.2863 | -3.2863 | -0.0000 (+0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2956 | 0.2956 | 0.0000 (+0.0005%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.2127 | -3.2127 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2206 | 0.2206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.2007 | -3.2007 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2085 | 0.2085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_upw_old
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.3170 | -3.3170 | 0.0000 (-0.0001%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.3268 | 0.3268 | -0.0000 (-0.0005%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.5017 | -3.5017 | 0.0000 (-0.0002%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.5147 | 0.5147 | -0.0000 (-0.0011%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.5238 | -3.5238 | 0.0000 (-0.0001%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.5379 | 0.5379 | -0.0000 (-0.0003%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.2998 | -3.2998 | 0.0000 (-0.0000%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.3097 | 0.3097 | -0.0000 (-0.0001%) ❗ |
clock__skew__worst_hold | -3.1920 | -3.1920 | -0.0000 (+0.0000%) ⭕ |
clock__skew__worst_setup | 0.1992 | 0.1992 | 0.0000 (+0.0002%) ⭕ |
power__internal__total | 0.0094 | 0.0094 | -0.0000 (-0.0008%) ⭕ |
power__switching__total | 0.0033 | 0.0033 | -0.0000 (-0.0042%) ⭕ |
power__total | 0.0128 | 0.0128 | -0.0000 (-0.0017%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.5492 | -3.5492 | -0.0000 (+0.0001%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.5638 | 0.5638 | 0.0000 (+0.0002%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.1920 | -3.1920 | -0.0000 (+0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1992 | 0.1992 | 0.0000 (+0.0002%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.2863 | -3.2863 | -0.0000 (+0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2956 | 0.2956 | 0.0000 (+0.0005%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.2127 | -3.2127 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2206 | 0.2206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.2007 | -3.2007 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2085 | 0.2085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/blink
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | 0.0000 | -0.2427 | -0.2427 |
timing__setup__wns | 0.0000 | -0.2427 | -0.2427 |
timing__setup_r2r_vio__count | 0 | 3 | 3 |
timing__setup_vio__count | 0 | 3 | 3 |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | -0.2427 | -0.2427 |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | -0.2427 | -0.2427 |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 1 | 1 |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 1 | 1 |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | -0.1143 | -0.1143 |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | -0.1143 | -0.1143 |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 1 | 1 |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 1 | 1 |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | -0.1732 | -0.1732 |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | -0.1732 | -0.1732 |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 1 | 1 |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 1 | 1 |
clock__skew__worst_setup | 0.0031 | -0.0077 | -0.0108 (-345.4194%) ❗ |
design__instance__area | 1407.6000 | 1456.4000 | 48.8000 (+3.4669%) ❗ |
ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (+17.1123%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+11.3118%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0047 | -0.0048 | -0.0095 (-201.8850%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0078 | -0.0077 | -0.0155 (-198.0739%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0057 | -0.0055 | -0.0113 (-196.0625%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0031 | -0.0031 | -0.0062 (-198.6836%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0063 | -0.0055 | -0.0118 (-186.6378%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0040 | -0.0037 | -0.0077 (-191.6163%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0037 | -0.0037 | -0.0074 (-200.7663%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0069 | -0.0065 | -0.0134 (-194.5498%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0047 | -0.0044 | -0.0091 (-193.9182%) ❗ |
clock__skew__worst_hold | 0.0078 | -0.0031 | -0.0109 (-139.4357%) ⭕ |
ir__drop__avg | 0.0001 | 0.0000 | -0.0000 (-17.3145%) ⭕ |
power__internal__total | 0.0002 | 0.0002 | -0.0000 (-0.2036%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | -0.0000 (-7.3122%) ⭕ |
power__total | 0.0002 | 0.0002 | -0.0000 (-1.5717%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0047 | -0.0048 | -0.0095 (-201.8850%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0078 | -0.0077 | -0.0155 (-198.0739%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0057 | -0.0055 | -0.0113 (-196.0625%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0031 | -0.0031 | -0.0062 (-198.6836%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0063 | -0.0055 | -0.0118 (-186.6378%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0040 | -0.0037 | -0.0077 (-191.6163%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0037 | -0.0037 | -0.0074 (-200.7663%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0069 | -0.0065 | -0.0134 (-194.5498%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0047 | -0.0044 | -0.0091 (-193.9182%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 2454.8500 | 2454.8500 | 0.0000 (0.0000%) ⭕ |
design__die__area | 4413.4900 | 4413.4900 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/caravel_upw
Metric | Before | After | Delta |
---|---|---|---|
design__max_cap_violation__count | 5 | 0 | -5 (-100.0000%) ⭕ |
design__max_slew_violation__count | 15 | 0 | -15 (-100.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 5 | 0 | -5 (-100.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 15 | 0 | -15 (-100.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 5 | 0 | -5 (-100.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 15 | 0 | -15 (-100.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 5 | 0 | -5 (-100.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 15 | 0 | -15 (-100.0000%) ⭕ |
clock__skew__worst_hold | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__switching__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__total | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 240 | 240 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/cell_inverter
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/dual_spm
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | -0.0053 | -0.0093 | -0.0040 (+75.5709%) ❗ |
design__instance__area | 22953.7000 | 22963.7000 | 10.0000 (+0.0436%) ❗ |
power__internal__total | 0.0018 | 0.0021 | 0.0003 (+15.8895%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+7.6079%) ❗ |
power__switching__total | 0.0007 | 0.0008 | 0.0000 (+0.6666%) ❗ |
power__total | 0.0026 | 0.0029 | 0.0003 (+11.4982%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0044 | -0.0050 | -0.0094 (-215.2445%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0061 | -0.0093 | -0.0154 (-253.0061%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0044 | -0.0058 | -0.0102 (-230.4977%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0026 | -0.0042 | -0.0016 (+62.6076%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0048 | -0.0079 | -0.0031 (+65.7520%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0032 | -0.0050 | -0.0017 (+54.0832%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0030 | -0.0045 | -0.0015 (+50.1393%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0053 | -0.0089 | -0.0037 (+69.0306%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0036 | -0.0054 | -0.0018 (+50.5507%) ❗ |
clock__skew__worst_hold | 0.0061 | -0.0042 | -0.0103 (-168.8398%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0044 | -0.0050 | -0.0094 (-215.2445%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0061 | -0.0093 | -0.0154 (-253.0061%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0044 | -0.0058 | -0.0102 (-230.4977%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0026 | -0.0042 | -0.0016 (+62.6076%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0048 | -0.0079 | -0.0031 (+65.7520%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0032 | -0.0050 | -0.0017 (+54.0832%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0030 | -0.0045 | -0.0015 (+50.1393%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0053 | -0.0089 | -0.0037 (+69.0306%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0036 | -0.0054 | -0.0018 (+50.5507%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 232536 | 232536 | 0 (0.0000%) ⭕ |
design__die__area | 250000 | 250000 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/gcd
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | 0.0000 | -1.3998 | -1.3998 |
timing__setup__wns | 0.0000 | -0.1775 | -0.1775 |
timing__setup_r2r_vio__count | 0 | 10 | 10 |
timing__setup_vio__count | 0 | 10 | 10 |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | -1.3998 | -1.3998 |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | -0.1775 | -0.1775 |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 10 | 10 |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 10 | 10 |
clock__skew__worst_setup | 0.0062 | 0.0055 | -0.0007 (-10.9428%) ❗ |
design__max_fanout_violation__count | 0 | 3 | 3 ❗ |
ir__drop__worst | 0.0000 | 0.0001 | 0.0000 (+21.4724%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0093 | 0.0080 | -0.0013 (-13.7933%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 3 | 3 ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0170 | 0.0143 | -0.0027 (-16.0329%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 3 | 3 ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0113 | 0.0096 | -0.0017 (-14.7615%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 3 | 3 ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0062 | 0.0055 | -0.0007 (-10.9428%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 3 | 3 ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0137 | 0.0111 | -0.0025 (-18.3349%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 3 | 3 ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0079 | 0.0069 | -0.0010 (-12.2222%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 3 | 3 ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0074 | 0.0063 | -0.0010 (-14.0715%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 3 | 3 ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0150 | 0.0123 | -0.0026 (-17.5620%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 3 | 3 ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0093 | 0.0078 | -0.0014 (-15.5526%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 3 | 3 ❗ |
antenna__violating__nets | 3 | 1 | -2 (-66.6667%) ⭕ |
antenna__violating__pins | 3 | 1 | -2 (-66.6667%) ⭕ |
clock__skew__worst_hold | 0.0170 | 0.0143 | -0.0027 (-16.0329%) ⭕ |
design__instance__area | 4405.4800 | 3966.3000 | -439.1800 (-9.9689%) ⭕ |
design__max_slew_violation__count | 9 | 0 | -9 (-100.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | -0.0000 (-11.4833%) ⭕ |
power__internal__total | 0.0005 | 0.0004 | -0.0001 (-14.8286%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-2.4952%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | -0.0001 (-13.7585%) ⭕ |
power__total | 0.0009 | 0.0008 | -0.0001 (-14.3269%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0093 | 0.0080 | -0.0013 (-13.7933%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0170 | 0.0143 | -0.0027 (-16.0329%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 9 | 0 | -9 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0113 | 0.0096 | -0.0017 (-14.7615%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0062 | 0.0055 | -0.0007 (-10.9428%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0137 | 0.0111 | -0.0025 (-18.3349%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0079 | 0.0069 | -0.0010 (-12.2222%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0074 | 0.0063 | -0.0010 (-14.0715%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0150 | 0.0123 | -0.0026 (-17.5620%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0093 | 0.0078 | -0.0014 (-15.5526%) ⭕ |
design__core__area | 67039.3000 | 67039.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 78425.2000 | 78425.2000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/inverter
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 1051.0100 | 1051.0100 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
design__instance__area | 18.7680 | 18.7680 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/io_placer
Metric | Before | After | Delta |
---|---|---|---|
design__max_cap_violation__count | 5 | 0 | -5 (-100.0000%) ⭕ |
design__max_slew_violation__count | 15 | 0 | -15 (-100.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 5 | 0 | -5 (-100.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 15 | 0 | -15 (-100.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 5 | 0 | -5 (-100.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 15 | 0 | -15 (-100.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 5 | 0 | -5 (-100.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 15 | 0 | -15 (-100.0000%) ⭕ |
clock__skew__worst_hold | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__switching__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__total | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 240 | 240 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch_bad
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch_good
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/manual_macro_placement_test
Metric | Before | After | Delta |
---|---|---|---|
power__internal__total | 0.0001 | 0.0001 | 0.0000 (+0.4007%) ❗ |
design__max_fanout_violation__count | 32 | 30 | -2 (-6.2500%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-35.7608%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | -0.0000 (-1.7434%) ⭕ |
power__total | 0.0002 | 0.0002 | -0.0000 (-0.1823%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 32 | 30 | -2 (-6.2500%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 32 | 30 | -2 (-6.2500%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 32 | 30 | -2 (-6.2500%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 32 | 30 | -2 (-6.2500%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 32 | 30 | -2 (-6.2500%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 32 | 30 | -2 (-6.2500%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 32 | 30 | -2 (-6.2500%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 32 | 30 | -2 (-6.2500%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 32 | 30 | -2 (-6.2500%) ⭕ |
clock__skew__worst_hold | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup | 0 | 0 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/s44
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0024 | 0.0048 | 0.0072 (-298.6932%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+4.2611%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0040 | 0.0025 | 0.0065 (-162.8184%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0058 | 0.0048 | 0.0105 (-182.2345%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0049 | 0.0033 | 0.0082 (-168.3063%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0024 | 0.0020 | 0.0044 (-185.5640%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0036 | 0.0041 | 0.0076 (-213.6656%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0031 | 0.0028 | 0.0058 (-190.8753%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0028 | 0.0023 | 0.0051 (-180.3097%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0042 | 0.0044 | 0.0086 (-204.4521%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0035 | 0.0030 | 0.0066 (-185.6179%) ❗ |
clock__skew__worst_setup | -0.0058 | 0.0020 | 0.0078 (-135.4130%) ⭕ |
design__instance__area | 2613.7600 | 2521.1700 | -92.5900 (-3.5424%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | -0.0000 (-45.2973%) ⭕ |
ir__drop__worst | 0.0002 | 0.0001 | -0.0001 (-43.1646%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | -0.0000 (-22.7955%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | -0.0000 (-26.9638%) ⭕ |
power__total | 0.0002 | 0.0001 | -0.0000 (-23.8121%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0040 | 0.0025 | 0.0065 (-162.8184%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0058 | 0.0048 | 0.0105 (-182.2345%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0049 | 0.0033 | 0.0082 (-168.3063%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0024 | 0.0020 | 0.0044 (-185.5640%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0036 | 0.0041 | 0.0076 (-213.6656%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0031 | 0.0028 | 0.0058 (-190.8753%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0028 | 0.0023 | 0.0051 (-180.3097%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0042 | 0.0044 | 0.0086 (-204.4521%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0035 | 0.0030 | 0.0066 (-185.6179%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 33280.7000 | 33280.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 39709.7000 | 39709.7000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/spm
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | -0.0056 | -0.0070 | -0.0015 (+26.5916%) ❗ |
design__instance__area | 3633.4800 | 4010.1000 | 376.6200 (+10.3653%) ❗ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (+17.6796%) ❗ |
power__internal__total | 0.0008 | 0.0012 | 0.0004 (+48.6764%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+13.8192%) ❗ |
power__switching__total | 0.0004 | 0.0004 | 0.0001 (+14.5136%) ❗ |
power__total | 0.0012 | 0.0016 | 0.0004 (+37.6805%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0045 | 0.0040 | 0.0085 (-189.5949%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0093 | -0.0070 | -0.0164 (-175.2857%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0056 | -0.0044 | 0.0012 (-21.5221%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0031 | -0.0033 | -0.0001 (+4.7475%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0072 | -0.0062 | -0.0134 (-187.2555%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0040 | -0.0041 | -0.0001 (+2.5639%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0036 | -0.0035 | 0.0001 (-2.3542%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0080 | -0.0068 | -0.0149 (-184.8176%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0046 | -0.0043 | 0.0003 (-6.0337%) ❗ |
clock__skew__worst_hold | 0.0093 | 0.0040 | -0.0053 (-57.1766%) ⭕ |
design__max_fanout_violation__count | 1 | 0 | -1 (-100.0000%) ⭕ |
ir__drop__worst | 0.0009 | 0.0008 | -0.0002 (-17.3536%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0045 | 0.0040 | 0.0085 (-189.5949%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 0 | -1 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0093 | -0.0070 | -0.0164 (-175.2857%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 0 | -1 (-100.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0056 | -0.0044 | 0.0012 (-21.5221%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 0 | -1 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0031 | -0.0033 | -0.0001 (+4.7475%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 0 | -1 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0072 | -0.0062 | -0.0134 (-187.2555%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 0 | -1 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0040 | -0.0041 | -0.0001 (+2.5639%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 0 | -1 (-100.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0036 | -0.0035 | 0.0001 (-2.3542%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 0 | -1 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0080 | -0.0068 | -0.0149 (-184.8176%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 0 | -1 (-100.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0046 | -0.0043 | 0.0003 (-6.0337%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 0 | -1 (-100.0000%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 8051.4700 | 8051.4700 | 0.0000 (0.0000%) ⭕ |
design__die__area | 11317.8000 | 11317.8000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/test_sram_macro
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.1277 | -0.1157 | 0.0120 (-9.3987%) ❗ |
clock__skew__worst_setup | -0.4144 | -0.4171 | -0.0027 (+0.6534%) ❗ |
design__max_slew_violation__count | 186 | 205 | 19 (+10.2151%) ❗ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (+8.7432%) ❗ |
power__internal__total | 0.0018 | 0.0018 | 0.0000 (+1.1301%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.0014%) ❗ |
power__switching__total | 0.0002 | 0.0002 | 0.0000 (+15.3912%) ❗ |
power__total | 0.0020 | 0.0021 | 0.0001 (+2.5692%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1277 | -0.1157 | 0.0120 (-9.3987%) ❗ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 51 | 71 | 20 (+39.2157%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.4144 | -0.4171 | -0.0027 (+0.6534%) ❗ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 186 | 205 | 19 (+10.2151%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2429 | -0.2331 | 0.0099 (-4.0589%) ❗ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 100 | 155 | 55 (+55.0000%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.1360 | -0.1341 | 0.0019 (-1.3892%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.3659 | -0.3740 | -0.0081 (+2.2064%) ❗ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 148 | 171 | 23 (+15.5405%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.2271 | -0.2281 | -0.0010 (+0.4243%) ❗ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 77 | 113 | 36 (+46.7532%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1342 | -0.1284 | 0.0058 (-4.3182%) ❗ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 39 | 48 | 9 (+23.0769%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.3937 | -0.3991 | -0.0054 (+1.3650%) ❗ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 182 | 185 | 3 (+1.6484%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2404 | -0.2324 | 0.0080 (-3.3113%) ❗ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 94 | 151 | 57 (+60.6383%) ❗ |
antenna__violating__nets | 9 | 8 | -1 (-11.1111%) ⭕ |
design__instance__area | 395756 | 395569 | -187 (-0.0473%) ⭕ |
design__max_fanout_violation__count | 4 | 2 | -2 (-50.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.1277 | -0.1157 | 0.0120 (-9.3987%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 10 | 8 | -2 (-20.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 4 | 2 | -2 (-50.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.4144 | -0.4171 | -0.0027 (+0.6534%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 4 | 2 | -2 (-50.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.2429 | -0.2331 | 0.0099 (-4.0589%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 11 | 9 | -2 (-18.1818%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 4 | 2 | -2 (-50.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.1360 | -0.1341 | 0.0019 (-1.3892%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 10 | 8 | -2 (-20.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 4 | 2 | -2 (-50.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.3659 | -0.3740 | -0.0081 (+2.2064%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 11 | 8 | -3 (-27.2727%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 4 | 2 | -2 (-50.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2271 | -0.2281 | -0.0010 (+0.4243%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 10 | 8 | -2 (-20.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 4 | 2 | -2 (-50.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.1342 | -0.1284 | 0.0058 (-4.3182%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 10 | 8 | -2 (-20.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 4 | 2 | -2 (-50.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.3937 | -0.3991 | -0.0054 (+1.3650%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 4 | 2 | -2 (-50.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.2404 | -0.2324 | 0.0080 (-3.3113%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 10 | 8 | -2 (-20.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 4 | 2 | -2 (-50.0000%) ⭕ |
antenna__violating__pins | 9 | 9 | 0 (0.0000%) ⭕ |
design__core__area | 906252 | 906252 | 0 (0.0000%) ⭕ |
design__die__area | 937500 | 937500 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 18 | 18 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 5666674 | 5666674 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 18 | 18 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 24 | 24 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 13 | 13 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0118 | -0.0106 | 0.0013 (-10.8910%) ❗ |
ir__drop__avg | 0.0003 | 0.0004 | 0.0001 (+33.0986%) ❗ |
ir__drop__worst | 0.0015 | 0.0016 | 0.0001 (+8.0537%) ❗ |
power__internal__total | 0.0011 | 0.0013 | 0.0003 (+24.1523%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+6.5738%) ❗ |
power__switching__total | 0.0004 | 0.0006 | 0.0002 (+45.5000%) ❗ |
power__total | 0.0015 | 0.0019 | 0.0005 (+30.3497%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0157 | -0.0158 | -0.0001 (+0.7906%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0273 | -0.0232 | 0.0041 (-15.1306%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0195 | -0.0185 | 0.0010 (-5.0721%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0118 | -0.0106 | 0.0013 (-10.8910%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0214 | -0.0176 | 0.0039 (-17.9752%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0150 | -0.0128 | 0.0022 (-14.6502%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0133 | -0.0124 | 0.0010 (-7.2064%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0239 | -0.0200 | 0.0039 (-16.2505%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0168 | -0.0150 | 0.0019 (-11.0099%) ❗ |
clock__skew__worst_setup | -0.0273 | -0.0232 | 0.0041 (-15.1306%) ⭕ |
design__instance__area | 11912.7000 | 11676.2000 | -236.5000 (-1.9853%) ⭕ |
design__max_fanout_violation__count | 19 | 17 | -2 (-10.5263%) ⭕ |
design__max_slew_violation__count | 13 | 0 | -13 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0157 | -0.0158 | -0.0001 (+0.7906%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 19 | 17 | -2 (-10.5263%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0273 | -0.0232 | 0.0041 (-15.1306%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 19 | 17 | -2 (-10.5263%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 13 | 0 | -13 (-100.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0195 | -0.0185 | 0.0010 (-5.0721%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 19 | 17 | -2 (-10.5263%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0118 | -0.0106 | 0.0013 (-10.8910%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 19 | 17 | -2 (-10.5263%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0214 | -0.0176 | 0.0039 (-17.9752%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 19 | 17 | -2 (-10.5263%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 13 | 0 | -13 (-100.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0150 | -0.0128 | 0.0022 (-14.6502%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 19 | 17 | -2 (-10.5263%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0133 | -0.0124 | 0.0010 (-7.2064%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 19 | 17 | -2 (-10.5263%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0239 | -0.0200 | 0.0039 (-16.2505%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 19 | 17 | -2 (-10.5263%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 13 | 0 | -13 (-100.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0168 | -0.0150 | 0.0019 (-11.0099%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 19 | 17 | -2 (-10.5263%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 24319.6000 | 24319.6000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 30066.6000 | 30066.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb_cdc_core
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 3 | 3 ❗ |
antenna__violating__pins | 0 | 3 | 3 ❗ |
power__internal__total | 0.0017 | 0.0018 | 0.0001 (+2.9909%) ❗ |
power__switching__total | 0.0007 | 0.0008 | 0.0001 (+9.6369%) ❗ |
power__total | 0.0024 | 0.0026 | 0.0001 (+4.9200%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1255 | 0.0387 | 0.1642 (-130.8406%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.3303 | 0.0731 | 0.4034 (-122.1321%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.1849 | 0.0482 | 0.2331 (-126.0874%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1200 | 0.0295 | -0.0905 (-75.4340%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.3184 | 0.0589 | 0.3773 (-118.4962%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.1778 | 0.0370 | -0.1408 (-79.2158%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1227 | 0.0330 | 0.1557 (-126.9211%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.3245 | 0.0651 | 0.3896 (-120.0694%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.1813 | 0.0415 | 0.2228 (-122.8979%) ❗ |
clock__skew__worst_hold | 0.1778 | 0.0731 | -0.1047 (-58.8833%) ⭕ |
clock__skew__worst_setup | -0.3303 | 0.0295 | 0.3598 (-108.9245%) ⭕ |
design__instance__area | 24755.0000 | 23376.2000 | -1378.8000 (-5.5698%) ⭕ |
design__max_slew_violation__count | 3 | 2 | -1 (-33.3333%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | -0.0000 (-2.2008%) ⭕ |
ir__drop__worst | 0.0003 | 0.0003 | -0.0000 (-3.4582%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-6.2215%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.1255 | 0.0387 | 0.1642 (-130.8406%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.3303 | 0.0731 | 0.4034 (-122.1321%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 3 | 2 | -1 (-33.3333%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.1849 | 0.0482 | 0.2331 (-126.0874%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.1200 | 0.0295 | -0.0905 (-75.4340%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.3184 | 0.0589 | 0.3773 (-118.4962%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 3 | 2 | -1 (-33.3333%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.1778 | 0.0370 | -0.1408 (-79.2158%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.1227 | 0.0330 | 0.1557 (-126.9211%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.3245 | 0.0651 | 0.3896 (-120.0694%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 3 | 2 | -1 (-33.3333%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.1813 | 0.0415 | 0.2228 (-122.8979%) ⭕ |
design__core__area | 61711.7000 | 61711.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 70647.5000 | 70647.5000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 30 | 30 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 30 | 30 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 30 | 30 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 30 | 30 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 30 | 30 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 30 | 30 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 30 | 30 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 30 | 30 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 30 | 30 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 30 | 30 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/user_proj_timer
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | 0.0075 | 0.0084 | 0.0009 (+12.5650%) ❗ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (+13.6364%) ❗ |
power__switching__total | 0.0001 | 0.0001 | 0.0000 (+1.7335%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0059 | 0.0055 | 0.0114 (-192.9522%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0090 | 0.0081 | 0.0172 (-190.1870%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0066 | 0.0059 | 0.0125 (-188.9335%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0035 | 0.0037 | 0.0072 (-204.4768%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0075 | 0.0081 | 0.0006 (+8.6537%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0042 | 0.0047 | 0.0089 (-213.1537%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0043 | 0.0040 | 0.0083 (-192.5932%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0080 | 0.0084 | 0.0163 (-205.4692%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0049 | 0.0051 | 0.0100 (-203.4357%) ❗ |
clock__skew__worst_setup | -0.0090 | 0.0037 | 0.0127 (-140.9642%) ⭕ |
design__instance__area | 17857.1000 | 17570.6000 | -286.5000 (-1.6044%) ⭕ |
design__max_cap_violation__count | 3 | 1 | -2 (-66.6667%) ⭕ |
design__max_fanout_violation__count | 6 | 4 | -2 (-33.3333%) ⭕ |
design__max_slew_violation__count | 103 | 59 | -44 (-42.7184%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | -0.0000 (-1.9713%) ⭕ |
power__internal__total | 0.0003 | 0.0002 | -0.0000 (-3.8120%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-1.7341%) ⭕ |
power__total | 0.0003 | 0.0003 | -0.0000 (-2.5713%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0059 | 0.0055 | 0.0114 (-192.9522%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 2 | 1 | -1 (-50.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 6 | 4 | -2 (-33.3333%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 50 | 0 | -50 (-100.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0090 | 0.0081 | 0.0172 (-190.1870%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 3 | 1 | -2 (-66.6667%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 6 | 4 | -2 (-33.3333%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 103 | 59 | -44 (-42.7184%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0066 | 0.0059 | 0.0125 (-188.9335%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 2 | 1 | -1 (-50.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 6 | 4 | -2 (-33.3333%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 50 | 0 | -50 (-100.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0035 | 0.0037 | 0.0072 (-204.4768%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 2 | 1 | -1 (-50.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 6 | 4 | -2 (-33.3333%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0075 | 0.0081 | 0.0006 (+8.6537%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 2 | 1 | -1 (-50.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 6 | 4 | -2 (-33.3333%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 103 | 52 | -51 (-49.5146%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0042 | 0.0047 | 0.0089 (-213.1537%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 2 | 1 | -1 (-50.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 6 | 4 | -2 (-33.3333%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0043 | 0.0040 | 0.0083 (-192.5932%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 2 | 1 | -1 (-50.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 6 | 4 | -2 (-33.3333%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0080 | 0.0084 | 0.0163 (-205.4692%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 2 | 1 | -1 (-50.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 6 | 4 | -2 (-33.3333%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 103 | 52 | -51 (-49.5146%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0049 | 0.0051 | 0.0100 (-203.4357%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 2 | 1 | -1 (-50.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 6 | 4 | -2 (-33.3333%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 50 | 0 | -50 (-100.0000%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 655604 | 655604 | 0 (0.0000%) ⭕ |
design__die__area | 700000 | 700000 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/wbqspiflash
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0433 | 0.0262 | 0.0695 (-160.6138%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0451 | -0.0186 | 0.0265 (-58.7615%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0944 | -0.0322 | 0.0622 (-65.9064%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0600 | 0.0230 | 0.0830 (-138.2546%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0433 | -0.0139 | 0.0294 (-67.9729%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0905 | 0.0229 | 0.1135 (-125.3387%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0578 | -0.0176 | 0.0402 (-69.5711%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0442 | -0.0150 | 0.0292 (-66.1038%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0923 | 0.0262 | 0.1185 (-128.4171%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0590 | -0.0188 | 0.0402 (-68.1859%) ❗ |
antenna__violating__nets | 2 | 0 | -2 (-100.0000%) ⭕ |
antenna__violating__pins | 2 | 0 | -2 (-100.0000%) ⭕ |
clock__skew__worst_setup | -0.0944 | -0.0322 | 0.0622 (-65.9064%) ⭕ |
design__instance__area | 27361.2000 | 23702.7000 | -3658.5000 (-13.3711%) ⭕ |
design__max_fanout_violation__count | 37 | 28 | -9 (-24.3243%) ⭕ |
design__max_slew_violation__count | 13 | 2 | -11 (-84.6154%) ⭕ |
ir__drop__avg | 0.0002 | 0.0002 | -0.0000 (-8.4337%) ⭕ |
ir__drop__worst | 0.0007 | 0.0007 | -0.0000 (-3.0556%) ⭕ |
power__internal__total | 0.0031 | 0.0029 | -0.0002 (-5.7075%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-1.1563%) ⭕ |
power__switching__total | 0.0031 | 0.0029 | -0.0003 (-8.0904%) ⭕ |
power__total | 0.0062 | 0.0058 | -0.0004 (-6.9122%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0451 | -0.0186 | 0.0265 (-58.7615%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 37 | 28 | -9 (-24.3243%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0944 | -0.0322 | 0.0622 (-65.9064%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 37 | 28 | -9 (-24.3243%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 13 | 2 | -11 (-84.6154%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0600 | 0.0230 | 0.0830 (-138.2546%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 37 | 28 | -9 (-24.3243%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0433 | -0.0139 | 0.0294 (-67.9729%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 37 | 28 | -9 (-24.3243%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0905 | 0.0229 | 0.1135 (-125.3387%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 37 | 28 | -9 (-24.3243%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0578 | -0.0176 | 0.0402 (-69.5711%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 37 | 28 | -9 (-24.3243%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0442 | -0.0150 | 0.0292 (-66.1038%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 37 | 28 | -9 (-24.3243%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0923 | 0.0262 | 0.1185 (-128.4171%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 37 | 28 | -9 (-24.3243%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 5 | 2 | -3 (-60.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0590 | -0.0188 | 0.0402 (-68.1859%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 37 | 28 | -9 (-24.3243%) ⭕ |
design__core__area | 74196.2000 | 74196.2000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 83741 | 83741 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/xtea
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 1 | 1 ❗ |
antenna__violating__pins | 0 | 1 | 1 ❗ |
clock__skew__worst_setup | 0.0227 | 0.0165 | -0.0062 (-27.3877%) ❗ |
ir__drop__avg | 0.0002 | 0.0003 | 0.0000 (+17.6471%) ❗ |
ir__drop__worst | 0.0008 | 0.0010 | 0.0002 (+24.7191%) ❗ |
power__internal__total | 0.0032 | 0.0036 | 0.0004 (+13.4090%) ❗ |
power__switching__total | 0.0039 | 0.0045 | 0.0005 (+13.5131%) ❗ |
power__total | 0.0071 | 0.0081 | 0.0010 (+13.4663%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0308 | 0.0261 | -0.0047 (-15.2466%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0574 | 0.0369 | -0.0205 (-35.6408%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0396 | 0.0300 | -0.0096 (-24.2530%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0227 | 0.0165 | -0.0062 (-27.3877%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0439 | 0.0269 | -0.0170 (-38.7046%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0298 | 0.0194 | -0.0104 (-34.8033%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0261 | 0.0202 | -0.0059 (-22.6798%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0501 | 0.0304 | -0.0197 (-39.3404%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0342 | 0.0236 | -0.0106 (-31.0368%) ❗ |
clock__skew__worst_hold | 0.0574 | 0.0369 | -0.0205 (-35.6408%) ⭕ |
design__instance__area | 25022.7000 | 23525.1000 | -1497.6000 (-5.9850%) ⭕ |
design__max_slew_violation__count | 16 | 3 | -13 (-81.2500%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-2.0549%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0308 | 0.0261 | -0.0047 (-15.2466%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0574 | 0.0369 | -0.0205 (-35.6408%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 16 | 3 | -13 (-81.2500%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0396 | 0.0300 | -0.0096 (-24.2530%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0227 | 0.0165 | -0.0062 (-27.3877%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0439 | 0.0269 | -0.0170 (-38.7046%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 12 | 0 | -12 (-100.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0298 | 0.0194 | -0.0104 (-34.8033%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0261 | 0.0202 | -0.0059 (-22.6798%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0501 | 0.0304 | -0.0197 (-39.3404%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 16 | 3 | -13 (-81.2500%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0342 | 0.0236 | -0.0106 (-31.0368%) ⭕ |
design__core__area | 52445.3000 | 52445.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 60511.9000 | 60511.9000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 17 | 17 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/zipdiv
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0141 | 0.0227 | 0.0367 (-261.1954%) ❗ |
design__max_fanout_violation__count | 15 | 16 | 1 (+6.6667%) ❗ |
power__internal__total | 0.0007 | 0.0007 | 0.0000 (+6.7856%) ❗ |
power__total | 0.0011 | 0.0011 | 0.0000 (+0.1692%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0184 | 0.0140 | 0.0323 (-175.9256%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 15 | 16 | 1 (+6.6667%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0301 | 0.0227 | 0.0527 (-175.3799%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 15 | 16 | 1 (+6.6667%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0230 | 0.0173 | 0.0403 (-175.2555%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 15 | 16 | 1 (+6.6667%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0141 | 0.0109 | 0.0250 (-177.8733%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 15 | 16 | 1 (+6.6667%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0232 | 0.0172 | 0.0404 (-174.4857%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 15 | 16 | 1 (+6.6667%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0178 | 0.0133 | 0.0312 (-174.7528%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 15 | 16 | 1 (+6.6667%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0157 | 0.0120 | 0.0277 (-176.6645%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 15 | 16 | 1 (+6.6667%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0261 | 0.0191 | 0.0452 (-173.1423%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 15 | 16 | 1 (+6.6667%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0199 | 0.0146 | 0.0345 (-173.7226%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 15 | 16 | 1 (+6.6667%) ❗ |
clock__skew__worst_setup | -0.0301 | 0.0109 | 0.0410 (-136.4159%) ⭕ |
design__instance__area | 13277.7000 | 11606.1000 | -1671.6000 (-12.5895%) ⭕ |
design__max_slew_violation__count | 4 | 0 | -4 (-100.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | -0.0000 (-4.5531%) ⭕ |
ir__drop__worst | 0.0003 | 0.0003 | -0.0000 (-0.6623%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-9.5400%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | -0.0000 (-9.5611%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0184 | 0.0140 | 0.0323 (-175.9256%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0301 | 0.0227 | 0.0527 (-175.3799%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 4 | 0 | -4 (-100.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0230 | 0.0173 | 0.0403 (-175.2555%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0141 | 0.0109 | 0.0250 (-177.8733%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0232 | 0.0172 | 0.0404 (-174.4857%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0178 | 0.0133 | 0.0312 (-174.7528%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0157 | 0.0120 | 0.0277 (-176.6645%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0261 | 0.0191 | 0.0452 (-173.1423%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0199 | 0.0146 | 0.0345 (-173.7226%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 31230 | 31230 | 0 (0.0000%) ⭕ |
design__die__area | 37409.7000 | 37409.7000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
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