gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/APU
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.4511 | -0.4511 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.4818 | 0.4818 | 0.0000 (0.0000%) ⭕ |
design__core__area | 289314 | 289314 | 0 (0.0000%) ⭕ |
design__die__area | 315191 | 315191 | 0 (0.0000%) ⭕ |
design__instance__area | 111696 | 111696 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 166 | 166 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 32 | 32 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0094 | 0.0094 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0044 | 0.0044 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0138 | 0.0138 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.4593 | -0.4593 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.4988 | 0.4988 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 166 | 166 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.8175 | -0.8175 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.9073 | 0.9073 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 166 | 166 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 32 | 32 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.5697 | -0.5697 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.6252 | 0.6252 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 166 | 166 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.4511 | -0.4511 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.4818 | 0.4818 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 166 | 166 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.7977 | -0.7977 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.8697 | 0.8697 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 166 | 166 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 32 | 32 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.5577 | -0.5577 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.6017 | 0.6017 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 166 | 166 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.4547 | -0.4547 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.4896 | 0.4896 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 166 | 166 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.8067 | -0.8067 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.8869 | 0.8869 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 166 | 166 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 32 | 32 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.5632 | -0.5632 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.6125 | 0.6125 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 166 | 166 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/blink
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2517 | -0.2517 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2517 | 0.2517 | 0.0000 (0.0000%) ⭕ |
design__core__area | 6868.7800 | 6868.7800 | 0.0000 (0.0000%) ⭕ |
design__die__area | 11201.3000 | 11201.3000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 4197.2200 | 4197.2200 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0028 | 0.0028 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0034 | 0.0034 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2525 | -0.2525 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2525 | 0.2525 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2553 | -0.2553 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2553 | 0.2553 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2533 | -0.2533 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2533 | 0.2533 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2517 | -0.2517 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2517 | 0.2517 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2536 | -0.2536 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2536 | 0.2536 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2522 | -0.2522 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2522 | 0.2522 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2520 | -0.2520 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2520 | 0.2520 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2544 | -0.2544 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2544 | 0.2544 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2527 | -0.2527 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2527 | 0.2527 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/cell_inverter
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 8.7808 | 8.7808 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/inverter
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 570.7520 | 570.7520 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
design__instance__area | 57.0752 | 57.0752 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch_bad
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch_good
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/spm
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2537 | -0.2537 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2541 | 0.2541 | 0.0000 (0.0000%) ⭕ |
design__core__area | 21280.3000 | 21280.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 28670.3000 | 28670.3000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 11731.1000 | 11731.1000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0072 | 0.0072 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0022 | 0.0022 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0094 | 0.0094 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2548 | -0.2548 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2554 | 0.2554 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2651 | -0.2651 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2650 | 0.2650 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2580 | -0.2580 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2580 | 0.2580 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2537 | -0.2537 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2541 | 0.2541 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2610 | -0.2610 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2609 | 0.2609 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2558 | -0.2558 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2560 | 0.2560 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2542 | -0.2542 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2547 | 0.2547 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2629 | -0.2629 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2628 | 0.2628 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2568 | -0.2568 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2569 | 0.2569 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2635 | -0.2635 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2635 | 0.2635 | 0.0000 (0.0000%) ⭕ |
design__core__area | 60989.2000 | 60989.2000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 72485.3000 | 72485.3000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 31233.3000 | 31233.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0164 | 0.0164 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0058 | 0.0058 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0222 | 0.0222 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2654 | -0.2654 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2654 | 0.2654 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2886 | -0.2886 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2886 | 0.2886 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2729 | -0.2729 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2729 | 0.2729 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2635 | -0.2635 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2635 | 0.2635 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2839 | -0.2839 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2839 | 0.2839 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2701 | -0.2701 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2701 | 0.2701 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2644 | -0.2644 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2644 | 0.2644 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2861 | -0.2861 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2861 | 0.2861 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2714 | -0.2714 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2714 | 0.2714 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb_cdc_core
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.4446 | -0.4446 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.4536 | 0.4536 | 0.0000 (0.0000%) ⭕ |
design__core__area | 157861 | 157861 | 0 (0.0000%) ⭕ |
design__die__area | 177413 | 177413 | 0 (0.0000%) ⭕ |
design__instance__area | 75067.1000 | 75067.1000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 71 | 71 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0020 | 0.0020 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0570 | 0.0570 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0208 | 0.0208 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0778 | 0.0778 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | -0.0584 | -0.0584 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | -0.0584 | -0.0584 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 2 | 2 | 0 (0.0000%) ⭕ |
timing__setup__tns | -80.7985 | -80.7985 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -2.9658 | -2.9658 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 288 | 288 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 321 | 321 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.4537 | -0.4537 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.4621 | 0.4621 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 71 | 71 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.8093 | -0.8093 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.8283 | 0.8283 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 71 | 71 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | -0.0584 | -0.0584 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | -0.0584 | -0.0584 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | -80.7985 | -80.7985 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | -2.9658 | -2.9658 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 107 | 107 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 118 | 118 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.5636 | -0.5636 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.5751 | 0.5751 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 71 | 71 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.4446 | -0.4446 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.4536 | 0.4536 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 71 | 71 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.7868 | -0.7868 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.8081 | 0.8081 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 71 | 71 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | -52.0402 | -52.0402 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | -2.7845 | -2.7845 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 85 | 85 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 96 | 96 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.5502 | -0.5502 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.5629 | 0.5629 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 71 | 71 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.4488 | -0.4488 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.4575 | 0.4575 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 71 | 71 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.7971 | -0.7971 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.8173 | 0.8173 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 71 | 71 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | -0.0110 | -0.0110 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | -0.0110 | -0.0110 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | -64.3225 | -64.3225 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | -2.8667 | -2.8667 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 96 | 96 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 107 | 107 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.5563 | -0.5563 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.5685 | 0.5685 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 71 | 71 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/wbqspiflash
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.4314 | -0.4314 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.4314 | 0.4314 | 0.0000 (0.0000%) ⭕ |
design__core__area | 104224 | 104224 | 0 (0.0000%) ⭕ |
design__die__area | 120173 | 120173 | 0 (0.0000%) ⭕ |
design__instance__area | 76546.6000 | 76546.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0016 | 0.0016 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0042 | 0.0042 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.1382 | 0.1382 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0997 | 0.0997 | 0.0000 (0.0000%) ⭕ |
power__total | 0.2379 | 0.2379 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -417.7350 | -417.7350 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -5.5098 | -5.5098 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 440 | 440 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 440 | 440 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.4343 | -0.4343 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.4343 | 0.4343 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.7719 | -0.7719 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.7719 | 0.7719 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | -417.7350 | -417.7350 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | -5.5098 | -5.5098 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 147 | 147 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 147 | 147 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.5383 | -0.5383 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.5383 | 0.5383 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.4314 | -0.4314 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.4314 | 0.4314 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.7612 | -0.7612 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.7612 | 0.7612 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | -326.3697 | -326.3697 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | -4.3309 | -4.3309 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 146 | 146 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 146 | 146 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.5330 | -0.5330 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.5330 | 0.5330 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.4327 | -0.4327 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.4327 | 0.4327 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.7660 | -0.7660 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.7660 | 0.7660 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | -361.9673 | -361.9673 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | -4.8384 | -4.8384 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 147 | 147 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 147 | 147 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.5353 | -0.5353 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.5353 | 0.5353 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/zipdiv
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2643 | -0.2643 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2653 | 0.2653 | 0.0000 (0.0000%) ⭕ |
design__core__area | 78085.5000 | 78085.5000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 92022.9000 | 92022.9000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 40244.6000 | 40244.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0201 | 0.0201 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0099 | 0.0099 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0300 | 0.0300 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -201.6676 | -201.6676 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -5.3780 | -5.3780 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 195 | 195 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 195 | 195 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2680 | -0.2680 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2688 | 0.2688 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2950 | -0.2950 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2966 | 0.2966 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | -201.6676 | -201.6676 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | -5.3780 | -5.3780 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 65 | 65 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 65 | 65 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2761 | -0.2761 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2777 | 0.2777 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2643 | -0.2643 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2653 | 0.2653 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2866 | -0.2866 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2878 | 0.2878 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | -184.6830 | -184.6830 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | -5.0492 | -5.0492 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 65 | 65 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 65 | 65 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2713 | -0.2713 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2725 | 0.2725 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2660 | -0.2660 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2669 | 0.2669 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2905 | -0.2905 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2918 | 0.2918 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | -191.7496 | -191.7496 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | -5.1990 | -5.1990 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 65 | 65 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 65 | 65 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2735 | -0.2735 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2748 | 0.2748 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/APU
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.3781 | -0.3781 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.3836 | 0.3836 | 0.0000 (0.0000%) ⭕ |
design__core__area | 83157.3000 | 83157.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 92959.7000 | 92959.7000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 33109.3000 | 33109.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 50 | 50 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 36 | 36 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0022 | 0.0022 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0011 | 0.0011 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.3864 | -0.3864 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3932 | 0.3932 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 50 | 50 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.6123 | -0.6123 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.6282 | 0.6282 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 50 | 50 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 36 | 36 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.4521 | -0.4521 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.4615 | 0.4615 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 50 | 50 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.3781 | -0.3781 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.3836 | 0.3836 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 50 | 50 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.5913 | -0.5913 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.6044 | 0.6044 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 50 | 50 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 18 | 18 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.4400 | -0.4400 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.4475 | 0.4475 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 50 | 50 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.3820 | -0.3820 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.3881 | 0.3881 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 50 | 50 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.6005 | -0.6005 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.6153 | 0.6153 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 50 | 50 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 31 | 31 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.4454 | -0.4454 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.4539 | 0.4539 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 50 | 50 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_GPIO
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2502 | -0.2502 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2512 | 0.2512 | 0.0000 (0.0000%) ⭕ |
design__core__area | 1670.3500 | 1670.3500 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2700.3500 | 2700.3500 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 1372.5700 | 1372.5700 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2510 | -0.2510 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2520 | 0.2520 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2510 | -0.2510 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2528 | 0.2528 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2510 | -0.2510 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2523 | 0.2523 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2503 | -0.2503 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2512 | 0.2512 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2502 | -0.2502 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2517 | 0.2517 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2503 | -0.2503 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2514 | 0.2514 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2504 | -0.2504 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2515 | 0.2515 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2504 | -0.2504 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2521 | 0.2521 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2504 | -0.2504 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2517 | 0.2517 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_PSRAM_CTRL_V2
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2534 | -0.2534 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2534 | 0.2534 | 0.0000 (0.0000%) ⭕ |
design__core__area | 8051.4700 | 8051.4700 | 0.0000 (0.0000%) ⭕ |
design__die__area | 11311.4000 | 11311.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 5670.4400 | 5670.4400 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -0.0213 | -0.0213 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -0.0213 | -0.0213 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2551 | -0.2551 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2547 | 0.2547 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2603 | -0.2603 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2600 | 0.2600 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | -0.0213 | -0.0213 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | -0.0213 | -0.0213 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2560 | -0.2560 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2557 | 0.2557 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2534 | -0.2534 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2534 | 0.2534 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2581 | -0.2581 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2580 | 0.2580 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2543 | -0.2543 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2543 | 0.2543 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2540 | -0.2540 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2539 | 0.2539 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2592 | -0.2592 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2591 | 0.2591 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2550 | -0.2550 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2549 | 0.2549 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_TCC32
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.1075 | -0.1075 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.1075 | 0.1075 | 0.0000 (0.0000%) ⭕ |
design__core__area | 11369.7000 | 11369.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 15327.4000 | 15327.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 9275.1500 | 9275.1500 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0013 | 0.0013 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0023 | 0.0023 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1141 | -0.1141 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1141 | 0.1141 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.1183 | -0.1183 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.1183 | 0.1183 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.1149 | -0.1149 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.1149 | 0.1149 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.1075 | -0.1075 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1075 | 0.1075 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.1137 | -0.1137 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.1137 | 0.1137 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.1083 | -0.1083 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.1083 | 0.1083 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1097 | -0.1097 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1097 | 0.1097 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.1151 | -0.1151 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.1151 | 0.1151 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.1106 | -0.1106 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.1106 | 0.1106 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_UART
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.1195 | -0.1195 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.1192 | 0.1192 | 0.0000 (0.0000%) ⭕ |
design__core__area | 22434 | 22434 | 0 (0.0000%) ⭕ |
design__die__area | 27763.5000 | 27763.5000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 19911.6000 | 19911.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0030 | 0.0030 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0021 | 0.0021 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0054 | 0.0054 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1269 | -0.1269 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1237 | 0.1237 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.1460 | -0.1460 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.1453 | 0.1453 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.1334 | -0.1334 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.1312 | 0.1312 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.1195 | -0.1195 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1192 | 0.1192 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.1374 | -0.1374 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.1370 | 0.1370 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.1258 | -0.1258 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.1255 | 0.1255 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1221 | -0.1221 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1216 | 0.1216 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.1425 | -0.1425 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.1418 | 0.1418 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.1291 | -0.1291 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.1287 | 0.1287 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_CLK_RST
Metric | Before | After | Delta |
---|---|---|---|
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (+1.1811%) ❗ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.8912 | -0.8912 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -2.4917 | -2.4917 | 0.0000 (0.0000%) ⭕ |
design__core__area | 9283.9000 | 9283.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 12970.7000 | 12970.7000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 5225.0100 | 5225.0100 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 133 | 133 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.8955 | -0.8955 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.5893 | -0.5893 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -2.7967 | -2.7967 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -2.4917 | -2.4917 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 133 | 133 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -1.5758 | -1.5758 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -1.2732 | -1.2732 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.8912 | -0.8912 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.5851 | -0.5851 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -2.7748 | -2.7748 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -2.4698 | -2.4698 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 133 | 133 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -1.5667 | -1.5667 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -1.2642 | -1.2642 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.8954 | -0.8954 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.5893 | -0.5893 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -2.7882 | -2.7882 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -2.4832 | -2.4832 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 133 | 133 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -1.5734 | -1.5734 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -1.2709 | -1.2709 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_DMAC_AHBL
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 1.5870 | 1.5870 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 1.2442 | 1.2442 | 0.0000 (0.0000%) ⭕ |
design__core__area | 19398.6000 | 19398.6000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 24521.5000 | 24521.5000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 15616.2000 | 15616.2000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 15 | 15 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0013 | 0.0013 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0013 | 0.0013 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0007 | 0.0007 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0020 | 0.0020 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -82.7157 | -82.7157 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -4.3222 | -4.3222 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 90 | 90 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.3545 | 0.3545 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 1.2739 | 1.2739 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 1.5870 | 1.5870 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 3.3234 | 3.3234 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | -82.7157 | -82.7157 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | -4.3222 | -4.3222 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 31 | 31 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.6984 | 0.6984 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 1.8516 | 1.8516 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.3295 | 0.3295 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 1.2442 | 1.2442 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 1.5206 | 1.5206 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 3.2319 | 3.2319 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | -71.2865 | -71.2865 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | -3.8690 | -3.8690 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 29 | 29 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.6614 | 0.6614 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 1.8014 | 1.8014 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.3403 | 0.3403 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 1.2586 | 1.2586 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 1.5500 | 1.5500 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 3.2781 | 3.2781 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | -76.6332 | -76.6332 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | -4.0879 | -4.0879 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 30 | 30 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.6773 | 0.6773 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 1.8267 | 1.8267 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_SPI_XIP_CACHE
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 35 | 35 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 40 | 40 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2925 | -0.2925 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2871 | 0.2871 | 0.0000 (0.0000%) ⭕ |
design__core__area | 189382 | 189382 | 0 (0.0000%) ⭕ |
design__die__area | 204054 | 204054 | 0 (0.0000%) ⭕ |
design__instance__area | 140406 | 140406 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 164 | 164 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 255 | 255 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0150 | 0.0150 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0064 | 0.0064 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0214 | 0.0214 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | -2.3781 | -2.3781 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | -0.6410 | -0.6410 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 20 | 20 | 0 (0.0000%) ⭕ |
timing__setup__tns | -94.6947 | -94.6947 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -3.7626 | -3.7626 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 136 | 136 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.3033 | -0.3033 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3003 | 0.3003 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 164 | 164 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.3656 | -0.3656 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.3515 | 0.3515 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 164 | 164 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 255 | 255 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | -2.3781 | -2.3781 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | -0.6410 | -0.6410 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 13 | 13 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | -94.6947 | -94.6947 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | -3.7626 | -3.7626 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 47 | 47 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.3248 | -0.3248 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.3178 | 0.3178 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 8 | 8 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 164 | 164 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 12 | 12 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2925 | -0.2925 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2871 | 0.2871 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 164 | 164 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.3430 | -0.3430 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.3267 | 0.3267 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 164 | 164 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 138 | 138 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | -1.3749 | -1.3749 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | -0.4584 | -0.4584 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | -61.4094 | -61.4094 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | -2.6600 | -2.6600 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 42 | 42 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.3103 | -0.3103 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.3003 | 0.3003 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 164 | 164 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2978 | -0.2978 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2920 | 0.2920 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 164 | 164 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.3547 | -0.3547 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.3371 | 0.3371 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 164 | 164 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 194 | 194 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | -1.6309 | -1.6309 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | -0.5421 | -0.5421 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | -78.4691 | -78.4691 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | -3.2416 | -3.2416 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 47 | 47 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.3176 | -0.3176 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.3078 | 0.3078 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 164 | 164 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 9 | 9 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_upw_new
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -3.2920 | -3.2920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2992 | 0.2992 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 656000 | 656000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0095 | 0.0095 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0035 | 0.0035 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0130 | 0.0130 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.3127 | -3.3127 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3206 | 0.3206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.6492 | -3.6492 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.6638 | 0.6638 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.4170 | -3.4170 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.4268 | 0.4268 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.2920 | -3.2920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2992 | 0.2992 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.6017 | -3.6017 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.6147 | 0.6147 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.3863 | -3.3863 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.3956 | 0.3956 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.3007 | -3.3007 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.3085 | 0.3085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.6238 | -3.6238 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.6379 | 0.6379 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.3998 | -3.3998 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.4097 | 0.4097 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_upw_old
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -3.2920 | -3.2920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2992 | 0.2992 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 656000 | 656000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0095 | 0.0095 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0035 | 0.0035 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0130 | 0.0130 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.3127 | -3.3127 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3206 | 0.3206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.6492 | -3.6492 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.6638 | 0.6638 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.4170 | -3.4170 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.4268 | 0.4268 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.2920 | -3.2920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2992 | 0.2992 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.6017 | -3.6017 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.6147 | 0.6147 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.3863 | -3.3863 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.3956 | 0.3956 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.3007 | -3.3007 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.3085 | 0.3085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.6238 | -3.6238 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.6379 | 0.6379 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.3998 | -3.3998 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.4097 | 0.4097 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/blink
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2531 | -0.2531 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2531 | 0.2531 | 0.0000 (0.0000%) ⭕ |
design__core__area | 2454.8500 | 2454.8500 | 0.0000 (0.0000%) ⭕ |
design__die__area | 4413.4900 | 4413.4900 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 1407.6000 | 1407.6000 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2546 | -0.2546 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2547 | 0.2547 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2577 | -0.2577 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2578 | 0.2578 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2557 | -0.2557 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2557 | 0.2557 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2531 | -0.2531 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2531 | 0.2531 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2563 | -0.2563 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2563 | 0.2563 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2540 | -0.2540 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2540 | 0.2540 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2537 | -0.2537 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2537 | 0.2537 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2569 | -0.2569 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2569 | 0.2569 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2546 | -0.2546 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2547 | 0.2547 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/caravel_upw
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 1080000 | 1080000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 1101 | 1101 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__switching__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__total | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 240 | 240 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/cell_inverter
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/dual_spm
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2536 | -0.2536 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2536 | 0.2536 | 0.0000 (0.0000%) ⭕ |
design__core__area | 232536 | 232536 | 0 (0.0000%) ⭕ |
design__die__area | 250000 | 250000 | 0 (0.0000%) ⭕ |
design__instance__area | 22972.4000 | 22972.4000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0019 | 0.0019 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0027 | 0.0027 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2550 | -0.2550 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2552 | 0.2552 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2579 | -0.2579 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2581 | 0.2581 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2558 | -0.2558 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2559 | 0.2559 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2536 | -0.2536 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2536 | 0.2536 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2558 | -0.2558 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2558 | 0.2558 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2544 | -0.2544 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2544 | 0.2544 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2541 | -0.2541 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2541 | 0.2541 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2566 | -0.2566 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2566 | 0.2566 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2549 | -0.2549 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2549 | 0.2549 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/gcd
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 2 | 2 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 2 | 2 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2571 | -0.2571 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2571 | 0.2571 | 0.0000 (0.0000%) ⭕ |
design__core__area | 67039.3000 | 67039.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 78425.2000 | 78425.2000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 4379.2000 | 4379.2000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 9 | 9 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2610 | -0.2610 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2610 | 0.2610 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2697 | -0.2697 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2697 | 0.2697 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 9 | 9 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2633 | -0.2633 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2633 | 0.2633 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2571 | -0.2571 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2571 | 0.2571 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2654 | -0.2654 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2654 | 0.2654 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2590 | -0.2590 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2590 | 0.2590 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2585 | -0.2585 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2585 | 0.2585 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2670 | -0.2670 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2670 | 0.2670 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2606 | -0.2606 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2606 | 0.2606 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/inverter
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 1051.0100 | 1051.0100 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
design__instance__area | 18.7680 | 18.7680 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/io_placer
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 12273800 | 12273800 | 0 (0.0000%) ⭕ |
design__die__area | 12390400 | 12390400 | 0 (0.0000%) ⭕ |
design__instance__area | 1080000 | 1080000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 1101 | 1101 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__switching__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__total | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 240 | 240 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 367 | 367 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 1101 | 1101 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch_bad
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch_good
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/manual_macro_placement_test
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
design__core__area | 80146.9000 | 80146.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 90000 | 90000 | 0 (0.0000%) ⭕ |
design__instance__area | 23540.6000 | 23540.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0354 | 0.0354 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0354 | 0.0354 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0143 | 0.0143 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0143 | 0.0143 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0140 | 0.0140 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0140 | 0.0140 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0202 | 0.0202 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0202 | 0.0202 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0193 | 0.0193 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0193 | 0.0193 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0198 | 0.0198 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0198 | 0.0198 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/s44
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2527 | -0.2527 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2506 | 0.2506 | 0.0000 (0.0000%) ⭕ |
design__core__area | 33280.7000 | 33280.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 39709.7000 | 39709.7000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 2613.7600 | 2613.7600 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2541 | -0.2541 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2516 | 0.2516 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2563 | -0.2563 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2515 | 0.2515 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2549 | -0.2549 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2516 | 0.2516 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2527 | -0.2527 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2507 | 0.2507 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2543 | -0.2543 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2506 | 0.2506 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2535 | -0.2535 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2507 | 0.2507 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2531 | -0.2531 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2509 | 0.2509 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2550 | -0.2550 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2509 | 0.2509 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2539 | -0.2539 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2509 | 0.2509 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/spm
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2555 | -0.2555 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2555 | 0.2555 | 0.0000 (0.0000%) ⭕ |
design__core__area | 8051.4700 | 8051.4700 | 0.0000 (0.0000%) ⭕ |
design__die__area | 11317.8000 | 11317.8000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 3701.0500 | 3701.0500 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0013 | 0.0013 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0014 | 0.0014 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2591 | -0.2591 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2591 | 0.2591 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2661 | -0.2661 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2661 | 0.2661 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2607 | -0.2607 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2607 | 0.2607 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2555 | -0.2555 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2555 | 0.2555 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2613 | -0.2613 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2613 | 0.2613 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2568 | -0.2568 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2568 | 0.2568 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2566 | -0.2566 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2567 | 0.2567 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2632 | -0.2632 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2632 | 0.2632 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2581 | -0.2581 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2581 | 0.2581 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/test_sram_macro
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 6 | 6 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 6 | 6 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.3748 | -0.3748 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__core__area | 906252 | 906252 | 0 (0.0000%) ⭕ |
design__die__area | 937500 | 937500 | 0 (0.0000%) ⭕ |
design__instance__area | 396005 | 396005 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 16 | 16 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 194 | 194 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 5666674 | 5666674 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0020 | 0.0020 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.3748 | -0.3748 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 46 | 46 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.6456 | -0.6456 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 16 | 16 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 194 | 194 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.4841 | -0.4841 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 141 | 141 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.3811 | -0.3811 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 24 | 24 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.5983 | -0.5983 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 154 | 154 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.4657 | -0.4657 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 123 | 123 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.3811 | -0.3811 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 33 | 33 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.6265 | -0.6265 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 173 | 173 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.4800 | -0.4800 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 139 | 139 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2619 | -0.2619 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2612 | 0.2612 | 0.0000 (0.0000%) ⭕ |
design__core__area | 24319.6000 | 24319.6000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 30066.6000 | 30066.6000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 11966.5000 | 11966.5000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 13 | 13 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0011 | 0.0011 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0015 | 0.0015 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2667 | -0.2667 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2640 | 0.2640 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2775 | -0.2775 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2748 | 0.2748 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 13 | 13 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2704 | -0.2704 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2676 | 0.2676 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2619 | -0.2619 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2612 | 0.2612 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2706 | -0.2706 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2705 | 0.2705 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 6 | 6 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2649 | -0.2649 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2643 | 0.2643 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2636 | -0.2636 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2622 | 0.2622 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2734 | -0.2734 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2725 | 0.2725 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 10 | 10 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2669 | -0.2669 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2655 | 0.2655 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb_cdc_core
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.3638 | -0.3638 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.3733 | 0.3733 | 0.0000 (0.0000%) ⭕ |
design__core__area | 61711.7000 | 61711.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 70647.5000 | 70647.5000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 24750 | 24750 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 33 | 33 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 8 | 8 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0019 | 0.0019 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0027 | 0.0027 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.3727 | -0.3727 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3794 | 0.3794 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 33 | 33 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.5708 | -0.5708 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.5916 | 0.5916 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 33 | 33 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 8 | 8 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.4302 | -0.4302 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.4405 | 0.4405 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 33 | 33 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.3638 | -0.3638 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.3733 | 0.3733 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 33 | 33 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.5551 | -0.5551 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.5766 | 0.5766 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 33 | 33 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.4200 | -0.4200 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.4323 | 0.4323 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 33 | 33 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.3670 | -0.3670 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.3763 | 0.3763 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 33 | 33 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.5616 | -0.5616 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.5843 | 0.5843 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 33 | 33 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.4241 | -0.4241 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.4364 | 0.4364 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 33 | 33 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/user_proj_timer
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2547 | -0.2547 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2546 | 0.2546 | 0.0000 (0.0000%) ⭕ |
design__core__area | 655604 | 655604 | 0 (0.0000%) ⭕ |
design__die__area | 700000 | 700000 | 0 (0.0000%) ⭕ |
design__instance__area | 17988.5000 | 17988.5000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 34 | 34 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2586 | -0.2586 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2586 | 0.2586 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2644 | -0.2644 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2643 | 0.2643 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 34 | 34 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2594 | -0.2594 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2593 | 0.2593 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2547 | -0.2547 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2546 | 0.2546 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2599 | -0.2599 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2598 | 0.2598 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2558 | -0.2558 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2557 | 0.2557 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2556 | -0.2556 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2556 | 0.2556 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2615 | -0.2615 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2615 | 0.2615 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2569 | -0.2569 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2569 | 0.2569 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/wbqspiflash
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 6 | 6 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 6 | 6 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.3748 | -0.3748 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.3738 | 0.3738 | 0.0000 (0.0000%) ⭕ |
design__core__area | 74196.2000 | 74196.2000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 83741 | 83741 | 0 (0.0000%) ⭕ |
design__instance__area | 27406.3000 | 27406.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 28 | 28 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0035 | 0.0035 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0037 | 0.0037 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0071 | 0.0071 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.3811 | -0.3811 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3804 | 0.3804 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.5882 | -0.5882 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.5882 | 0.5882 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 28 | 28 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.4422 | -0.4422 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.4422 | 0.4422 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.3748 | -0.3748 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.3738 | 0.3738 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.5720 | -0.5720 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.5720 | 0.5720 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.4331 | -0.4331 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.4331 | 0.4331 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.3769 | -0.3769 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.3769 | 0.3769 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.5794 | -0.5794 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.5794 | 0.5794 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 22 | 22 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.4376 | -0.4376 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.4376 | 0.4376 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 40 | 40 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/xtea
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2630 | -0.2630 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2663 | 0.2663 | 0.0000 (0.0000%) ⭕ |
design__core__area | 52445.3000 | 52445.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 60511.9000 | 60511.9000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 24922.7000 | 24922.7000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 16 | 16 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0011 | 0.0011 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0042 | 0.0042 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0051 | 0.0051 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0093 | 0.0093 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2640 | -0.2640 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2698 | 0.2698 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2780 | -0.2780 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2881 | 0.2881 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 16 | 16 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2685 | -0.2685 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2759 | 0.2759 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2630 | -0.2630 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2663 | 0.2663 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2754 | -0.2754 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2817 | 0.2817 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2672 | -0.2672 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2715 | 0.2715 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2637 | -0.2637 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2681 | 0.2681 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2772 | -0.2772 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2852 | 0.2852 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 16 | 16 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2682 | -0.2682 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2739 | 0.2739 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/zipdiv
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2687 | -0.2687 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2688 | 0.2688 | 0.0000 (0.0000%) ⭕ |
design__core__area | 31230 | 31230 | 0 (0.0000%) ⭕ |
design__die__area | 37409.7000 | 37409.7000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 13329 | 13329 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 12 | 12 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2748 | -0.2748 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2750 | 0.2750 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2915 | -0.2915 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2917 | 0.2917 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2810 | -0.2810 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2813 | 0.2813 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2687 | -0.2687 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2688 | 0.2688 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2817 | -0.2817 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2818 | 0.2818 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2738 | -0.2738 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2739 | 0.2739 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2712 | -0.2712 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2714 | 0.2714 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2862 | -0.2862 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2864 | 0.2864 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2769 | -0.2769 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2771 | 0.2771 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |