gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/APU
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.4453 | -0.4453 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.4794 | 0.4794 | 0.0000 (0.0000%) ⭕ |
design__core__area | 284217 | 284217 | 0 (0.0000%) ⭕ |
design__die__area | 308622 | 308622 | 0 (0.0000%) ⭕ |
design__instance__area | 110658 | 110658 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 163 | 163 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0100 | 0.0100 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0055 | 0.0055 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0154 | 0.0154 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.4508 | -0.4508 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.4918 | 0.4918 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 163 | 163 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.8044 | -0.8044 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.8980 | 0.8980 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 21 | 21 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 163 | 163 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.5597 | -0.5597 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.6173 | 0.6173 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 163 | 163 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.4453 | -0.4453 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.4794 | 0.4794 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 163 | 163 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.7913 | -0.7913 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.8701 | 0.8701 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 163 | 163 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.5518 | -0.5518 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.6001 | 0.6001 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 163 | 163 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.4478 | -0.4478 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.4851 | 0.4851 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 163 | 163 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.7973 | -0.7973 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.8828 | 0.8828 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 18 | 18 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 163 | 163 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.5554 | -0.5554 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.6080 | 0.6080 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 18 | 18 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 163 | 163 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/blink
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2518 | -0.2518 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2516 | 0.2516 | 0.0000 (0.0000%) ⭕ |
design__core__area | 6146.5600 | 6146.5600 | 0.0000 (0.0000%) ⭕ |
design__die__area | 10108.6000 | 10108.6000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 4168.6800 | 4168.6800 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0007 | 0.0007 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0028 | 0.0028 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0034 | 0.0034 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2523 | -0.2523 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2521 | 0.2521 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2529 | -0.2529 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2527 | 0.2527 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2525 | -0.2525 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2523 | 0.2523 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2518 | -0.2518 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2516 | 0.2516 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2521 | -0.2521 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2519 | 0.2519 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2519 | -0.2519 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2517 | 0.2517 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2520 | -0.2520 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2518 | 0.2518 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2525 | -0.2525 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2523 | 0.2523 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2522 | -0.2522 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2520 | 0.2520 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/cell_inverter
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 8.7808 | 8.7808 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/inverter
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 570.7520 | 570.7520 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
design__instance__area | 57.0752 | 57.0752 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch_bad
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch_good
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/spm
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2559 | -0.2559 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2547 | 0.2547 | 0.0000 (0.0000%) ⭕ |
design__core__area | 21280.3000 | 21280.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 28670.3000 | 28670.3000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 11709.2000 | 11709.2000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0011 | 0.0011 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0072 | 0.0072 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0022 | 0.0022 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0094 | 0.0094 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2576 | -0.2576 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2564 | 0.2564 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2699 | -0.2699 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2634 | 0.2634 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2614 | -0.2614 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2585 | 0.2585 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2559 | -0.2559 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2547 | 0.2547 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2653 | -0.2653 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2598 | 0.2598 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2588 | -0.2588 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2563 | 0.2563 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2566 | -0.2566 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2555 | 0.2555 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2674 | -0.2674 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2615 | 0.2615 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2600 | -0.2600 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2573 | 0.2573 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2647 | -0.2647 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2653 | 0.2653 | 0.0000 (0.0000%) ⭕ |
design__core__area | 59885.1000 | 59885.1000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 72420.7000 | 72420.7000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 31891.9000 | 31891.9000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0164 | 0.0164 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0061 | 0.0061 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0225 | 0.0225 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2700 | -0.2700 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2699 | 0.2699 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2955 | -0.2955 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2963 | 0.2963 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2782 | -0.2782 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2784 | 0.2784 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2647 | -0.2647 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2653 | 0.2653 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2832 | -0.2832 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2856 | 0.2856 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2707 | -0.2707 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2719 | 0.2719 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2671 | -0.2671 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2674 | 0.2674 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2889 | -0.2889 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2905 | 0.2905 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2742 | -0.2742 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2749 | 0.2749 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 14 | 14 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb_cdc_core
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.4354 | -0.4354 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.4380 | 0.4380 | 0.0000 (0.0000%) ⭕ |
design__core__area | 157640 | 157640 | 0 (0.0000%) ⭕ |
design__die__area | 177207 | 177207 | 0 (0.0000%) ⭕ |
design__instance__area | 73923.4000 | 73923.4000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 80 | 80 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0014 | 0.0014 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0574 | 0.0574 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0223 | 0.0223 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0798 | 0.0798 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -71.0631 | -71.0631 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -2.1816 | -2.1816 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 153 | 153 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 186 | 186 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.4409 | -0.4409 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.4429 | 0.4429 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 80 | 80 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.7731 | -0.7731 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.7807 | 0.7807 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 10 | 10 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 80 | 80 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | -71.0631 | -71.0631 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | -2.1816 | -2.1816 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 54 | 54 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 65 | 65 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.5423 | -0.5423 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.5471 | 0.5471 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 80 | 80 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.4354 | -0.4354 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.4380 | 0.4380 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 80 | 80 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.7596 | -0.7596 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.7700 | 0.7700 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 80 | 80 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | -54.2446 | -54.2446 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | -1.9176 | -1.9176 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 47 | 47 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 58 | 58 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.5348 | -0.5348 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.5403 | 0.5403 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 80 | 80 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.4380 | -0.4380 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.4403 | 0.4403 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 80 | 80 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.7656 | -0.7656 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.7746 | 0.7746 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 80 | 80 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | -61.6196 | -61.6196 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | -2.0292 | -2.0292 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 52 | 52 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 63 | 63 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.5382 | -0.5382 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.5434 | 0.5434 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 80 | 80 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/wbqspiflash
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.4321 | -0.4321 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.4286 | 0.4286 | 0.0000 (0.0000%) ⭕ |
design__core__area | 94345.3000 | 94345.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 109560 | 109560 | 0 (0.0000%) ⭕ |
design__instance__area | 68769 | 68769 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0025 | 0.0025 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0120 | 0.0120 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.1187 | 0.1187 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0879 | 0.0879 | 0.0000 (0.0000%) ⭕ |
power__total | 0.2067 | 0.2067 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -404.1298 | -404.1298 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -3.6249 | -3.6249 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 448 | 448 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 451 | 451 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.4394 | -0.4394 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.4338 | 0.4338 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.7733 | -0.7733 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.7591 | 0.7591 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | -404.1298 | -404.1298 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | -3.6249 | -3.6249 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 150 | 150 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 151 | 151 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.5425 | -0.5425 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.5343 | 0.5343 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.4321 | -0.4321 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.4286 | 0.4286 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.7549 | -0.7549 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.7454 | 0.7454 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | -318.2667 | -318.2667 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | -2.8119 | -2.8119 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 149 | 149 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 150 | 150 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.5318 | -0.5318 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.5264 | 0.5264 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.4355 | -0.4355 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.4310 | 0.4310 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.7633 | -0.7633 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.7517 | 0.7517 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | -357.1103 | -357.1103 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | -3.1743 | -3.1743 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 149 | 149 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 150 | 150 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.5367 | -0.5367 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.5300 | 0.5300 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/zipdiv
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2708 | -0.2708 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2708 | 0.2708 | 0.0000 (0.0000%) ⭕ |
design__core__area | 73310.9000 | 73310.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 86150 | 86150 | 0 (0.0000%) ⭕ |
design__instance__area | 36192.3000 | 36192.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0015 | 0.0015 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0205 | 0.0205 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0111 | 0.0111 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0316 | 0.0316 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -227.2777 | -227.2777 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -4.8488 | -4.8488 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 186 | 186 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 186 | 186 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2760 | -0.2760 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2767 | 0.2767 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.3154 | -0.3154 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.3154 | 0.3154 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | -227.2777 | -227.2777 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | -4.8488 | -4.8488 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 63 | 63 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 63 | 63 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2886 | -0.2886 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2886 | 0.2886 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2708 | -0.2708 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2708 | 0.2708 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.3023 | -0.3023 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.3023 | 0.3023 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | -208.3596 | -208.3596 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | -4.3687 | -4.3687 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 61 | 61 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 61 | 61 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2808 | -0.2808 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2808 | 0.2808 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2732 | -0.2732 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2734 | 0.2734 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.3083 | -0.3083 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.3083 | 0.3083 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | -216.9541 | -216.9541 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | -4.5875 | -4.5875 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 62 | 62 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 62 | 62 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2843 | -0.2843 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2844 | 0.2844 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/APU
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.3652 | -0.3652 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.3649 | 0.3649 | 0.0000 (0.0000%) ⭕ |
design__core__area | 83157.3000 | 83157.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 92941.4000 | 92941.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 33422.1000 | 33422.1000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 49 | 49 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 21 | 21 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0023 | 0.0023 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0013 | 0.0013 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0036 | 0.0036 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.3704 | -0.3704 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3706 | 0.3706 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 49 | 49 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.5585 | -0.5585 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.5601 | 0.5601 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 49 | 49 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 21 | 21 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.4260 | -0.4260 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.4265 | 0.4265 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 49 | 49 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.3652 | -0.3652 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.3649 | 0.3649 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 49 | 49 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.5453 | -0.5453 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.5474 | 0.5474 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 49 | 49 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.4183 | -0.4183 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.4187 | 0.4187 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 49 | 49 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.3667 | -0.3667 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.3675 | 0.3675 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 49 | 49 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.5508 | -0.5508 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.5530 | 0.5530 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 49 | 49 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 18 | 18 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.4207 | -0.4207 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.4223 | 0.4223 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 49 | 49 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_GPIO
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2511 | -0.2511 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2503 | 0.2503 | 0.0000 (0.0000%) ⭕ |
design__core__area | 1670.3500 | 1670.3500 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2700.3500 | 2700.3500 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 1358.8000 | 1358.8000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2521 | -0.2521 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2510 | 0.2510 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2533 | -0.2533 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2510 | 0.2510 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2523 | -0.2523 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2510 | 0.2510 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2511 | -0.2511 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2503 | 0.2503 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2518 | -0.2518 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2503 | 0.2503 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2512 | -0.2512 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2503 | 0.2503 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2514 | -0.2514 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2505 | 0.2505 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2524 | -0.2524 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2504 | 0.2504 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2516 | -0.2516 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2504 | 0.2504 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_PSRAM_CTRL_V2
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2539 | -0.2539 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2535 | 0.2535 | 0.0000 (0.0000%) ⭕ |
design__core__area | 8051.4700 | 8051.4700 | 0.0000 (0.0000%) ⭕ |
design__die__area | 11313.5000 | 11313.5000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 5660.4300 | 5660.4300 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -0.0798 | -0.0798 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -0.0798 | -0.0798 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 2 | 2 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2558 | -0.2558 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2543 | 0.2543 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2592 | -0.2592 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2578 | 0.2578 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | -0.0798 | -0.0798 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | -0.0798 | -0.0798 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2568 | -0.2568 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2553 | 0.2553 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2539 | -0.2539 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2535 | 0.2535 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2568 | -0.2568 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2564 | 0.2564 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2547 | -0.2547 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2543 | 0.2543 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2545 | -0.2545 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2539 | 0.2539 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2580 | -0.2580 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2574 | 0.2574 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | -0.0096 | -0.0096 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | -0.0096 | -0.0096 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2555 | -0.2555 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2549 | 0.2549 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_TCC32
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.1087 | -0.1087 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.1069 | 0.1069 | 0.0000 (0.0000%) ⭕ |
design__core__area | 11369.7000 | 11369.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 15327.4000 | 15327.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 9387.7500 | 9387.7500 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0013 | 0.0013 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0023 | 0.0023 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1123 | -0.1123 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1095 | 0.1095 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.1260 | -0.1260 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.1206 | 0.1206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.1161 | -0.1161 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.1128 | 0.1128 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.1087 | -0.1087 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1069 | 0.1069 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.1205 | -0.1205 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.1172 | 0.1172 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.1117 | -0.1117 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.1095 | 0.1095 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1102 | -0.1102 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1082 | 0.1082 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.1229 | -0.1229 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.1188 | 0.1188 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.1136 | -0.1136 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.1111 | 0.1111 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_UART
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 6 | 6 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 6 | 6 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.1258 | -0.1258 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.1176 | 0.1176 | 0.0000 (0.0000%) ⭕ |
design__core__area | 22502.8000 | 22502.8000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 27887 | 27887 | 0 (0.0000%) ⭕ |
design__instance__area | 19716.4000 | 19716.4000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 23 | 23 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0023 | 0.0023 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0032 | 0.0032 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0050 | 0.0050 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1353 | -0.1353 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1209 | 0.1209 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 23 | 23 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.1616 | -0.1616 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.1398 | 0.1398 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 23 | 23 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.1450 | -0.1450 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.1283 | 0.1283 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 23 | 23 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.1258 | -0.1258 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1176 | 0.1176 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 23 | 23 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.1463 | -0.1463 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.1328 | 0.1328 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 23 | 23 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.1337 | -0.1337 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.1240 | 0.1240 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 23 | 23 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1289 | -0.1289 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1184 | 0.1184 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 23 | 23 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.1514 | -0.1514 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.1346 | 0.1346 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 23 | 23 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.1370 | -0.1370 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.1248 | 0.1248 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 23 | 23 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_CLK_RST
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.9037 | -0.9037 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -2.5291 | -2.5291 | 0.0000 (0.0000%) ⭕ |
design__core__area | 9240.1100 | 9240.1100 | 0.0000 (0.0000%) ⭕ |
design__die__area | 12880.8000 | 12880.8000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 5177.4700 | 5177.4700 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 133 | 133 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.9069 | -0.9069 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.6004 | -0.6004 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -2.8341 | -2.8341 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -2.5291 | -2.5291 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 133 | 133 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -1.5924 | -1.5924 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -1.2897 | -1.2897 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.9037 | -0.9037 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.5974 | -0.5974 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -2.8081 | -2.8081 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -2.5031 | -2.5031 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 133 | 133 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -1.5839 | -1.5839 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -1.2812 | -1.2812 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.9087 | -0.9087 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.6023 | -0.6023 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -2.8251 | -2.8251 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -2.5201 | -2.5201 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 133 | 133 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -1.5918 | -1.5918 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -1.2890 | -1.2890 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_DMAC_AHBL
Metric | Before | After | Delta |
---|---|---|---|
ir__drop__avg | 0.0003 | 0.0004 | 0.0000 (+0.2865%) ❗ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 1.6498 | 1.6498 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 1.2405 | 1.2405 | 0.0000 (0.0000%) ⭕ |
design__core__area | 19398.6000 | 19398.6000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 24435.4000 | 24435.4000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 15442.3000 | 15442.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 5 | 5 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0013 | 0.0013 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0020 | 0.0020 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | -81.6305 | -81.6305 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -4.0084 | -4.0084 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 92 | 92 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.3748 | 0.3748 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 1.2866 | 1.2866 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 1.6498 | 1.6498 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 3.3847 | 3.3847 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | -81.6305 | -81.6305 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | -4.0084 | -4.0084 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.7349 | 0.7349 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 1.8695 | 1.8695 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.3528 | 0.3528 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 1.2405 | 1.2405 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 1.5772 | 1.5772 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 3.2607 | 3.2607 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | -71.8556 | -71.8556 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | -3.6499 | -3.6499 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 30 | 30 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.6926 | 0.6926 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 1.7954 | 1.7954 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.3669 | 0.3669 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 1.2676 | 1.2676 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 1.6140 | 1.6140 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 3.3296 | 3.3296 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | -76.5412 | -76.5412 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | -3.8246 | -3.8246 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 30 | 30 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.7141 | 0.7141 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 1.8374 | 1.8374 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_SPI_XIP_CACHE
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 58 | 58 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 78 | 78 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.3093 | -0.3093 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.3184 | 0.3184 | 0.0000 (0.0000%) ⭕ |
design__core__area | 207279 | 207279 | 0 (0.0000%) ⭕ |
design__die__area | 223714 | 223714 | 0 (0.0000%) ⭕ |
design__instance__area | 149284 | 149284 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 43 | 43 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 221 | 221 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 439 | 439 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0020 | 0.0020 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0160 | 0.0160 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0076 | 0.0076 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0236 | 0.0236 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | -3.6390 | -3.6390 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | -0.2293 | -0.2293 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 62 | 62 | 0 (0.0000%) ⭕ |
timing__setup__tns | -68.6819 | -68.6819 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | -2.5638 | -2.5638 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 96 | 96 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.3264 | -0.3264 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3352 | 0.3352 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 28 | 28 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 221 | 221 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 49 | 49 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.4097 | -0.4097 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.4286 | 0.4286 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 43 | 43 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 221 | 221 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 439 | 439 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | -3.6390 | -3.6390 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | -0.2293 | -0.2293 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 26 | 26 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | -68.6819 | -68.6819 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | -2.5638 | -2.5638 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.3543 | -0.3543 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.3670 | 0.3670 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 28 | 28 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 221 | 221 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 140 | 140 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.3093 | -0.3093 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.3184 | 0.3184 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 221 | 221 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.3805 | -0.3805 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.3972 | 0.3972 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 221 | 221 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 338 | 338 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | -0.5274 | -0.5274 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | -0.0603 | -0.0603 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 18 | 18 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | -41.9287 | -41.9287 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | -1.7608 | -1.7608 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.3329 | -0.3329 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.3452 | 0.3452 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 7 | 7 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 221 | 221 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 58 | 58 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.3176 | -0.3176 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.3272 | 0.3272 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 221 | 221 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 43 | 43 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.3953 | -0.3953 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.4137 | 0.4137 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 33 | 33 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 221 | 221 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 374 | 374 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | -1.8472 | -1.8472 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | -0.1375 | -0.1375 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 18 | 18 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | -55.4686 | -55.4686 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | -2.1821 | -2.1821 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.3441 | -0.3441 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.3573 | 0.3573 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 20 | 20 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 221 | 221 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 77 | 77 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_upw_new
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -3.2920 | -3.2920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2992 | 0.2992 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 656000 | 656000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0094 | 0.0094 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0128 | 0.0128 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.3127 | -3.3127 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3206 | 0.3206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.6492 | -3.6492 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.6638 | 0.6638 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.4170 | -3.4170 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.4268 | 0.4268 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.2920 | -3.2920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2992 | 0.2992 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.6017 | -3.6017 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.6147 | 0.6147 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.3863 | -3.3863 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.3956 | 0.3956 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.3007 | -3.3007 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.3085 | 0.3085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.6238 | -3.6238 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.6379 | 0.6379 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.3998 | -3.3998 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.4097 | 0.4097 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_upw_old
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -3.2920 | -3.2920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2992 | 0.2992 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 656000 | 656000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0094 | 0.0094 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0128 | 0.0128 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.3127 | -3.3127 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3206 | 0.3206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.6492 | -3.6492 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.6638 | 0.6638 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.4170 | -3.4170 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.4268 | 0.4268 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.2920 | -3.2920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2992 | 0.2992 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.6017 | -3.6017 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.6147 | 0.6147 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.3863 | -3.3863 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.3956 | 0.3956 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.3007 | -3.3007 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.3085 | 0.3085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.6238 | -3.6238 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.6379 | 0.6379 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.3998 | -3.3998 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.4097 | 0.4097 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/blink
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2521 | -0.2521 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2521 | 0.2521 | 0.0000 (0.0000%) ⭕ |
design__core__area | 2387.2900 | 2387.2900 | 0.0000 (0.0000%) ⭕ |
design__die__area | 4273.3200 | 4273.3200 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 1401.3400 | 1401.3400 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2532 | -0.2532 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2532 | 0.2532 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2557 | -0.2557 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2557 | 0.2557 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2538 | -0.2538 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2538 | 0.2538 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2521 | -0.2521 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2521 | 0.2521 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2541 | -0.2541 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2541 | 0.2541 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2526 | -0.2526 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2526 | 0.2526 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2526 | -0.2526 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2526 | 0.2526 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2548 | -0.2548 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2548 | 0.2548 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2531 | -0.2531 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2531 | 0.2531 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/caravel_upw
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 1080000 | 1080000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 365 | 365 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 1098 | 1098 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__switching__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__total | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 240 | 240 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 365 | 365 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 365 | 365 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 1098 | 1098 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 365 | 365 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 1095 | 1095 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 360 | 360 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 1074 | 1074 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 360 | 360 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 1098 | 1098 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 360 | 360 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 1095 | 1095 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 1083 | 1083 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 1098 | 1098 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 1095 | 1095 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/cell_inverter
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/dual_spm
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2524 | -0.2524 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2524 | 0.2524 | 0.0000 (0.0000%) ⭕ |
design__core__area | 232536 | 232536 | 0 (0.0000%) ⭕ |
design__die__area | 250000 | 250000 | 0 (0.0000%) ⭕ |
design__instance__area | 22889.8000 | 22889.8000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0007 | 0.0007 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0025 | 0.0025 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2534 | -0.2534 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2534 | 0.2534 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2552 | -0.2552 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2552 | 0.2552 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2541 | -0.2541 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2542 | 0.2542 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2524 | -0.2524 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2524 | 0.2524 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2541 | -0.2541 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2541 | 0.2541 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2530 | -0.2530 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2530 | 0.2530 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2527 | -0.2527 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2527 | 0.2527 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2546 | -0.2546 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2546 | 0.2546 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2534 | -0.2534 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2533 | 0.2533 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/gcd
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2538 | -0.2538 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2538 | 0.2538 | 0.0000 (0.0000%) ⭕ |
design__core__area | 67039.3000 | 67039.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 78425.2000 | 78425.2000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 4524.3400 | 4524.3400 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2550 | -0.2550 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2550 | 0.2550 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2588 | -0.2588 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2588 | 0.2588 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2563 | -0.2563 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2563 | 0.2563 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2538 | -0.2538 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2538 | 0.2538 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2578 | -0.2578 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2578 | 0.2578 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2548 | -0.2548 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2548 | 0.2548 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2541 | -0.2541 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2541 | 0.2541 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2576 | -0.2576 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2576 | 0.2576 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2552 | -0.2552 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2552 | 0.2552 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/inverter
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 1051.0100 | 1051.0100 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
design__instance__area | 18.7680 | 18.7680 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/io_placer
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 12273800 | 12273800 | 0 (0.0000%) ⭕ |
design__die__area | 12390400 | 12390400 | 0 (0.0000%) ⭕ |
design__instance__area | 1080000 | 1080000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 1092 | 1092 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__leakage__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__switching__total | 0 | 0 | 0 (0.0000%) ⭕ |
power__total | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 240 | 240 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 1092 | 1092 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 1092 | 1092 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 1092 | 1092 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch_bad
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch_good
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/manual_macro_placement_test
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 80146.9000 | 80146.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 90000 | 90000 | 0 (0.0000%) ⭕ |
design__instance__area | 23540.6000 | 23540.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/s44
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2518 | -0.2518 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2505 | 0.2505 | 0.0000 (0.0000%) ⭕ |
design__core__area | 33280.7000 | 33280.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 39709.7000 | 39709.7000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 2626.2700 | 2626.2700 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2525 | -0.2525 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2512 | 0.2512 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2539 | -0.2539 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2514 | 0.2514 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2532 | -0.2532 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2512 | 0.2512 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2518 | -0.2518 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2505 | 0.2505 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2528 | -0.2528 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2515 | 0.2515 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2523 | -0.2523 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2506 | 0.2506 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2520 | -0.2520 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2507 | 0.2507 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2531 | -0.2531 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2516 | 0.2516 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2526 | -0.2526 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2508 | 0.2508 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/spm
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2565 | -0.2565 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2565 | 0.2565 | 0.0000 (0.0000%) ⭕ |
design__core__area | 8051.4700 | 8051.4700 | 0.0000 (0.0000%) ⭕ |
design__die__area | 11317.8000 | 11317.8000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 3686.0400 | 3686.0400 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2610 | -0.2610 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2610 | 0.2610 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2653 | -0.2653 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2653 | 0.2653 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2620 | -0.2620 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2620 | 0.2620 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2565 | -0.2565 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2565 | 0.2565 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2600 | -0.2600 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2601 | 0.2601 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2574 | -0.2574 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2575 | 0.2575 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2579 | -0.2579 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2579 | 0.2579 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2618 | -0.2618 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2618 | 0.2618 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2588 | -0.2588 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2588 | 0.2588 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/test_sram_macro
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 11 | 11 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 13 | 13 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.3896 | -0.3896 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__core__area | 906252 | 906252 | 0 (0.0000%) ⭕ |
design__die__area | 937500 | 937500 | 0 (0.0000%) ⭕ |
design__instance__area | 395731 | 395731 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 18 | 18 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 222 | 222 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 5666674 | 5666674 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0021 | 0.0021 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.3896 | -0.3896 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 46 | 46 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.6904 | -0.6904 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 18 | 18 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 222 | 222 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.5100 | -0.5100 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 144 | 144 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.3992 | -0.3992 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 23 | 23 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.6402 | -0.6402 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 179 | 179 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.4944 | -0.4944 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 83 | 83 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.3972 | -0.3972 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 26 | 26 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.6694 | -0.6694 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 13 | 13 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 192 | 192 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.5074 | -0.5074 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 12 | 12 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 117 | 117 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2553 | -0.2553 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2553 | 0.2553 | 0.0000 (0.0000%) ⭕ |
design__core__area | 24891.4000 | 24891.4000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 30400.6000 | 30400.6000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 11985.2000 | 11985.2000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0015 | 0.0015 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2573 | -0.2573 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2582 | 0.2582 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2614 | -0.2614 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2615 | 0.2615 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2586 | -0.2586 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2591 | 0.2591 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2553 | -0.2553 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2553 | 0.2553 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2586 | -0.2586 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2586 | 0.2586 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2559 | -0.2559 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2559 | 0.2559 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2561 | -0.2561 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2562 | 0.2562 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2600 | -0.2600 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2600 | 0.2600 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2569 | -0.2569 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2569 | 0.2569 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb_cdc_core
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2736 | -0.2736 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2761 | 0.2761 | 0.0000 (0.0000%) ⭕ |
design__core__area | 62620.1000 | 62620.1000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 71190.9000 | 71190.9000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 23010.8000 | 23010.8000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 34 | 34 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0007 | 0.0007 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0024 | 0.0024 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2764 | -0.2764 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2800 | 0.2800 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 34 | 34 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.3082 | -0.3082 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.3135 | 0.3135 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 34 | 34 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2843 | -0.2843 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2884 | 0.2884 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 34 | 34 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2736 | -0.2736 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2761 | 0.2761 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 34 | 34 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.3008 | -0.3008 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.3056 | 0.3056 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 34 | 34 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2803 | -0.2803 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2833 | 0.2833 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 34 | 34 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2756 | -0.2756 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2784 | 0.2784 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 34 | 34 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.3057 | -0.3057 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.3106 | 0.3106 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 34 | 34 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2831 | -0.2831 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2865 | 0.2865 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 34 | 34 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/user_proj_timer
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2540 | -0.2540 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2540 | 0.2540 | 0.0000 (0.0000%) ⭕ |
design__core__area | 655604 | 655604 | 0 (0.0000%) ⭕ |
design__die__area | 700000 | 700000 | 0 (0.0000%) ⭕ |
design__instance__area | 17890.9000 | 17890.9000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 89 | 89 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2566 | -0.2566 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2567 | 0.2567 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2600 | -0.2600 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2600 | 0.2600 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 89 | 89 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2573 | -0.2573 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2574 | 0.2574 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2540 | -0.2540 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2540 | 0.2540 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2567 | -0.2567 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2568 | 0.2568 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 71 | 71 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2546 | -0.2546 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2546 | 0.2546 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2549 | -0.2549 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2549 | 0.2549 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2579 | -0.2579 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2580 | 0.2580 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 71 | 71 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2555 | -0.2555 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2555 | 0.2555 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 6 | 6 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/wbqspiflash
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 2 | 2 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 3 | 3 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.3886 | -0.3886 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.3885 | 0.3885 | 0.0000 (0.0000%) ⭕ |
design__core__area | 74571.5000 | 74571.5000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 84643.5000 | 84643.5000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 27737.9000 | 27737.9000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 39 | 39 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 35 | 35 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0014 | 0.0014 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0030 | 0.0030 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0029 | 0.0029 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0060 | 0.0060 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.4019 | -0.4019 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.4022 | 0.4022 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 39 | 39 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.6272 | -0.6272 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.6262 | 0.6262 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 39 | 39 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 35 | 35 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.4689 | -0.4689 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.4692 | 0.4692 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 39 | 39 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.3886 | -0.3886 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.3885 | 0.3885 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 39 | 39 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.6025 | -0.6025 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.5999 | 0.5999 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 39 | 39 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.4531 | -0.4531 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.4522 | 0.4522 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 39 | 39 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.3938 | -0.3938 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.3940 | 0.3940 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 39 | 39 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.6131 | -0.6131 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.6108 | 0.6108 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 39 | 39 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 14 | 14 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.4600 | -0.4600 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.4596 | 0.4596 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 39 | 39 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/xtea
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2617 | -0.2617 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2623 | 0.2623 | 0.0000 (0.0000%) ⭕ |
design__core__area | 52235.1000 | 52235.1000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 60033 | 60033 | 0 (0.0000%) ⭕ |
design__instance__area | 24902.6000 | 24902.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 22 | 22 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0032 | 0.0032 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0039 | 0.0039 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0071 | 0.0071 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2651 | -0.2651 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2654 | 0.2654 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2782 | -0.2782 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2803 | 0.2803 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 22 | 22 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2694 | -0.2694 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2703 | 0.2703 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2617 | -0.2617 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2623 | 0.2623 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2721 | -0.2721 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2741 | 0.2741 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 6 | 6 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2652 | -0.2652 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2662 | 0.2662 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2629 | -0.2629 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2635 | 0.2635 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2746 | -0.2746 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2766 | 0.2766 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 16 | 16 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2668 | -0.2668 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2679 | 0.2679 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 17 | 17 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/zipdiv
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.2594 | -0.2594 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.2599 | 0.2599 | 0.0000 (0.0000%) ⭕ |
design__core__area | 29796.1000 | 29796.1000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 36193 | 36193 | 0 (0.0000%) ⭕ |
design__instance__area | 13257.7000 | 13257.7000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0007 | 0.0007 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0011 | 0.0011 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2628 | -0.2628 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2640 | 0.2640 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2707 | -0.2707 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2718 | 0.2718 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2661 | -0.2661 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2672 | 0.2672 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2594 | -0.2594 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2599 | 0.2599 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2658 | -0.2658 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2662 | 0.2662 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2620 | -0.2620 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2624 | 0.2624 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2608 | -0.2608 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2614 | 0.2614 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2680 | -0.2680 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2685 | 0.2685 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2636 | -0.2636 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2642 | 0.2642 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |