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Milk-V Duo S (SG2000) firmware
oreboot 🦀 bt0 on Arm
1091555380
boot_log_len: 2359
>>> BEGIN OF BOOT LOG
B. I:V/3360889e/7vcz:g2a3d7b10/0/40000000.
SCS/0/0. I:ep_swinfo.
I:sw_info=0x0
I:EP:0x3050134/0x0.
I:EP:0x305013c/0x0.
I:EP:0x3050144/0x0.
I:EP:0x305014c/0x0.
I:EP:0x3050154/0x0.
I:EP:0x305015c/0x0.
I:EP:0x3050164/0x0.
I:EP:0x305016c/0x0.
I:EP:0x3050174/0x0.
I:EP:0x305017c/0x0.
I:EP:0x3050184/0x0.
I:ep_dev.
I:EP:0x3050134/0x0.
I:EP:0x305013c/0x0.
I:EP:0x3050144/0x0.
I:EP:0x305014c/0x0.
I:EP:0x3050154/0x0.
I:EP:0x305015c/0x0.
I:EP:0x3050164/0x0.
I:EP:0x305016c/0x0.
I:EP:0x3050174/0x0.
I:EP:0x305017c/0x0.
I:EP:0x3050184/0x0.
WD.URPL. I:cv_usb_hw_init done
I:cv_usb_clk_init done
USBI. I:ep_dev.
I:EP:0x3050134/0x0.
I:EP:0x305013c/0x0.
I:EP:0x3050144/0x0.
I:EP:0x305014c/0x0.
I:EP:0x3050154/0x0.
I:EP:0x305015c/0x0.
I:EP:0x3050164/0x0.
I:EP:0x305016c/0x0.
I:EP:0x3050174/0x0.
I:EP:0x305017c/0x0.
I:EP:0x3050184/0x0.
I:USBVID/0.
I:timeout_in_ms 1000
I:USB polling timeout_in_ms: 1000
I:bulkBufAlloc: 0xc03a000
I:cmdBufAlloc: 0xc03a200
I:cb0_buf: 0xc03a400
I:cb1_buf: 0xc03a480
I:cb2_buf: 0xc03a500
I:ep0BuffAlloc: 0xc03a580
I:rsp_buf: 0xc03a5c0
I:acm_buf: 0xc03a5e0
I:setup_buf: 0xc03a660
I:handler: 0xc03a680
I:usb bind
I:connection speed: 3
USBK. I:flagEnterDL 1
USBD. I:BS/cea3.
BS/USB.PS. I:LIS/0xcea3/0x40139000/0x0/4096/0.
I:USBVID/0.
I:timeout_in_ms 1000
I:USB polling timeout_in_ms: 1000
I:bulkBufAlloc: 0xc03a000
I:cmdBufAlloc: 0xc03a200
I:cb0_buf: 0xc03a400
I:cb1_buf: 0xc03a480
I:cb2_buf: 0xc03a500
I:ep0BuffAlloc: 0xc03a580
I:rsp_buf: 0xc03a5c0
I:acm_buf: 0xc03a5e0
I:setup_buf: 0xc03a660
I:handler: 0xc03a680
I:usb bind
USBB. I:connection speed: 3
I:CVI_USB_BREAK
USBL. I:Application: disconnect
I:usb unbind
I:LIE/0/0x40139000/0x0/4096.
I:C/0/0xe00000c/0xa0000001.
I:C/1/0xe00000c/0xa0000002.
PE. I:CS/0x5200200/0x0/0x1700030b.
I:No BLCP.
BS. I:LIS/0xcea3/0x40100000/0x1000/10248/0.
I:USBVID/0.
I:timeout_in_ms 1000
I:USB polling timeout_in_ms: 1000
I:bulkBufAlloc: 0xc03a000
I:cmdBufAlloc: 0xc03a200
I:cb0_buf: 0xc03a400
I:cb1_buf: 0xc03a480
I:cb2_buf: 0xc03a500
I:ep0BuffAlloc: 0xc03a580
I:rsp_buf: 0xc03a5c0
I:acm_buf: 0xc03a5e0
I:setup_buf: 0xc03a660
I:handler: 0xc03a680
I:usb bind
I:connection speed: 3
USBK. I:flagEnterDL 1
I:CVI_USB_BREAK
USBL. I:Application: disconnect
I:usb unbind
I:LIE/0/0x40100000/0x1000/10248.
BE. I:bl2_entry=0x40100020
J.
<<< END OF BOOT LOG
Architecture: 15
Implementer: Arm
Part number: 3331
Revision: 4
Variant: 0
[bt0] panic in 'src/mainboard/milk-v/duo-s/bt0a/src/main.rs' line 206
[bt0] DO NOT PANIC! EVERYTHING IS OKAY!
boot_log_len: 2353
>>> BEGIN OF BOOT LOG
C. I:V/6da499f8/7vcz:g2a3d7b10/0/4418000.
SCS/0/0. I:ep_swinfo.
I:sw_info=0x0
I:EP:0x3050134/0x0.
I:EP:0x305013c/0x0.
I:EP:0x3050144/0x0.
I:EP:0x305014c/0x0.
I:EP:0x3050154/0x0.
I:EP:0x305015c/0x0.
I:EP:0x3050164/0x0.
I:EP:0x305016c/0x0.
I:EP:0x3050174/0x0.
I:EP:0x305017c/0x0.
I:EP:0x3050184/0x0.
I:ep_dev.
I:EP:0x3050134/0x0.
I:EP:0x305013c/0x0.
I:EP:0x3050144/0x0.
I:EP:0x305014c/0x0.
I:EP:0x3050154/0x0.
I:EP:0x305015c/0x0.
I:EP:0x3050164/0x0.
I:EP:0x305016c/0x0.
I:EP:0x3050174/0x0.
I:EP:0x305017c/0x0.
I:EP:0x3050184/0x0.
WD.URPL. I:cv_usb_hw_init done
I:cv_usb_clk_init done
USBI. I:ep_dev.
I:EP:0x3050134/0x0.
I:EP:0x305013c/0x0.
I:EP:0x3050144/0x0.
I:EP:0x305014c/0x0.
I:EP:0x3050154/0x0.
I:EP:0x305015c/0x0.
I:EP:0x3050164/0x0.
I:EP:0x305016c/0x0.
I:EP:0x3050174/0x0.
I:EP:0x305017c/0x0.
I:EP:0x3050184/0x0.
I:USBVID/0.
I:timeout_in_ms 1000
I:USB polling timeout_in_ms: 1000
I:bulkBufAlloc: 0xc03a000
I:cmdBufAlloc: 0xc03a200
I:cb0_buf: 0xc03a400
I:cb1_buf: 0xc03a480
I:cb2_buf: 0xc03a500
I:ep0BuffAlloc: 0xc03a580
I:rsp_buf: 0xc03a5c0
I:acm_buf: 0xc03a5e0
I:setup_buf: 0xc03a660
I:handler: 0xc03a680
I:usb bind
I:connection speed: 3
USBK. I:flagEnterDL 1
USBD. I:BS/cea3.
BS/USB.PS. I:LIS/0xcea3/0xc039000/0x0/4096/0.
I:USBVID/0.
I:timeout_in_ms 1000
I:USB polling timeout_in_ms: 1000
I:bulkBufAlloc: 0xc03a000
I:cmdBufAlloc: 0xc03a200
I:cb0_buf: 0xc03a400
I:cb1_buf: 0xc03a480
I:cb2_buf: 0xc03a500
I:ep0BuffAlloc: 0xc03a580
I:rsp_buf: 0xc03a5c0
I:acm_buf: 0xc03a5e0
I:setup_buf: 0xc03a660
I:handler: 0xc03a680
I:usb bind
USBB. I:connection speed: 3
I:CVI_USB_BREAK
USBL. I:Application: disconnect
I:usb unbind
I:LIE/0/0xc039000/0x0/4096.
I:C/0/0xe00000c/0xa0000001.
I:C/1/0xe00000c/0xa0000002.
PE. I:CS/0x5200200/0x0/0x170003ab.
I:No BLCP.
BS. I:LIS/0xcea3/0xc000000/0x1000/30224/0.
I:USBVID/0.
I:timeout_in_ms 1000
I:USB polling timeout_in_ms: 1000
I:bulkBufAlloc: 0xc03a000
I:cmdBufAlloc: 0xc03a200
I:cb0_buf: 0xc03a400
I:cb1_buf: 0xc03a480
I:cb2_buf: 0xc03a500
I:ep0BuffAlloc: 0xc03a580
I:rsp_buf: 0xc03a5c0
I:acm_buf: 0xc03a5e0
I:setup_buf: 0xc03a660
I:handler: 0xc03a680
I:usb bind
I:connection speed: 3
USBK. I:flagEnterDL 1
I:CVI_USB_BREAK
USBL. I:Application: disconnect
I:usb unbind
I:LIE/0/0xc000000/0x1000/30224.
BE. I:bl2_entry=0xc000020
J.
<<< END OF BOOT LOG
C.SCS/0/0.WD.URPL.USBI.USBK.USBD.BS/USB.PS.USBB.USBL.PE.BS.USBK.USBL.BE.J.B
oreboot 🦀 bt0
RISC-V arch 00000000
RISC-V core vendor: T-Head (0x05b7)
RISC-V implementation: unknown (0x00000000)
RISC-V hart ID 0
boot src: USB
retries: 1
ATF state: b100fe00
CP_STATE: 00000000
CONF: 170003ab
TYPE: SG20000 / 512MB DDR3 RAM @1866 (1)
SW INFO: 00000000
EFUSE_STATUS: 00000020
FTSN0: 00000000
efuse: FTSN0 is NOT locked
FTSN1: 00000000
efuse: FTSN1 is NOT locked
EFUSE_LEAKAGE: 5020002d
efuse: FTSN2 is locked
FTSN3: d1c21ea5
efuse: FTSN3 is locked
FTSN4: 1526b59a
efuse: FTSN4 is locked
dram_vendor 1, dram_capacity 4
boot from USB
boot flag 4d474e31
boot flag 4d474e31
st_on_reason 080f0003
st_off_reason 00000000
Data rate = 1866
tar_freq 116
reg_set 00011001111011100101100001000110 (435050566)
reg_span 00000000000000000000000100100010 (290)
reg_step 00000000000000000001111000001100 (7692)
cvx16_pll_init
SSC_EN = 0
DPLL_SSC_SYN_CTRL 00000000000000000000000000000000
DPLL_SSC_SYN_CTRL 00000000000000000000000000100001
SSC_OFF
Wait for DDR PLL LOCK=1...
Finished DDR PLL LOCK=1.
PLL init done.
DDRC init
DDRC 0x000c 03780301
DDRC 0x000c 63746371
Release DDR controller from reset
/ cvx16_setting_check
phy_reg_version 20210920
dfi_t_ctrl_delay 4
dfi_t_rddata_en 10
dfi_tphy_wrlat 5
dfi_tphy_wrdata 3
dfi_t_wrdata_delay 7
\ cvx16_setting_check finish
/ cvx16_pinmux start
\ cvx16_pinmux finish
/ ddr_patch_set start
\ ddr_patch_set finish
/ cvx16_en_rec_vol_mode start
\ cvx16_en_rec_vol_mode finish
/ cvx16_set_dfi_init start
\ set_dfi_init_start finish
/ ddr_phy_power_on_seq1 start
RESET PD !!!
All PHYA CA PD=0 ...
TOP_REG_TX_SEL_GPIO = 1
TX_BYTE PD=0 ...
TOP_REG_TX_SEL_GPIO = 0
\ ddr_phy_power_on_seq1 finish
/ first dfi_init_start
\ cvx16_polling_dfi_init_start finish
/ cvx16_int_isr_08 start
en_pll_speed_chg false
curr_pll_speed 32
next_pll_speed 512
\ cvx16_int_isr_08 finish
/ cvx16_ddr_phy_power_on_seq2 start
DLL calibration if necessary ...
en_pll_speed_chg false
curr_pll_speed 32
next_pll_speed 512
DLL lock !
Do DLL UPD
DLL CAL Finish
DLL calibration done
ZQCAL if necessary ...
cv181x without ZQ Calibration ...
ZQ240 calibration if necessary ...
cv181x without ZQ240 Calibration ...
ZQ calculate variation not run
All PHYA CA PD = 0 ...
TX_BYTE PD = 0 ...
\ cvx16_ddr_phy_power_on_seq2 finish
/ cvx16_set_dfi_init_complete start
set init_complete = 1 ...
\ cvx16_set_dfi_init_complete finish
/ change_pll_freq start
Change PLL frequency if necessary ...
RSTZ_DIV = 0
en_pll_speed_chg false
curr_pll_speed 32
next_pll_speed 512
RSTZ_DIV = 1
TOP_REG_RESETZ_DQS
Wait for DDR PLL_SLV_LOCK = 1...
\ change_pll_freq finish
/ ddr_phy_power_on_seq3 start
--> ca_oenz ca_clk_oenz !!!
--> en clock gated for power save !!!
\ ddr_phy_power_on_seq3 finish
/ wait_for_dfi_init_complete start
\ wait_for_dfi_init_complete finish
/ polling_synp_normal_mode start
operating_mode 1
\ polling_synp_normal_mode finish
bist_wr_prbs_init
bist_wr_prbs_init done
>> BIST start
- BIST success
ctrl_low_patch finish
clk_gating_disable
bist_wrlvl_init
bist_wrlvl_init done
rtt_nom for wrlvl setting
wr_odt_en = 0 ...
Poll MRSTAT.mr_wr_busy until it is 0
non-lp4 Poll MRSTAT.mr_wr_busy finish
non-lp4 Write the MRCTRL0
non-lp4 Write the MRCTRL1
non-lp4 Write MRCTRL0.mr_wr to 1
Poll MRSTAT.mr_wr_busy until it is 0
non-lp4 Poll MRSTAT.mr_wr_busy finish
non-lp4 Write the MRCTRL0
non-lp4 Write the MRCTRL1
non-lp4 Write MRCTRL0.mr_wr to 1
DDR3 MRS rtt_nom ...
wait retraining finish ...
Poll MRSTAT.mr_wr_busy until it is 0
non-lp4 Poll MRSTAT.mr_wr_busy finish
non-lp4 Write the MRCTRL0
non-lp4 Write the MRCTRL1
non-lp4 Write MRCTRL0.mr_wr to 1
Poll MRSTAT.mr_wr_busy until it is 0
non-lp4 Poll MRSTAT.mr_wr_busy finish
non-lp4 Write the MRCTRL0
non-lp4 Write the MRCTRL1
non-lp4 Write MRCTRL0.mr_wr to 1
clk_gating_enable
cvx16_wrlvl_req finish
bist_wr_prbs_init
bist_wr_prbs_init done
>> BIST start
- BIST success
clk_gating_disable
bist_rdglvl_init
bist_rdglvl_init done
wait retraining finish ...
clk_gating_enable
cvx16_rdglvl_req finish
bist_wr_prbs_init
bist_wr_prbs_init done
>> BIST start
- BIST success
wdqlvl_M1_ALL_DQ_DM
clk_gating_disable
cvx16_dfi_ca_park_prbs start
dfi_ca_park_prbs enable = true
cvx16_dfi_ca_park_prbs done
bist_wdqlvl_init
sram_sp = 00000102
bist_wdqlvl_init done
phyd_dfi_wdqlvl 00090400
phyd_dfi_wdqlvl 00090411
wait retraining finish ...
dfi_ca_park_prbs enable = false
clk_gating_enable
cvx16_wdqlvl_req dq/dm finish
clk_gating_disable
cvx16_dfi_ca_park_prbs start
dfi_ca_park_prbs enable = true
cvx16_dfi_ca_park_prbs done
bist_wdqlvl_init
sram_sp = 00000102
bist_wdqlvl_init done
phyd_dfi_wdqlvl 00090410
phyd_dfi_wdqlvl 00090411
wait retraining finish ...
dfi_ca_park_prbs enable = false
clk_gating_enable
cvx16_wdqlvl_req dq finish
clk_gating_disable
cvx16_dfi_ca_park_prbs start
dfi_ca_park_prbs enable = true
cvx16_dfi_ca_park_prbs done
bist_wdmlvl_init
sram_sp = 00000102
bist_wdmlvl_init done
phyd_dfi_wdqlvl 00090410
phyd_dfi_wdqlvl 00090011
wait retraining finish ...
dfi_ca_park_prbs enable = false
clk_gating_enable
cvx16_wdqlvl_req dm finish
bist_wr_prbs_init
bist_wr_prbs_init done
>> BIST start
- BIST success
BIST poll: 00000004
cap_in_mbyte = 5
BIST poll: 00000004
BIST poll: 0000000c
dram_cap_in_mbyte: 5
DRAM cap shift vals: x16 1, dev 2
DRAM cap in MB per dev: 5
WARNING: unsupported DRAM cap in MB per dev
ctrl_init_update_by_dram_size finish
dram_cap_in_mbyte: 5
cvx16_dram_cap_check finish
clk_gating_enable
cvx16_clk_gating_enable finish
bist_wr_prbs_init
bist_wr_prbs_init done
>> BIST start
- BIST success
DDR BIST PASS
DRAM init done
time: 12271025
RTOS base: 0x0c85e985
>> load main stage over USB
USBK.USBL.load image: 0
>> load SBI test over USB
USBK.USBL.load image: 0
[bt0] Jump to main stage @80000000
oreboot 🦀 main
RISC-V arch 00000000
RISC-V core vendor: T-Head (0x05b7)
RISC-V implementation: unknown (0x00000000)
RISC-V hart ID 0
test 04100513
[SBI] PLIC init
[SBI] ipi init
[SBI] rfence init
[SBI] timer init
[SBI] reset init
==== platform CSRs ====
MXSTATUS c0638000
MHCR 00000108
MCOR 00000003
MHINT 00004000
see C906 manual p581 ff
=======================
Set up extension CSRs
==== platform CSRs ====
MXSTATUS c0638000
MHCR 0000017f
MCOR 00000003
MHINT 0000610c
see C906 manual p581 ff
=======================
MCPUID 0: 0910010d
MCPUID 1: 12046000
MCPUID 2: 260c0001
MCPUID 3: 30030054
MCPUID 4: 42180000
MCPUID 5: 50000000
MCPUID 6: 60000753
[SBI] set mtvec: 80000044
[SBI] delegate interrupts and exceptions
RustSBI version 0.3.2
.______ __ __ _______.___________. _______..______ __
| _ \ | | | | / | | / || _ \ | |
| |_) | | | | | | (----`---| |----`| (----`| |_) || |
| / | | | | \ \ | | \ \ | _ < | |
| |\ \----.| `--' |.----) | | | .----) | | |_) || |
| _| `._____| \______/ |_______/ |__| |_______/ |______/ |__|
Platform Name: Milk-V Duo S
Implementation: oreboot version 0.1.0
[SBI] misa: RV64ACDFIMSUX
[SBI] mideleg: ssoft stimer sext (0x000222)
[SBI] medeleg: ima ia lma la sma sa uecall ipage lpage spage (0x00b1f3)
[SBI] mie: (0x000000)
[SBI] PMP0: 0x00000000 - 0x00000000 (A,R,W,X)
[SBI] PMP1: 0x00000000 - 0x40000000 (A,R,W,X)
[SBI] PMP2: 0x40000000 - 0x40200000 (A,R,W,X)
[SBI] PMP3: 0x40200000 - 0xfffffff000 (A,R,W,X)
[SBI] PMP8: 0x00000000 - 0x00000000 (A,R,W,X)
[main] .......
[SBI] Enter supervisor on hart 0 at 80200000 with DTB from 80202000
[SBI] Enter loop...
A TEST
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