msp430f1611 i2c master receiver test

main.c

#include "msp430f1611.h"
#include "ossitypes.h"
/*
 * main.c
 */
uint8_t RXData = 0;
uint8_t TestData[64] = {0};
volatile uint8_t cnt;
int main (void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

  P3SEL |= 0x0A;                            // Select I2C pins
  P6DIR |= 0x01;                            // P6.0 output
  P6OUT |= 0x01;                           // Clear P6.0
  U0CTL |= I2C + SYNC;                      // Recommended init procedure
  U0CTL &= ~I2CEN;                          // Recommended init procedure
  I2CTCTL |= I2CSSEL1;                      // SMCLK

  I2CSCLH = 0x03;                           // High period of SCL
  I2CSCLL = 0x03;                           // Low period of SCL
  I2CNDAT = 64;                           // Read one byte
  I2CSA = 0x0049;                           // Slave Address is 048h
  I2CIE = RXRDYIE + NACKIE;                  // Enable RXRDYIFG interrupt
  U0CTL |= I2CEN;                           // Enable I2C
  _EINT();                                  // Enable interrupts

  cnt = 0;
  volatile uint8_t i;

  for (i = 0; i<64;i++)
  {
	  TestData[i] = 63-i;
  }

  __delay_cycles(2000);
  while (1)
  {
	while(I2CTCTL&I2CSTP);
    U0CTL |= MST;                           // Master mode
    I2CTCTL |= I2CSTT + I2CSTP;             // Initiate transfer
    _BIS_SR(CPUOFF);                        // Enter LPM0
                            // Set P6.0
    //if (TestData++ != RXData) break;        // Test received data
    //P6OUT &= ~0x01;                         // Clear P6.0
  }

 // while (1);                                // Trap CPU

}

// Common ISR for I2C Module
#pragma vector=USART0TX_VECTOR
__interrupt void I2C_ISR(void)
{
 switch(I2CIV)
 {
   case  0: break;                          // No interrupt
   case  2: break;                          // Arbitration lost
   case  4:                           // No Acknowledge
   	 P6OUT |= 0x01;
   	   cnt = 0;
   //	_BIC_SR_IRQ(CPUOFF);
   	   break;
   case  6: break;                          // Own Address
   case  8: break;                          // Register Access Ready
   case 10:                                 // Receive Ready
     RXData = I2CDRB;                       // RX data
     if( RXData != TestData[cnt])
     {
    	 P6OUT ^= 0x01;
     }
     cnt++;
     if( cnt > 63)
     {
    	 cnt = 0;
    	 _BIC_SR_IRQ(CPUOFF);                   // Clear LPM0
     }
     break;
   case 12: break;                          // Transmit Ready
   case 14: break;                          // General Call
   case 16: break;                          // Start Condition
 }
}

ossitypes.h

/*
 * ossitypes.h
 *
 *  Created on: 2012. 12. 22.
 *      Author: OSSI
 */

#ifndef OSSITYPES_H_
#define OSSITYPES_H_

typedef unsigned char       uint8_t;
typedef signed char         int8_t;
typedef unsigned short int  uint16_t;
typedef signed short int    int16_t;
typedef unsigned long int   uint32_t;
typedef signed long int     int32_t;


#endif /* OSSITYPES_H_ */