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MSP430F1611 simple DAC12 module is added. Work with ADC12 module. see the code for the explanation
/*
* adc12.c
*
* Created on: 2013. 1. 16.
* Author: OSSI
*/
#include "adc12.h"
void adc12_portSetup(uint8_t ports)
{
ASSERT(ports <= 0xFF);
P6SEL |= ports;
}
void adc12_init(uint8_t clockSourceSelect, uint16_t clockSourceDivider, uint16_t clockCycleHoldCount)
{
// Make sure ENC is cleared
ADC12CTL0 &= ~ENC;
// Turn off ADC and Clear interrupts and etc
ADC12CTL0 &= ~(ADC12ON + ADC12OVIE + ADC12TOVIE + ENC + ADC12SC);
// reset registers
ADC12IFG &= 0x0000;
ADC12IE &= 0x0000;
// we only use ADC12MEM0
ADC12MCTL0 &= 0x0000;
// set clockSourceSelect / clockSourceDivider / ADC12_SAMPLEHOLDSOURCE_SC
// and set SHP
ADC12CTL1 = clockSourceSelect + clockSourceDivider + ADC12_SAMPLEHOLDSOURCE_SC + SHP;
// we only use ADC12MEM0,
// so we set hold count for lower conversion memory
ADC12CTL0 = 0x0F00 & clockCycleHoldCount ;
}
void adc12_setVolReference(uint8_t refVoltageSourceSelect)
{
// Clear ENC to set registers
ADC12CTL0 &= ~ENC;
if (refVoltageSourceSelect == ADC12_REF_VCC_VSS)
{
// default reference setting
// reset internal reference setting
ADC12CTL0 &= ~(REFON+REF2_5V);
// reset reference voltage setting for ADC12MEM0
ADC12MCTL0 &= 0x8F;
ADC12MCTL0 |= ADC12_REF_VCC_VSS;
}
else if(refVoltageSourceSelect == ADC12_REF_VREF_VSS)
{
// internal reference setting
// we only use 2.5V internal reference
ADC12CTL0 |= (REFON+REF2_5V);
// reset reference voltage setting for ADC12MEM0
ADC12MCTL0 &= 0x8F;
ADC12MCTL0 |= ADC12_REF_VREF_VSS;
// make sure you wait for reference to stabilize about 17~20ms
// TODO: change cycles based on system clock
volatile uint8_t i;
for(i = 0; i < 17; i++)
{
__delay_cycles(7372);
}
}
else if(refVoltageSourceSelect == ADC12_REF_V_EREF_VSS)
{
// external reference setting
// reset internal reference setting
ADC12CTL0 &= ~(REFON+REF2_5V);
// reset reference voltage setting for ADC12MEM0
ADC12MCTL0 &= 0x8F;
ADC12MCTL0 |= ADC12_REF_V_EREF_VSS;
}
}
void adc12_offInternalVolReference(void)
{
// Clear ENC to set registers
ADC12CTL0 &= ~ENC;
ADC12CTL0 &= ~(REFON+REF2_5V);
}
uint16_t adc12_readChannel(uint8_t channelSelect)
{
volatile uint16_t adcValue = 0;
// Clear ENC to set registers
ADC12CTL0 &= ~ENC;
// reset previous channel setting
ADC12MCTL0 &= 0xF0;
// set channel
ADC12MCTL0 |= (channelSelect & 0x0F);
ADC12CTL0 |= ADC12ON;
// clear IFG before starting convertion
ADC12IFG &= ~BIT0;
ADC12CTL0 |= ENC;
ADC12CTL0 |= ADC12SC;
// wait conversion to be finished
while ((ADC12IFG & BIT0)==0);
// read value
adcValue = ADC12MEM0;
// wait adc12 not busy to turn off
while(ADC12CTL1&ADC12BUSY);
ADC12CTL0 &= ~ENC;
ADC12IFG &= ~BIT0;
return adcValue;
}
/*
* adc12.h
*
* Created on: 2013. 1. 16.
* Author: OSSI
*/
#ifndef ADC12_H_
#define ADC12_H_
#include "ossiobc.h"
#define ADC12_PIN_6_0 (BIT0)
#define ADC12_PIN_6_1 (BIT1)
#define ADC12_PIN_6_2 (BIT2)
#define ADC12_PIN_6_3 (BIT3)
#define ADC12_PIN_6_4 (BIT4)
#define ADC12_PIN_6_5 (BIT5)
#define ADC12_PIN_6_6 (BIT6)
#define ADC12_PIN_6_7 (BIT7)
#define ADC12_INPUT_A0 (INCH_0)
#define ADC12_INPUT_A1 (INCH_1)
#define ADC12_INPUT_A2 (INCH_2)
#define ADC12_INPUT_A3 (INCH_3)
#define ADC12_INPUT_A4 (INCH_4)
#define ADC12_INPUT_A5 (INCH_5)
#define ADC12_INPUT_A6 (INCH_6)
#define ADC12_INPUT_A7 (INCH_7)
#define ADC12_INPUT_V_EREF_POS (INCH_8) //TODO: what is this?
#define ADC12_INPUT_VREF_NEG (INCH_9) //TODO: what is this?
#define ADC12_INPUT_TEMPSENSOR (INCH_10)
#define ADC12_INPUT_VMID (INCH_11)
#define ADC12_SAMPLEHOLDSOURCE_SC (SHS_0)
//#define ADC12_SAMPLEHOLDSOURCE_1 (SHS_1)
//#define ADC12_SAMPLEHOLDSOURCE_2 (SHS_2)
//#define ADC12_SAMPLEHOLDSOURCE_3 (SHS_3)
#define ADC12_CLOCKSOURCE_ADC12OSC (ADC12SSEL_0)
#define ADC12_CLOCKSOURCE_ACLK (ADC12SSEL_1)
#define ADC12_CLOCKSOURCE_MCLK (ADC12SSEL_2)
#define ADC12_CLOCKSOURCE_SMCLK (ADC12SSEL_3)
#define ADC12_CLOCKDIVIDER_1 (ADC12DIV_0)
#define ADC12_CLOCKDIVIDER_2 (ADC12DIV_1)
#define ADC12_CLOCKDIVIDER_3 (ADC12DIV_2)
#define ADC12_CLOCKDIVIDER_4 (ADC12DIV_3)
#define ADC12_CLOCKDIVIDER_5 (ADC12DIV_4)
#define ADC12_CLOCKDIVIDER_6 (ADC12DIV_5)
#define ADC12_CLOCKDIVIDER_7 (ADC12DIV_6)
#define ADC12_CLOCKDIVIDER_8 (ADC12DIV_7)
#define ADC12_CYCLEHOLD_4_CYCLES (SHT0_0)
#define ADC12_CYCLEHOLD_8_CYCLES (SHT0_1)
#define ADC12_CYCLEHOLD_16_CYCLES (SHT0_2)
#define ADC12_CYCLEHOLD_32_CYCLES (SHT0_3)
#define ADC12_CYCLEHOLD_64_CYCLES (SHT0_4)
#define ADC12_CYCLEHOLD_96_CYCLES (SHT0_5)
#define ADC12_CYCLEHOLD_128_CYCLES (SHT0_6)
#define ADC12_CYCLEHOLD_192_CYCLES (SHT0_7)
#define ADC12_CYCLEHOLD_256_CYCLES (SHT0_8)
#define ADC12_CYCLEHOLD_384_CYCLES (SHT0_9)
#define ADC12_CYCLEHOLD_512_CYCLES (SHT0_10)
#define ADC12_CYCLEHOLD_768_CYCLES (SHT0_11)
#define ADC12_CYCLEHOLD_1024_CYCLES (SHT0_12)
#define ADC12_REF_VCC_VSS (SREF_0)
#define ADC12_REF_VREF_VSS (SREF_1)
#define ADC12_REF_V_EREF_VSS (SREF_2)
#define ADC12_SINGLECHANNEL (CONSEQ_0)
void adc12_portSetup(uint8_t ports);
// call adc12_init() one time in the beginning
void adc12_init(uint8_t clockSourceSelect, uint16_t clockSourceDivider, uint16_t clockCycleHoldCount);
void adc12_setVolReference(uint8_t refVoltageSourceSelect);
// adc12_end() turns off internal reference
// as the reference is not automatically power down
// and turns off adc12 module to save power
void adc12_offInternalVolReference(void);
// returns the value
// single channel single conversion mode
uint16_t adc12_readChannel(uint8_t channelSelect);
#endif /* ADC12_H_ */
/*
* clock.c
*
* Created on: 2013. 1. 14.
* Author: OSSI
*/
#include"clock.h"
// main clock will be shared via system
static volatile uint8_t clockMode;
uint8_t clock_getMode(void)
{
return clockMode;
}
uint8_t clock_setDefaultDCO(void)
{
// Chage DCO_DELTA to change default DCO frequency
// default DCO_DELTA = 255 and fDCO ~ 1MHz
uint16_t Compare, Oldcapture = 0;
_DINT();
BCSCTL1 |= DIVA_3; // ACLK= LFXT1CLK/8
CCTL2 = CM_1 + CCIS_1 + CAP; // CAP, ACLK
TACTL = TASSEL_2 + MC_2 + TACLR; // SMCLK, cont-mode, clear
while (1)
{
while (!(CCIFG & CCTL2)); // Wait until capture occured
CCTL2 &= ~CCIFG; // Capture occured, clear flag
Compare = CCR2; // Get current captured SMCLK
Compare = Compare - Oldcapture; // SMCLK difference
Oldcapture = CCR2; // Save current captured SMCLK
if (DCO_DELTA == Compare) break; // If equal, leave "while(1)"
else if (DCO_DELTA < Compare) // DCO is too fast, slow it down
{
DCOCTL--;
if (DCOCTL == 0xFF)
{
if (!(BCSCTL1 == (XT2OFF + DIVA_3)))
BCSCTL1--; // Did DCO roll under?, Sel lower RSEL
}
}
else
{
DCOCTL++;
if (DCOCTL == 0x00)
{
if (!(BCSCTL1 == (XT2OFF + DIVA_3 + 0x07)))
BCSCTL1++; // Did DCO roll over? Sel higher RSEL
}
}
}
CCTL2 = 0; // Stop CCR2
TACTL = 0;
BCSCTL1 &= ~DIVA_3; // Back to ACLK= LFXT1CLK
_EINT();
return 1;
}
uint8_t clock_setup(void)
{
// We want to use LFXT1CLK for 32.768kHz / XT2CLK for 8MHz or 7.3728MHz
// after POR, default DCO frequency is 800kHz
// default mode
// CLOCK_XT2_LFXT1 mode
// LFXT1CLK source select first and 32.768kHz crystal needs long startup time
BCSCTL1 &= ~XTS; // default value is 0 but to make sure
// To change MCLK source from DCO to XT2CLK, we need to do following procedure
// Switch on the XT2
BCSCTL1 &= ~XT2OFF;
// when do while is executed, MCLK = default DCO = 800kHz
// timeout *250 delay cycles / 800kHz + other instruction cycles /800kHz = timeout time
// timeout = 1450 -> timeout time ~500 ms
volatile uint16_t timeout = 1450;
// Check oscillator fault with timeout
do
{
IFG1 &= ~OFIFG; // Clear OSCFault flag
// need to have some delay in between checks
__delay_cycles(250);
}
while ((IFG1 & OFIFG)&& --timeout); // OSCFault flag still set?
// Add timeout to prevent hang in case osc fails.
// Switch to DCO when XT2 failed
// if failed change to CLOCK_DCO_LFXT1
// Let system know that clock is switched
// check temperature effect on clocks if possible
if(timeout)
{
// when there's no fault, proceed to select source
// MCLK = SMCLK = XT2 (safe)
BCSCTL2 |= SELM_2 + SELS;
clockMode = CLOCK_XT2_LFXT1;
return CLOCK_XT2_LFXT1;
}
else
{
// CLOCK_DCO_LFXT1 mode DCOCLK = ~1MHz ACLK = 32.768kHz
// Set DCO frequency in case XT2 fails
BCSCTL1 &= ~XTS; // default value is 0 but to make sure
BCSCTL1 |= XT2OFF; // XT2 OFF
BCSCTL2 = 0x00; // reset BCSCTL2
clock_setDefaultDCO();
clockMode = CLOCK_DCO_LFXT1;
return CLOCK_DCO_LFXT1;
}
}
void clock_dividerSetup(uint8_t MCLKDividerSelect, uint8_t SMCLKDividerSelect, uint8_t ACLKDividerSelect)
{
// reset divider first
// reset ACLK divider
BCSCTL1 &= 0xCF; // Clear BIT5 and BIT4
// select ACLK Divider
BCSCTL1 |= ACLKDividerSelect;
// reset MCLK, SMCLK divider
BCSCTL2 &= 0xC9; // Clear BIT5,BIT4, BIT2, BIT1
// select MCLK Divider
BCSCTL2 |= MCLKDividerSelect;
// select SMCLK Divider
BCSCTL2 |= SMCLKDividerSelect;
}
/*
* clock.h
*
* Created on: 2013. 1. 14.
* Author: OSSI
*/
/* Clock setting for OSSI MSP430F1611
*
* default: CLOCK_XT2_LFXT1
* XT2 ON: 7.3728 MHz or 8 MHz
* LFXT1 Low Power Mode: 32.768 kHz
* MCLK = XT2CLK / SMCLK = XT2CLK / ACLK = LFXT1
*
* alternative 1: CLOCK_DCO_LFXT1
* XT2 OFF: DCO set to ~ 1MHz
* LFXT1 Low Power Mode: 32.768 kHz
* MCLK = DCOCLK / SMCLK = DCOCLK / ACLK = LFXT1
*
*
* alternative 2: CLOCK_DCO_DCO
* DCO set to ~ 1MHz
* MCLK = DCOCLK / SMCLK = DCOCLK / ACLK = DCOCLK / 30
*
*/
#ifndef CLOCK_H_
#define CLOCK_H_
#include "msp430f1611.h"
#include "ossitypes.h"
#include "debug.h"
#define CLOCK_XT2_LFXT1 (0)
#define CLOCK_DCO_LFXT1 (1)
#define CLOCK_DCO_DCO (2)
#define CLOCK_XT2_FREQ_8MHz (0)
#define CLOCK_XT2_FREQ_7_3728MHz (1)
#define CLOCK_DCO_FREQ_1MHz (2)
//#define DELTA 900 // target DCO = DELTA*(4096) = 3686400
//#define DELTA 70 // target DCO = DELTA*(4096) = 286720
#define DCO_DELTA (245) // target DCO = DELTA*(4096) = 1003275
#define MCLK_DIVIDED_BY_1 DIVM_0 /* MCLK Divider 0: /1 */
#define MCLK_DIVIDED_BY_2 DIVM_1 /* MCLK Divider 1: /2 */
#define MCLK_DIVIDED_BY_4 DIVM_2 /* MCLK Divider 2: /4 */
#define MCLK_DIVIDED_BY_8 DIVM_3 /* MCLK Divider 3: /8 */
#define SMCLK_DIVIDED_BY_1 DIVS_0 /* SMCLK Divider 0: /1 */
#define SMCLK_DIVIDED_BY_2 DIVS_1 /* SMCLK Divider 1: /2 */
#define SMCLK_DIVIDED_BY_4 DIVS_2 /* SMCLK Divider 2: /4 */
#define SMCLK_DIVIDED_BY_8 DIVS_3 /* SMCLK Divider 3: /8 */
#define ACLK_DIVIDED_BY_1 DIVA_0 /* ACLK Divider 0: /1 */
#define ACLK_DIVIDED_BY_2 DIVA_1 /* ACLK Divider 1: /2 */
#define ACLK_DIVIDED_BY_4 DIVA_2 /* ACLK Divider 2: /4 */
#define ACLK_DIVIDED_BY_8 DIVA_3 /* ACLK Divider 3: /8 */
uint8_t clock_getMode(void);
uint8_t clock_setup(void);
void clock_dividerSetup(uint8_t MCLKDividerSelect, uint8_t SMCLKDividerSelect, uint8_t ACLKDividerSelect);
#endif /* CLOCK_H_ */
/*
* dac12.c
*
* Created on: 2013. 1. 17.
* Author: OSSI
*/
#include "dac12.h"
void dac12_initDAC0(uint16_t multiplierSelect, uint8_t amplifierSelect)
{
// Clear DAC12ENC to set register
DAC12_0CTL &= ~DAC12ENC;
DAC12_0CTL = multiplierSelect + amplifierSelect + DAC12_TRIGGER_ENCBYPASS;
}
void dac12_initDAC1(uint16_t multiplierSelect, uint8_t amplifierSelect)
{
// Clear DAC12ENC to set register
DAC12_1CTL &= ~DAC12ENC;
DAC12_1CTL = multiplierSelect + amplifierSelect + DAC12_TRIGGER_ENCBYPASS;
}
void dac12_setVolRefDAC0(uint16_t refVoltageSourceSelect)
{
DAC12_0CTL &= ~DAC12ENC;
DAC12_0CTL |= refVoltageSourceSelect;
}
void dac12_setVolRefDAC1(uint16_t refVoltageSourceSelect)
{
DAC12_1CTL &= ~DAC12ENC;
DAC12_1CTL |= refVoltageSourceSelect;
}
void dac12_outputDAC0(uint16_t dacValue)
{
// DAC12_0CTL &= ~DAC12ENC;
DAC12_0DAT = dacValue;
// DAC12_0CTL &= ~DAC12ENC;
}
void dac12_outputDAC1(uint16_t dacValue)
{
// DAC12_0CTL &= ~DAC12ENC;
DAC12_1DAT = dacValue;
// DAC12_0CTL &= ~DAC12ENC;
}
// if dac12_disableDAC0 is called,
// you need to dac12_init() again to start dac12
void dac12_disableDAC0(void)
{
DAC12_0CTL &= ~DAC12ENC;
DAC12_0CTL = 0x0000;
}
void dac12_disableDAC1(void)
{
DAC12_1CTL &= ~DAC12ENC;
DAC12_1CTL = 0x0000;
}
/*
* dac12.h
*
* Created on: 2013. 1. 17.
* Author: OSSI
*/
#ifndef DAC12_H_
#define DAC12_H_
#include "ossiobc.h"
// ports setup is not needed for dac12
// amplifierSelect > 0 -> DAC port ON
#define DAC12_PIN_6_6 (0x01)
#define DAC12_PIN_6_7 (0x10)
// multiplierSelect
#define DAC12_VREFx1 (DAC12IR)
#define DAC12_VREFx3 (!(DAC12IR))
// amplifierSelect
#define DAC12_AMP_OFF_PINOUTHIGHZ (DAC12AMP_0)
#define DAC12_AMP_OFF_PINOUTLOW (DAC12AMP_1)
#define DAC12_AMP_LOWIN_LOWOUT (DAC12AMP_2)
#define DAC12_AMP_LOWIN_MEDOUT (DAC12AMP_3)
#define DAC12_AMP_LOWIN_HIGHOUT (DAC12AMP_4)
#define DAC12_AMP_MEDIN_MEDOUT (DAC12AMP_5)
#define DAC12_AMP_MEDIN_HIGHOUT (DAC12AMP_6)
#define DAC12_AMP_HIGHIN_HIGHOUT (DAC12AMP_7)
#define DAC12_TRIGGER_ENCBYPASS (DAC12LSEL_0)
#define DAC12_TRIGGER_ENC (DAC12LSEL_1)
#define DAC12_TRIGGER_TA (DAC12LSEL_2)
#define DAC12_TRIGGER_TB (DAC12LSEL_3)
// refVoltageSourceSelect
#define DAC12_VREF_INT (DAC12SREF_0)
#define DAC12_VREF_EXT (DAC12SREF_2)
void dac12_initDAC0(uint16_t multiplierSelect, uint8_t amplifierSelect);
void dac12_initDAC1(uint16_t multiplierSelect, uint8_t amplifierSelect);
// make sure you call adc12_setVolReference()
// to set dac12 reference
// and the refVoltageSourceSelect should be matched
// that of adc12
void dac12_setVolRefDAC0(uint16_t refVoltageSourceSelect);
void dac12_setVolRefDAC1(uint16_t refVoltageSourceSelect);
// Watchout the dacValue overflow!!!!!
void dac12_outputDAC0(uint16_t dacValue);
void dac12_outputDAC1(uint16_t dacValue);
// shut down dac12
void dac12_disableDAC0(void);
void dac12_disableDAC1(void);
#endif /* DAC12_H_ */
/* --COPYRIGHT--,BSD
* Copyright (c) 2012, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
//*****************************************************************************
//
//debug.h - Macros for assisting debug of the driver library.
//
//
//This is part of revision 0001 of the MSP430 Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
//Prototype for the function that is called when an invalid argument is passed
//to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__ (char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
//The ASSERT macro, which does the actual assertion checking. Typically, this
//will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) { \
if (!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define ASSERT(expr)
#endif
#endif //__DEBUG_H__
#include "ossiobc.h"
#include "adc12.h"
#include "dac12.h"
/*
* main.c
*/
uint16_t adcValueVccRef[5]={0};
uint16_t adcValueIntRef[5]={0};
uint16_t adcValueExtRef[5]={0};
int main(void) {
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
// to check timing
P6DIR |= BIT0; // P6.0 output
P6OUT |= BIT0;
clock_setup();
uint8_t systemClock;
systemClock = clock_getMode();
if(systemClock == CLOCK_XT2_LFXT1)
{
clock_dividerSetup(MCLK_DIVIDED_BY_1, SMCLK_DIVIDED_BY_1, ACLK_DIVIDED_BY_1);
}
else if(systemClock == CLOCK_DCO_LFXT1)
{
clock_dividerSetup(MCLK_DIVIDED_BY_1, SMCLK_DIVIDED_BY_1, ACLK_DIVIDED_BY_1);
}
adc12_portSetup(ADC12_PIN_6_1+ADC12_PIN_6_2+ADC12_PIN_6_3+ ADC12_PIN_6_4+ADC12_PIN_6_5);
adc12_init(ADC12_CLOCKSOURCE_SMCLK, ADC12_CLOCKDIVIDER_8, ADC12_CYCLEHOLD_16_CYCLES);
// when DAC12 amplifier setting > 0
// P6SEL and P6DIR is ignored
// and function as DAC12 module
// no port setup for DAC12
dac12_initDAC0(DAC12_VREFx1, DAC12_AMP_HIGHIN_HIGHOUT);
dac12_initDAC1(DAC12_VREFx1, DAC12_AMP_HIGHIN_HIGHOUT);
while(1)
{
volatile uint8_t i;
volatile uint16_t j;
/*
* DAC12 section
*/
// you cannot use separate reference settings for dac12 for now
// TODO: change adc12 voltage reference mode
// so we can turn on Vref and Veref at the same time??
// call adc12 ref function to start dac12
// and match the reference setting
// adc12 internal ref -> dac12 internal ref
// adc12 external ref -> dac12 external ref
adc12_setVolReference(ADC12_REF_VREF_VSS);
dac12_setVolRefDAC0(DAC12_VREF_INT);
dac12_setVolRefDAC1(DAC12_VREF_INT);
for(j = 0 ; j < 4096; j++)
{
// Vout = 2.5V REF * (dacValue + 1) / 4096
dac12_outputDAC0((uint16_t)(j/2));
// if j is bigger or equal to 4096, dac12 outputs 0
// overflow warning
dac12_outputDAC1(j);
}
// back to 0V
dac12_outputDAC0(0);
dac12_outputDAC1(0);
// turn off adc12 ref when dac12 if finished
adc12_offInternalVolReference();
// if dac12_disableDAC0 is called,
// you need to dac12_init() again to start dac12
// dac12_disableDAC0();
// dac12_disableDAC1();
/*
* ADC12 section
*/
// Vref = VCC
adc12_setVolReference(ADC12_REF_VCC_VSS);
for (i = 0; i < 5;i++)
{
adcValueVccRef[i] = adc12_readChannel(i+1);
// Convert the value to 0 ~ 3300 mV (3300/2^12 = 0.8056)
adcValueVccRef[i] = (uint16_t)(0.8056 * adcValueVccRef[i]);
}
// Vref = Internal Ref 2.5V
adc12_setVolReference(ADC12_REF_VREF_VSS);
for (i = 0; i < 5;i++)
{
adcValueIntRef[i] = adc12_readChannel(i+1);
// Convert the value to 0 ~ 2500 mV (2500/2^12 = 0.6103)
adcValueIntRef[i] = (uint16_t)(0.6103 * adcValueIntRef[i]);
}
// When we use internal reference,
// Make sure you turn it off to save power
adc12_offInternalVolReference();
// Vref = Internal Ref 1.25V
adc12_setVolReference(ADC12_REF_V_EREF_VSS);
for (i = 0; i < 5;i++)
{
adcValueExtRef[i] = adc12_readChannel(i+1);
// Convert the value to 0 ~ 1250 mV (2500/2^12 = 0.3051)
adcValueExtRef[i] = (uint16_t)(0.3051 * adcValueExtRef[i]);
}
_NOP();
// LPM3;
}
}
/*
* ossiobc.h
*
* Created on: 2013. 1. 6.
* Author: OSSI
*/
#ifndef OSSIOBC_H_
#define OSSIOBC_H_
#include "msp430f1611.h"
#include "ossitypes.h"
#include "clock.h"
#include "debug.h"
#endif /* OSSIOBC_H_ */
/*
* ossitypes.h
*
* Created on: 2012. 12. 22.
* Author: OSSI
*/
#ifndef OSSITYPES_H_
#define OSSITYPES_H_
typedef unsigned char uint8_t;
typedef signed char int8_t;
typedef unsigned short int uint16_t;
typedef signed short int int16_t;
typedef unsigned long int uint32_t;
typedef signed long int int32_t;
#endif /* OSSITYPES_H_ */
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