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@p-pavel
Last active August 31, 2023 08:14
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PDP-11 architecture
import compiletime.ops.int.S
type Nat[n <: Int] =
n match
case 0 => 0
case S[n] => S[n] | Nat[n]
type Octal = Nat[7]
object Registers:
type Flags = Nat[15]
val N: Flags = 8
val Z: Flags = 4
val V: Flags = 2
val C: Flags = 1
extension (f: Flags)
inline def | (g: Flags) = f | g
inline def & (g: Flags) = f & g
inline def ^ (g: Flags) = f ^g
inline def ~ = ~f
val a = N | Z
extension (r: Register) inline def toOctal = r
opaque type Register = Octal
opaque type BasicMode <: Mode = 0 | 1 | 2 | 3
opaque type Mode = Octal
inline def r(i: Octal): Register = i
val R0 = r(0)
val R1 = r(1)
val R2 = r(2)
val R3 = r(3)
val R4 = r(4)
val R5 = r(5)
val R6 = r(6)
val R7 = r(7)
inline def PC = R7
inline def SP = R6
trait AddressingModes:
type BasicMode
type Mode >: BasicMode
import Registers.*
final given Conversion[Register, BasicMode] = _.direct
extension (r: Register)
def direct: BasicMode
def inc: BasicMode
def dec: BasicMode
def apply(offset: Short): BasicMode
extension (mode: BasicMode) def defer: Mode
type Command
type SizedCommand <: Command
extension (s: SizedCommand) def b: Command
type TwoArgSized = (Mode, Mode) => SizedCommand
type TwoArg = (Mode, Mode) => Command
val mov, cmp, bit, bic, bis: TwoArgSized
val add, sub: TwoArg
// TODO: mul,div, ash, ashc
type SingleArg = Mode => Command
type SingleArgSized = Mode => SizedCommand
val jmp, swab, mtps, mfps, sxt: SingleArg
val clr, com, inc, dec, neg, adc, sbc, tst, ror, rol, asr, asl: SingleArg
type Offset = Byte
type Branch = Offset => Command
val br, bne, beq, bge, blt, bgt, ble, bpl, bmi, bhi, blos, bvc, bvs, bcc,
bcs: Branch
def sob(r: Register, off: Offset): Command
def jsr(r: Register, addr: Mode): Command
def rts(r: Register): Command
def mark(n: Nat[31]): Command
type VectorId = Nat[255]
def emt(v: VectorId): Command
def trap(v: VectorId): Command
val rti, bpt, iot, rtt, halt, Wait, reset: Command //TODO: wait?
def clearFlags(f: Flags): Command
def setFlags(f: Flags): Command
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