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paulburton/ci20-clk.diff

Created July 23, 2018 17:05
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Ci20 clk_summary diff
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ci20-clk.diff
--- ci20-clk.txt 2018-07-23 10:01:50.208091103 -0700
+++ ci20-clk-pc.txt 2018-07-23 10:02:58.591727593 -0700
@@ -3,7 +3,17 @@
clock count count count rate accuracy phase
----------------------------------------------------------------------------------------
rtc 0 0 0 32768 0 0
- ext 10 10 0 48000000 0 0
+ wdt 0 0 0 32768 0 0
+ ext 12 12 0 48000000 0 0
+ ost 0 0 0 48000000 0 0
+ timer7 0 0 0 48000000 0 0
+ timer6 0 0 0 48000000 0 0
+ timer5 0 0 0 48000000 0 0
+ timer4 0 0 0 48000000 0 0
+ timer3 0 0 0 48000000 0 0
+ timer2 0 0 0 48000000 0 0
+ timer1 0 0 0 48000000 0 0
+ timer0 1 1 0 48000000 0 0
x2d 0 0 0 48000000 0 0
des 0 0 0 48000000 0 0
ahb_mon 0 0 0 48000000 0 0
@@ -74,4 +84,4 @@
l2cache 0 0 0 600000000 0 0
cpu 0 0 0 1200000000 0 0
core1 0 0 0 1200000000 0 0
- apll 0 0 0 400000000 0 0
+ apll 0 0 0 400000000 0 0
\ No newline at end of file
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