Created
July 23, 2018 16:39
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Ci20 clk_summary
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| # cat /sys/kernel/debug/clk/clk_summary | |
| enable prepare protect | |
| clock count count count rate accuracy phase | |
| ---------------------------------------------------------------------------------------- | |
| rtc 0 0 0 32768 0 0 | |
| wdt 0 0 0 32768 0 0 | |
| ext 12 12 0 48000000 0 0 | |
| ost 0 0 0 48000000 0 0 | |
| timer7 0 0 0 48000000 0 0 | |
| timer6 0 0 0 48000000 0 0 | |
| timer5 0 0 0 48000000 0 0 | |
| timer4 0 0 0 48000000 0 0 | |
| timer3 0 0 0 48000000 0 0 | |
| timer2 0 0 0 48000000 0 0 | |
| timer1 0 0 0 48000000 0 0 | |
| timer0 1 1 0 48000000 0 0 | |
| x2d 0 0 0 48000000 0 0 | |
| des 0 0 0 48000000 0 0 | |
| ahb_mon 0 0 0 48000000 0 0 | |
| uart4 1 1 0 48000000 0 0 | |
| otg1 0 0 0 48000000 0 0 | |
| gpvlc 0 0 0 48000000 0 0 | |
| aic1 0 0 0 48000000 0 0 | |
| compress 0 0 0 48000000 0 0 | |
| tssi1 0 0 0 48000000 0 0 | |
| ipu 0 0 0 48000000 0 0 | |
| lcd 0 0 0 48000000 0 0 | |
| tve 0 0 0 48000000 0 0 | |
| cim 0 0 0 48000000 0 0 | |
| mac 0 0 0 48000000 0 0 | |
| gps 0 0 0 48000000 0 0 | |
| pdma 1 1 0 48000000 0 0 | |
| uart3 1 1 0 48000000 0 0 | |
| uart2 0 0 0 48000000 0 0 | |
| uart1 1 1 0 48000000 0 0 | |
| uart0 1 1 0 48000000 0 0 | |
| sadc 0 0 0 48000000 0 0 | |
| kbc 0 0 0 48000000 0 0 | |
| owi 0 0 0 48000000 0 0 | |
| tssi0 0 0 0 48000000 0 0 | |
| aic 0 0 0 48000000 0 0 | |
| scc 0 0 0 48000000 0 0 | |
| otg0 0 0 0 48000000 0 0 | |
| pcm 0 0 0 48000000 0 0 | |
| ssi 0 0 0 48000000 0 0 | |
| ssi2 0 0 0 48000000 0 0 | |
| ssi1 0 0 0 48000000 0 0 | |
| ssi0 0 0 0 48000000 0 0 | |
| i2s 0 0 0 48000000 0 0 | |
| sclk_a 0 0 0 48000000 0 0 | |
| bch 0 0 0 48000000 0 0 | |
| hdmi 0 0 0 48000000 0 0 | |
| gpu 0 0 0 48000000 0 0 | |
| pcm_pll 0 0 0 48000000 0 0 | |
| cim_mclk 0 0 0 48000000 0 0 | |
| ssi_pll 0 0 0 48000000 0 0 | |
| uhc 0 0 0 48000000 0 0 | |
| msc_mux 0 0 0 48000000 0 0 | |
| msc2 0 0 0 24000000 0 0 | |
| msc1 0 0 0 93750 0 0 | |
| msc0 0 0 0 93750 0 0 | |
| lcd1pixclk 0 0 0 48000000 0 0 | |
| lcd0pixclk 0 0 0 48000000 0 0 | |
| i2s_pll 0 0 0 48000000 0 0 | |
| vpu 0 0 0 48000000 0 0 | |
| otg_phy 0 0 0 48000000 0 0 | |
| vpll 0 0 0 48000000 0 0 | |
| epll 0 0 0 48000000 0 0 | |
| mpll 1 1 0 1200000000 0 0 | |
| ddr 0 0 0 400000000 0 0 | |
| ddr1 0 0 0 400000000 0 0 | |
| ddr0 0 0 0 400000000 0 0 | |
| ahb2_apb_mux 1 1 0 1200000000 0 0 | |
| pclk 0 0 0 100000000 0 0 | |
| smb4 0 0 0 100000000 0 0 | |
| smb3 0 0 0 100000000 0 0 | |
| smb2 0 0 0 100000000 0 0 | |
| smb1 0 0 0 100000000 0 0 | |
| smb0 0 0 0 100000000 0 0 | |
| ahb2 1 1 0 200000000 0 0 | |
| nemc 1 1 0 200000000 0 0 | |
| ahb0 0 0 0 400000000 0 0 | |
| cpumux 0 0 0 1200000000 0 0 | |
| l2cache 0 0 0 600000000 0 0 | |
| cpu 0 0 0 1200000000 0 0 | |
| core1 0 0 0 1200000000 0 0 | |
| apll 0 0 0 400000000 0 0 |
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