In the CV32E41P current code, interrupts are mapped in a 32-bit signal. https://github.com/litex-hub/pythondata-cpu-cv32e41p/blob/master/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_core.sv#L85
This interrupt signal goes into the mip CSR: https://github.com/litex-hub/pythondata-cpu-cv32e41p/blob/master/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_int_controller.sv#L59-L70
LiteX software layer uses two fast interrupts (timer at index 1, uart at index 0). It must be mapped on bits 17 and 16 (the 2 first fast interrupts). => Added a 16-bit padding vector.