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pdp7/litex-tftp-linux.txt

Last active February 19, 2020 22:36
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tftp linux litex
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litex-tftp-linux.txt
pdp7@x1:~/dev$ cd litex-buildenv/
pdp7@x1:~/dev/litex-buildenv$ export CPU=vexriscv CPU_VARIANT=linux PLATFORM=arty TARGET=net FIRMWARE=linux
pdp7@x1:~/dev/litex-buildenv$ source ./scripts/enter-env.sh
This script is: /home/pdp7/dev/litex-buildenv/scripts/enter-env.sh
Firmware directory: /home/pdp7/dev/litex-buildenv
Build directory is: /home/pdp7/dev/litex-buildenv/build
3rd party directory is: /home/pdp7/dev/litex-buildenv/third_party
Checking environment
---------------------------------
Platform: arty
Target: net (default: net)
CPU: vexriscv.linux (default: lm32)
Firmare: linux (default: firmware)
Architecture: riscv32
python found at 3.7
Checking FPGA toolchain
---------------------------------------
yosys found at /home/pdp7/dev/litex-buildenv/build/conda/bin/yosys
Platform Toolchain: Xilinx
Xilinx directory is: /home/pdp7/dev/litex-buildenv/build/Xilinx/opt/Xilinx/
- Xilinx ISE toolchain found!
- Xilinx Vivado toolchain found!
Xilinx license in: /home/pdp7/dev/litex-buildenv/build/Xilinx
Checking programming tools in environment
-----------------------------------------
flterm found at /home/pdp7/dev/litex-buildenv/build/conda/bin/flterm
openocd found at 0.10.0
Checking C compiler toolchain
---------------------------------------
riscv32-elf-ld found at 2.32
riscv32-elf-gcc found at 9.1.0
Checking Python modules in environment
---------------------------------------
serial found
IPython found
progressbar found
colorama found
hexfile found at 0.1.1
hdmi2usb.modeswitch found at v0.0.1.post58
Updating git config
-----------------------
Checking git submodules
-----------------------
3a6108a75be356a3dc53760d22782f1323248b6b third_party/edid-decode (heads/master)
3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 third_party/flash_proxies (heads/master)
5a90a8b0dde504d383ffcc3c1ad6e0724caf5713 third_party/litedram (heads/master)
f532a12b40648e84cef626e9343f428e5e366fb4 third_party/liteeth (heads/master)
061418c620cb09e32aafc202ed1379a29c49cc17 third_party/litepcie (heads/master)
1e3573b07d382eac50ef764fd839009bf90cb8ce third_party/litesata (heads/master)
daf10e9473fb70b3034e0331ef89005661ac04e0 third_party/litescope (heads/master)
7457a29b1a47fe15e81fa37f3bbdd510788f1d53 third_party/liteusb (heads/master)
49bafa481075e0bfbaf067b63c351ec29e993894 third_party/litevideo (49bafa4)
02bfda5e38f33c66e2fe9bb2f63ec02756657233 third_party/litex (02bfda5e)
bd557ff00d8fe2473fcf346e36c96d004e94b8ca third_party/litex/litex/build/sim/core/modules/ethernet/tapcfg (heads/master)
84b3e3ca0ad9535acaef201c1482342871358b08 third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule (heads/master)
0518621134dd7a551cac5758d9171a24d0c1578f third_party/litex/litex/soc/cores/cpu/minerva/verilog (0518621)
69b97fcb43b35d6c6639ecc68e63d912c09ee8da third_party/litex/litex/soc/cores/cpu/mor1kx/verilog (v1.0-133-g69b97fc)
a9e0ea54cffa162cfe901ff8d30d8877a18c6d8e third_party/litex/litex/soc/cores/cpu/picorv32/verilog (v1.0~45)
d67a7d7a12ff06297226b1862412849c4d50e949 third_party/litex/litex/soc/cores/cpu/rocket/verilog (d67a7d7)
854f9bd2282c97251ce65e4117c5cf1630722004 third_party/litex/litex/soc/cores/cpu/vexriscv/verilog (heads/master)
5f0c7a7faf6b65c907a93be6e3723e297d37ee71 third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/ext/VexRiscv (1.0.1-265-g5f0c7a7)
539398c1481203a51115b5f1228ea961f0ac9bd3 third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/ext/VexRiscv/src/test/resources/VexRiscvRegressionData (heads/master)
81fb4f00c2cfe13814765968e09931ffa93b5138 third_party/litex/litex/soc/software/compiler_rt (81fb4f00c)
70e884e88c25d997ea5e3dd1e2a8bb08f0d02f90 third_party/litex-renode (heads/master)
d11565a8ead28eb5a18d7d4f57abe2a7562cdc8c third_party/migen (0.6.dev-328-gd11565a)
f207f3f62098a56d24de90bb833f02eedf55b054 third_party/nmigen (v0.1-4-gf207f3f)
migen found
nmigen found
litex found
litedram found
liteeth found
litepcie found
litesata found
litescope found
litevideo found
-----------------------
On branch master
Your branch is up to date with 'origin/master'.
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git checkout -- <file>..." to discard changes in working directory)
(commit or discard the untracked or modified content in submodules)
modified: third_party/litex (modified content)
no changes added to commit (use "git add" and/or "git commit -a")
-----------------------
Completed loading environment.
(LX P=arty C=vexriscv.linux F=linux) pdp7@x1:~/dev/litex-buildenv$ ls -ltar build/arty_net_vexriscv.linux/software/linux
total 20692
-rw-r--r-- 1 pdp7 pdp7 1842 Jul 26 2019 rv32.dtb
drwxr-xr-x 10 pdp7 pdp7 4096 Feb 2 17:05 ..
-rw-r--r-- 1 pdp7 pdp7 0 Feb 2 17:05 riscv32-rootfs.cpio
drwxr-xr-x 4 pdp7 pdp7 4096 Feb 2 17:05 include
drwxr-xr-x 3 pdp7 pdp7 4096 Feb 2 17:05 arch
drwxr-xr-x 2 pdp7 pdp7 4096 Feb 2 17:06 .tmp_versions
drwxr-xr-x 6 pdp7 pdp7 4096 Feb 2 17:06 scripts
drwxr-xr-x 2 pdp7 pdp7 4096 Feb 2 17:06 usr
drwxr-xr-x 2 pdp7 pdp7 4096 Feb 2 17:06 certs
drwxr-xr-x 2 pdp7 pdp7 4096 Feb 2 17:06 init
drwxr-xr-x 2 pdp7 pdp7 4096 Feb 2 17:06 ipc
drwxr-xr-x 2 pdp7 pdp7 4096 Feb 2 17:06 security
drwxr-xr-x 2 pdp7 pdp7 4096 Feb 2 17:06 crypto
drwxr-xr-x 3 pdp7 pdp7 4096 Feb 2 17:06 block
drwxr-xr-x 2 pdp7 pdp7 4096 Feb 2 17:06 sound
drwxr-xr-x 2 pdp7 pdp7 4096 Feb 2 17:06 firmware
drwxr-xr-x 2 pdp7 pdp7 4096 Feb 2 17:06 net
drwxr-xr-x 2 pdp7 pdp7 4096 Feb 2 17:06 mm
drwxr-xr-x 3 pdp7 pdp7 4096 Feb 2 17:06 virt
drwxr-xr-x 11 pdp7 pdp7 4096 Feb 2 17:06 fs
drwxr-xr-x 11 pdp7 pdp7 4096 Feb 2 17:06 kernel
drwxr-xr-x 6 pdp7 pdp7 12288 Feb 2 17:06 lib
drwxr-xr-x 42 pdp7 pdp7 4096 Feb 2 17:06 drivers
-rw-r--r-- 1 pdp7 pdp7 2 Feb 2 17:06 .version
-rw-r--r-- 1 pdp7 pdp7 176108 Feb 2 17:06 built-in.a
-rw-r--r-- 1 pdp7 pdp7 6121292 Feb 2 17:06 vmlinux.o
-rw-r--r-- 1 pdp7 pdp7 0 Feb 2 17:06 Module.symvers
-rwxr-xr-x 1 pdp7 pdp7 3016688 Feb 2 17:06 .tmp_vmlinux1
-rw-r--r-- 1 pdp7 pdp7 811924 Feb 2 17:06 .tmp_kallsyms1.S
-rw-r--r-- 1 pdp7 pdp7 140564 Feb 2 17:06 .tmp_kallsyms1.o
-rwxr-xr-x 1 pdp7 pdp7 3156196 Feb 2 17:06 .tmp_vmlinux2
-rw-r--r-- 1 pdp7 pdp7 811924 Feb 2 17:06 .tmp_kallsyms2.S
-rw-r--r-- 1 pdp7 pdp7 140564 Feb 2 17:06 .tmp_kallsyms2.o
-rwxr-xr-x 1 pdp7 pdp7 3156196 Feb 2 17:06 vmlinux
-rw-r--r-- 1 pdp7 pdp7 371777 Feb 2 17:06 System.map
-rw-r--r-- 1 pdp7 pdp7 371777 Feb 2 17:06 .tmp_System.map
-rw-r--r-- 1 pdp7 pdp7 155 Feb 2 17:06 .vmlinux.cmd
-rw-r--r-- 1 pdp7 pdp7 2717932 Feb 19 22:33 firmware.fbi
-rw-r--r-- 1 pdp7 pdp7 22648 Feb 19 22:45 .config.old
-rw-r--r-- 1 pdp7 pdp7 22648 Feb 19 22:45 .config
lrwxrwxrwx 1 pdp7 pdp7 47 Feb 19 22:45 source -> /home/pdp7/dev/litex-buildenv/third_party/linux
-rw-r--r-- 1 pdp7 pdp7 437 Feb 19 22:45 Makefile
-rw-r--r-- 1 pdp7 pdp7 0 Feb 19 22:45 modules.order
-rw-r--r-- 1 pdp7 pdp7 1186 Feb 19 22:45 .missing-syscalls.d
lrwxrwxrwx 1 pdp7 pdp7 97 Feb 19 22:45 firmware.bin -> /home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux//software/linux/arch/riscv/boot/Image
drwxr-xr-x 22 pdp7 pdp7 4096 Feb 19 22:45 .
(LX P=arty C=vexriscv.linux F=linux) pdp7@x1:~/dev/litex-buildenv$ make gateware
mkdir -p build/arty_net_vexriscv.linux/
time python -u ./make.py --platform=arty --target=net --cpu-type=vexriscv --iprange=192.168.100 -Ob toolchain_path /home/pdp7/dev/litex-buildenv/build/Xilinx/opt/Xilinx/ --cpu-variant=linux --cpu-variant=linux \
2>&1 | tee -a /home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux//output.20200219-232752.log; (exit ${PIPESTATUS[0]})
[WARNING] Deprecated, please update : shadow_base replaced by IO regions.
make[1]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule.
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/libcompiler_rt'
make[1]: Nothing to be done for 'all'.
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/libcompiler_rt'
make[1]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule.
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/libbase'
CC exception.o
CC system.o
CC id.o
CC uart.o
CC time.o
CC spiflash.o
CC mdio.o
AR libbase.a
AR libbase-nofloat.a
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/libbase'
make[1]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule.
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/libnet'
CC microudp.o
AR libnet.a
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/libnet'
make[1]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule.
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/bios'
CC isr.o
CC sdram.o
CC main.o
CC boot.o
LD bios.elf
chmod -x bios.elf
OBJCOPY bios.bin
chmod -x bios.bin
python -m litex.soc.software.mkmscimg bios.bin --little
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/bios'
make[1]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule.
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/uip'
CC clock-arch.o
CC liteethmac-drv.o
AR libuip.a
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/uip'
make[1]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule.
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/firmware'
CC bist.o
CC ci.o
/home/pdp7/dev/litex-buildenv/firmware/ci.c: In function 'status_short_print':
/home/pdp7/dev/litex-buildenv/firmware/ci.c:368:15: warning: unused variable 'underflows' [-Wunused-variable]
unsigned int underflows;
^~~~~~~~~~
/home/pdp7/dev/litex-buildenv/firmware/ci.c: In function 'status_print':
/home/pdp7/dev/litex-buildenv/firmware/ci.c:467:15: warning: unused variable 'underflows' [-Wunused-variable]
unsigned int underflows;
^~~~~~~~~~
At top level:
/home/pdp7/dev/litex-buildenv/firmware/ci.c:1002:21: warning: 'log2' defined but not used [-Wunused-function]
static unsigned int log2(unsigned int v)
^~~~
CC config.o
CC encoder.o
CC etherbone.o
CC ethernet.o
CC fx2.o
CC hdmi_in0.o
CC hdmi_out0.o
CC hdmi_out1.o
CC heartbeat.o
CC isr.o
CC main.o
CC mdio.o
CC mmcm.o
/home/pdp7/dev/litex-buildenv/firmware/mmcm.c: In function 'mmcm_dump_all':
/home/pdp7/dev/litex-buildenv/firmware/mmcm.c:110:6: warning: unused variable 'i' [-Wunused-variable]
int i;
^
CC oled.o
CC opsis_eeprom.o
bash /home/pdp7/dev/litex-buildenv/firmware/version_data.sh
# Check the version files exist
[ -e /home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/include/../..//software/firmware/version_data.h ]
[ -e /home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/include/../..//software/firmware/version_data.c ]
CC pattern.o
CC pll.o
CC processor.o
/home/pdp7/dev/litex-buildenv/firmware/processor.c: In function 'fb_set_mode':
/home/pdp7/dev/litex-buildenv/firmware/processor.c:532:15: warning: unused variable 'hdmi_out1_enabled' [-Wunused-variable]
unsigned int hdmi_out1_enabled;
^~~~~~~~~~~~~~~~~
/home/pdp7/dev/litex-buildenv/firmware/processor.c:531:15: warning: unused variable 'hdmi_out0_enabled' [-Wunused-variable]
unsigned int hdmi_out0_enabled;
^~~~~~~~~~~~~~~~~
/home/pdp7/dev/litex-buildenv/firmware/processor.c: In function 'processor_service':
/home/pdp7/dev/litex-buildenv/firmware/processor.c:793:29: warning: unused variable 'm' [-Wunused-variable]
const struct video_timing *m = &video_modes[processor_mode];
^
At top level:
/home/pdp7/dev/litex-buildenv/firmware/processor.c:449:13: warning: 'fb_clkgen_write' defined but not used [-Wunused-function]
static void fb_clkgen_write(int m, int d)
^~~~~~~~~~~~~~~
CC reboot.o
CC stdio_wrap.o
CC tofe_eeprom.o
CC uptime.o
CC version.o
CC pcie.o
CC /home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/include/../..//software/firmware/hdmi_in1.o
LD firmware.elf
chmod -x firmware.elf
OBJCOPY firmware.bin
chmod -x firmware.bin
python -m litex.soc.software.mkmscimg -f --little firmware.bin -o firmware.fbi
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/firmware'
DEBUG:RDI_PROG:/opt/Xilinx/Vivado/2017.3/bin/unwrapped/lnx64.o/vivado
****** Vivado v2017.3 (64-bit)
**** SW Build 2018833 on Wed Oct 4 19:58:07 MDT 2017
**** IP Build 2016188 on Wed Oct 4 21:52:56 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
INFO: [Common 17-1239] XILINX_LOCAL_USER_DATA is set to 'no'.
source top.tcl
# create_project -force -name top -part xc7a35t-csg324-1
# set_msg_config -id {Common 17-55} -new_severity {Warning}
# read_verilog {/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v}
# read_verilog {/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v}
# read_xdc top.xdc
# synth_design -directive default -top top -part xc7a35t-csg324-1
Command: synth_design -directive default -top top -part xc7a35t-csg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 9955
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1220.234 ; gain = 74.000 ; free physical = 8850 ; free virtual = 12128
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'top' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:333]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1214]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1217]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1220]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1303]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1306]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1309]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1392]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1395]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1398]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1481]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1484]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1487]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1570]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1573]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1576]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1659]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1662]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1665]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1748]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1751]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1754]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1837]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1840]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1843]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1898]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1901]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1905]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:1908]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:2046]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:2048]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:2449]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:2454]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:2497]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:2502]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3800]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3800]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3801]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3801]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3810]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3810]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3811]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3811]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3814]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3814]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3815]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3815]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3816]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3816]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3817]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3817]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3818]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3818]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3819]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3819]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3820]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3820]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3821]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3821]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3822]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3822]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3823]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3823]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3824]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3824]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3825]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3825]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3826]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3826]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3827]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3827]
INFO: [Synth 8-3876] $readmem data file 'mem.init' is read successfully [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14422]
INFO: [Synth 8-3876] $readmem data file 'mem_1.init' is read successfully [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14442]
INFO: [Synth 8-3876] $readmem data file 'mem_2.init' is read successfully [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14488]
INFO: [Synth 8-155] case statement is not full and has no default [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:10716]
INFO: [Synth 8-155] case statement is not full and has no default [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12955]
INFO: [Synth 8-155] case statement is not full and has no default [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12983]
INFO: [Synth 8-155] case statement is not full and has no default [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13064]
INFO: [Synth 8-155] case statement is not full and has no default [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13146]
INFO: [Synth 8-155] case statement is not full and has no default [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13260]
INFO: [Synth 8-155] case statement is not full and has no default [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13283]
INFO: [Synth 8-155] case statement is not full and has no default [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13444]
INFO: [Synth 8-155] case statement is not full and has no default [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13748]
INFO: [Synth 8-155] case statement is not full and has no default [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13770]
INFO: [Synth 8-155] case statement is not full and has no default [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13864]
INFO: [Synth 8-638] synthesizing module 'PLLE2_BASE' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:40130]
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
Parameter CLKFBOUT_MULT bound to: 16 - type: integer
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float
Parameter CLKOUT0_DIVIDE bound to: 16 - type: integer
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT2_DIVIDE bound to: 4 - type: integer
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT2_PHASE bound to: 90.000000 - type: float
Parameter CLKOUT3_DIVIDE bound to: 8 - type: integer
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT4_DIVIDE bound to: 32 - type: integer
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT5_DIVIDE bound to: 16 - type: integer
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter REF_JITTER1 bound to: 0.010000 - type: float
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-256] done synthesizing module 'PLLE2_BASE' (1#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:40130]
WARNING: [Synth 8-350] instance 'PLLE2_BASE' of module 'PLLE2_BASE' requires 12 connections, but only 10 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14509]
INFO: [Synth 8-638] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-256] done synthesizing module 'BUFG' (2#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:607]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14552]
INFO: [Synth 8-638] synthesizing module 'IDELAYCTRL' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:21504]
Parameter SIM_DEVICE bound to: 7SERIES - type: string
INFO: [Synth 8-256] done synthesizing module 'IDELAYCTRL' (3#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:21504]
WARNING: [Synth 8-350] instance 'IDELAYCTRL' of module 'IDELAYCTRL' requires 3 connections, but only 2 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14552]
INFO: [Synth 8-638] synthesizing module 'BUFR' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:884]
Parameter BUFR_DIVIDE bound to: 4 - type: string
Parameter SIM_DEVICE bound to: 7SERIES - type: string
INFO: [Synth 8-256] done synthesizing module 'BUFR' (4#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:884]
INFO: [Synth 8-638] synthesizing module 'DNA_PORT' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:3032]
Parameter SIM_DNA_VALUE bound to: 57'b000000000000000000000000000000000000000000000000000000000
INFO: [Synth 8-256] done synthesizing module 'DNA_PORT' (5#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:3032]
INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:52527]
Parameter INIT_40 bound to: 16'b1001000000000000
Parameter INIT_41 bound to: 16'b0010111011110000
Parameter INIT_42 bound to: 16'b0000010000000000
Parameter INIT_43 bound to: 16'b0000000000000000
Parameter INIT_44 bound to: 16'b0000000000000000
Parameter INIT_45 bound to: 16'b0000000000000000
Parameter INIT_46 bound to: 16'b0000000000000000
Parameter INIT_47 bound to: 16'b0000000000000000
Parameter INIT_48 bound to: 16'b0100011100000001
Parameter INIT_49 bound to: 16'b0000000000001111
Parameter INIT_4A bound to: 16'b0100011100000000
Parameter INIT_4B bound to: 16'b0000000000000000
Parameter INIT_4C bound to: 16'b0000000000000000
Parameter INIT_4D bound to: 16'b0000000000000000
Parameter INIT_4E bound to: 16'b0000000000000000
Parameter INIT_4F bound to: 16'b0000000000000000
Parameter INIT_50 bound to: 16'b1011010111101101
Parameter INIT_51 bound to: 16'b0101100110011001
Parameter INIT_52 bound to: 16'b1010000101000111
Parameter INIT_53 bound to: 16'b1101110111011101
Parameter INIT_54 bound to: 16'b1010100100111010
Parameter INIT_55 bound to: 16'b0101000100010001
Parameter INIT_56 bound to: 16'b1001000111101011
Parameter INIT_57 bound to: 16'b1010111001001110
Parameter INIT_58 bound to: 16'b0101100110011001
Parameter INIT_59 bound to: 16'b0000000000000000
Parameter INIT_5A bound to: 16'b0000000000000000
Parameter INIT_5B bound to: 16'b0000000000000000
Parameter INIT_5C bound to: 16'b0101000100010001
Parameter INIT_5D bound to: 16'b0000000000000000
Parameter INIT_5E bound to: 16'b0000000000000000
Parameter INIT_5F bound to: 16'b0000000000000000
Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0
Parameter IS_DCLK_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: 7SERIES - type: string
Parameter SIM_MONITOR_FILE bound to: design.txt - type: string
INFO: [Synth 8-256] done synthesizing module 'XADC' (6#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:52527]
WARNING: [Synth 8-689] width (7) of port connection 'CHANNEL' does not match port width (5) of module 'XADC' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14616]
WARNING: [Synth 8-350] instance 'XADC' of module 'XADC' requires 24 connections, but only 20 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14601]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14624]
INFO: [Synth 8-638] synthesizing module 'STARTUPE2' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:50875]
Parameter PROG_USR bound to: FALSE - type: string
Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: float
INFO: [Synth 8-256] done synthesizing module 'STARTUPE2' (7#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:50875]
WARNING: [Synth 8-350] instance 'STARTUPE2' of module 'STARTUPE2' requires 13 connections, but only 9 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14624]
INFO: [Synth 8-638] synthesizing module 'OSERDESE2' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:31221]
Parameter DATA_RATE_OQ bound to: DDR - type: string
Parameter DATA_RATE_TQ bound to: BUF - type: string
Parameter DATA_WIDTH bound to: 8 - type: integer
Parameter INIT_OQ bound to: 1'b0
Parameter INIT_TQ bound to: 1'b0
Parameter IS_CLKDIV_INVERTED bound to: 1'b0
Parameter IS_CLK_INVERTED bound to: 1'b0
Parameter IS_D1_INVERTED bound to: 1'b0
Parameter IS_D2_INVERTED bound to: 1'b0
Parameter IS_D3_INVERTED bound to: 1'b0
Parameter IS_D4_INVERTED bound to: 1'b0
Parameter IS_D5_INVERTED bound to: 1'b0
Parameter IS_D6_INVERTED bound to: 1'b0
Parameter IS_D7_INVERTED bound to: 1'b0
Parameter IS_D8_INVERTED bound to: 1'b0
Parameter IS_T1_INVERTED bound to: 1'b0
Parameter IS_T2_INVERTED bound to: 1'b0
Parameter IS_T3_INVERTED bound to: 1'b0
Parameter IS_T4_INVERTED bound to: 1'b0
Parameter SERDES_MODE bound to: MASTER - type: string
Parameter SRVAL_OQ bound to: 1'b0
Parameter SRVAL_TQ bound to: 1'b0
Parameter TBYTE_CTL bound to: FALSE - type: string
Parameter TBYTE_SRC bound to: FALSE - type: string
Parameter TRISTATE_WIDTH bound to: 1 - type: integer
INFO: [Synth 8-256] done synthesizing module 'OSERDESE2' (8#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:31221]
WARNING: [Synth 8-350] instance 'OSERDESE2' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14658]
INFO: [Synth 8-638] synthesizing module 'OBUFDS' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:27284]
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
INFO: [Synth 8-256] done synthesizing module 'OBUFDS' (9#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:27284]
WARNING: [Synth 8-350] instance 'OSERDESE2_1' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14686]
WARNING: [Synth 8-350] instance 'OSERDESE2_2' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14708]
WARNING: [Synth 8-350] instance 'OSERDESE2_3' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14730]
WARNING: [Synth 8-350] instance 'OSERDESE2_4' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14752]
WARNING: [Synth 8-350] instance 'OSERDESE2_5' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14774]
WARNING: [Synth 8-350] instance 'OSERDESE2_6' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14796]
WARNING: [Synth 8-350] instance 'OSERDESE2_7' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14818]
WARNING: [Synth 8-350] instance 'OSERDESE2_8' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14840]
WARNING: [Synth 8-350] instance 'OSERDESE2_9' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14862]
WARNING: [Synth 8-350] instance 'OSERDESE2_10' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14884]
WARNING: [Synth 8-350] instance 'OSERDESE2_11' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14906]
WARNING: [Synth 8-350] instance 'OSERDESE2_12' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14928]
WARNING: [Synth 8-350] instance 'OSERDESE2_13' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14950]
WARNING: [Synth 8-350] instance 'OSERDESE2_14' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14972]
WARNING: [Synth 8-350] instance 'OSERDESE2_15' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14994]
WARNING: [Synth 8-350] instance 'OSERDESE2_16' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15016]
WARNING: [Synth 8-350] instance 'OSERDESE2_17' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15038]
WARNING: [Synth 8-350] instance 'OSERDESE2_18' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15060]
WARNING: [Synth 8-350] instance 'OSERDESE2_19' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15082]
WARNING: [Synth 8-350] instance 'OSERDESE2_20' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15104]
WARNING: [Synth 8-350] instance 'OSERDESE2_21' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15126]
WARNING: [Synth 8-350] instance 'OSERDESE2_22' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15148]
WARNING: [Synth 8-350] instance 'OSERDESE2_23' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15170]
WARNING: [Synth 8-350] instance 'OSERDESE2_24' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15192]
WARNING: [Synth 8-350] instance 'OSERDESE2_25' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15214]
WARNING: [Synth 8-350] instance 'OSERDESE2_26' of module 'OSERDESE2' requires 27 connections, but only 17 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15236]
INFO: [Synth 8-638] synthesizing module 'OBUFTDS' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:27501]
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
INFO: [Synth 8-256] done synthesizing module 'OBUFTDS' (10#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:27501]
WARNING: [Synth 8-350] instance 'OSERDESE2_27' of module 'OSERDESE2' requires 27 connections, but only 13 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15269]
WARNING: [Synth 8-350] instance 'OSERDESE2_28' of module 'OSERDESE2' requires 27 connections, but only 17 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15291]
WARNING: [Synth 8-350] instance 'OSERDESE2_29' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15324]
INFO: [Synth 8-638] synthesizing module 'ISERDESE2' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:25007]
Parameter DATA_RATE bound to: DDR - type: string
Parameter DATA_WIDTH bound to: 8 - type: integer
Parameter DYN_CLKDIV_INV_EN bound to: FALSE - type: string
Parameter DYN_CLK_INV_EN bound to: FALSE - type: string
Parameter INIT_Q1 bound to: 1'b0
Parameter INIT_Q2 bound to: 1'b0
Parameter INIT_Q3 bound to: 1'b0
Parameter INIT_Q4 bound to: 1'b0
Parameter INTERFACE_TYPE bound to: NETWORKING - type: string
Parameter IOBDELAY bound to: IFD - type: string
Parameter IS_CLKB_INVERTED bound to: 1'b0
Parameter IS_CLKDIVP_INVERTED bound to: 1'b0
Parameter IS_CLKDIV_INVERTED bound to: 1'b0
Parameter IS_CLK_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_OCLKB_INVERTED bound to: 1'b0
Parameter IS_OCLK_INVERTED bound to: 1'b0
Parameter NUM_CE bound to: 1 - type: integer
Parameter OFB_USED bound to: FALSE - type: string
Parameter SERDES_MODE bound to: MASTER - type: string
Parameter SRVAL_Q1 bound to: 1'b0
Parameter SRVAL_Q2 bound to: 1'b0
Parameter SRVAL_Q3 bound to: 1'b0
Parameter SRVAL_Q4 bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'ISERDESE2' (11#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:25007]
WARNING: [Synth 8-350] instance 'ISERDESE2' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15350]
INFO: [Synth 8-638] synthesizing module 'IDELAYE2' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:21517]
Parameter CINVCTRL_SEL bound to: FALSE - type: string
Parameter DELAY_SRC bound to: IDATAIN - type: string
Parameter HIGH_PERFORMANCE_MODE bound to: TRUE - type: string
Parameter IDELAY_TYPE bound to: VARIABLE - type: string
Parameter IDELAY_VALUE bound to: 0 - type: integer
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_DATAIN_INVERTED bound to: 1'b0
Parameter IS_IDATAIN_INVERTED bound to: 1'b0
Parameter PIPE_SEL bound to: FALSE - type: string
Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: float
Parameter SIGNAL_PATTERN bound to: DATA - type: string
Parameter SIM_DELAY_D bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'IDELAYE2' (12#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:21517]
WARNING: [Synth 8-350] instance 'IDELAYE2' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15377]
INFO: [Synth 8-638] synthesizing module 'IOBUF' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:22655]
Parameter DRIVE bound to: 12 - type: integer
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
INFO: [Synth 8-256] done synthesizing module 'IOBUF' (13#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:22655]
WARNING: [Synth 8-350] instance 'OSERDESE2_30' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15400]
WARNING: [Synth 8-350] instance 'ISERDESE2_1' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15426]
WARNING: [Synth 8-350] instance 'IDELAYE2_1' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15453]
WARNING: [Synth 8-350] instance 'OSERDESE2_31' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15476]
WARNING: [Synth 8-350] instance 'ISERDESE2_2' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15502]
WARNING: [Synth 8-350] instance 'IDELAYE2_2' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15529]
WARNING: [Synth 8-350] instance 'OSERDESE2_32' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15552]
WARNING: [Synth 8-350] instance 'ISERDESE2_3' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15578]
WARNING: [Synth 8-350] instance 'IDELAYE2_3' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15605]
WARNING: [Synth 8-350] instance 'OSERDESE2_33' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15628]
WARNING: [Synth 8-350] instance 'ISERDESE2_4' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15654]
WARNING: [Synth 8-350] instance 'IDELAYE2_4' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15681]
WARNING: [Synth 8-350] instance 'OSERDESE2_34' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15704]
WARNING: [Synth 8-350] instance 'ISERDESE2_5' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15730]
WARNING: [Synth 8-350] instance 'IDELAYE2_5' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15757]
WARNING: [Synth 8-350] instance 'OSERDESE2_35' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15780]
WARNING: [Synth 8-350] instance 'ISERDESE2_6' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15806]
WARNING: [Synth 8-350] instance 'IDELAYE2_6' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15833]
WARNING: [Synth 8-350] instance 'OSERDESE2_36' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15856]
WARNING: [Synth 8-350] instance 'ISERDESE2_7' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15882]
WARNING: [Synth 8-350] instance 'IDELAYE2_7' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15909]
WARNING: [Synth 8-350] instance 'OSERDESE2_37' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15932]
WARNING: [Synth 8-350] instance 'ISERDESE2_8' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15958]
WARNING: [Synth 8-350] instance 'IDELAYE2_8' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:15985]
WARNING: [Synth 8-350] instance 'OSERDESE2_38' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16008]
WARNING: [Synth 8-350] instance 'ISERDESE2_9' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16034]
WARNING: [Synth 8-350] instance 'IDELAYE2_9' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16061]
WARNING: [Synth 8-350] instance 'OSERDESE2_39' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16084]
WARNING: [Synth 8-350] instance 'ISERDESE2_10' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16110]
WARNING: [Synth 8-350] instance 'IDELAYE2_10' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16137]
WARNING: [Synth 8-350] instance 'OSERDESE2_40' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16160]
WARNING: [Synth 8-350] instance 'ISERDESE2_11' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16186]
WARNING: [Synth 8-350] instance 'IDELAYE2_11' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16213]
WARNING: [Synth 8-350] instance 'OSERDESE2_41' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16236]
WARNING: [Synth 8-350] instance 'ISERDESE2_12' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16262]
WARNING: [Synth 8-350] instance 'IDELAYE2_12' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16289]
WARNING: [Synth 8-350] instance 'OSERDESE2_42' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16312]
WARNING: [Synth 8-350] instance 'ISERDESE2_13' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16338]
WARNING: [Synth 8-350] instance 'IDELAYE2_13' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16365]
WARNING: [Synth 8-350] instance 'OSERDESE2_43' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16388]
WARNING: [Synth 8-350] instance 'ISERDESE2_14' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16414]
WARNING: [Synth 8-350] instance 'IDELAYE2_14' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16441]
WARNING: [Synth 8-350] instance 'OSERDESE2_44' of module 'OSERDESE2' requires 27 connections, but only 16 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16464]
WARNING: [Synth 8-350] instance 'ISERDESE2_15' of module 'ISERDESE2' requires 28 connections, but only 15 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16490]
WARNING: [Synth 8-350] instance 'IDELAYE2_15' of module 'IDELAYE2' requires 12 connections, but only 7 given [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16517]
INFO: [Synth 8-638] synthesizing module 'VexRiscv' [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1181]
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2678]
INFO: [Synth 8-638] synthesizing module 'InstructionCache' [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:53]
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:155]
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:156]
WARNING: [Synth 8-6014] Unused sequential element decodeStage_mmuRsp_isIoAccess_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:325]
WARNING: [Synth 8-6014] Unused sequential element decodeStage_mmuRsp_allowRead_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:326]
WARNING: [Synth 8-6014] Unused sequential element decodeStage_mmuRsp_allowWrite_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:327]
INFO: [Synth 8-256] done synthesizing module 'InstructionCache' (14#1) [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:53]
INFO: [Synth 8-638] synthesizing module 'DataCache' [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:342]
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:518]
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:519]
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:520]
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:521]
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:522]
WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_valid_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060]
WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_way_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1061]
WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_address_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1062]
WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_data_valid_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1063]
WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_data_error_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1064]
WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_data_address_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1065]
WARNING: [Synth 8-6014] Unused sequential element stageB_mmuRsp_allowExecute_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1094]
WARNING: [Synth 8-6014] Unused sequential element stageB_tagsReadRsp_0_valid_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1099]
WARNING: [Synth 8-6014] Unused sequential element stageB_tagsReadRsp_0_address_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1101]
INFO: [Synth 8-256] done synthesizing module 'DataCache' (15#1) [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:342]
WARNING: [Synth 8-6014] Unused sequential element IBusCachedPlugin_rspCounter_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6356]
WARNING: [Synth 8-6014] Unused sequential element DBusCachedPlugin_rspCounter_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6360]
WARNING: [Synth 8-6014] Unused sequential element CsrPlugin_lastStageWasWfi_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6415]
WARNING: [Synth 8-6014] Unused sequential element _zz_123__reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4693]
WARNING: [Synth 8-6014] Unused sequential element _zz_130__reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4701]
WARNING: [Synth 8-6014] Unused sequential element MmuPlugin_shared_pteBuffer_V_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6949]
WARNING: [Synth 8-6014] Unused sequential element MmuPlugin_shared_pteBuffer_R_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6950]
WARNING: [Synth 8-6014] Unused sequential element MmuPlugin_shared_pteBuffer_W_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6951]
WARNING: [Synth 8-6014] Unused sequential element MmuPlugin_shared_pteBuffer_X_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6952]
WARNING: [Synth 8-6014] Unused sequential element MmuPlugin_shared_pteBuffer_U_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6953]
WARNING: [Synth 8-6014] Unused sequential element MmuPlugin_shared_pteBuffer_G_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6954]
WARNING: [Synth 8-6014] Unused sequential element MmuPlugin_shared_pteBuffer_A_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6955]
WARNING: [Synth 8-6014] Unused sequential element MmuPlugin_shared_pteBuffer_D_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6956]
WARNING: [Synth 8-6014] Unused sequential element MmuPlugin_shared_pteBuffer_RSW_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6957]
WARNING: [Synth 8-6014] Unused sequential element CsrPlugin_mcycle_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7093]
WARNING: [Synth 8-6014] Unused sequential element CsrPlugin_minstret_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7095]
WARNING: [Synth 8-6014] Unused sequential element decode_to_execute_FORMAL_PC_NEXT_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4038]
WARNING: [Synth 8-6014] Unused sequential element execute_to_memory_FORMAL_PC_NEXT_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4037]
WARNING: [Synth 8-6014] Unused sequential element memory_to_writeBack_FORMAL_PC_NEXT_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4036]
WARNING: [Synth 8-6014] Unused sequential element CsrPlugin_mtvec_mode_reg was removed. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7407]
INFO: [Synth 8-256] done synthesizing module 'VexRiscv' (16#1) [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1181]
INFO: [Synth 8-638] synthesizing module 'FDPE' [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:3904]
Parameter INIT bound to: 1'b1
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_PRE_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDPE' (17#1) [/opt/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:3904]
WARNING: [Synth 8-6014] Unused sequential element soc_liteethphymiirx_converter_converter_source_payload_valid_token_count_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:10325]
WARNING: [Synth 8-6014] Unused sequential element soc_rx_converter_converter_source_payload_valid_token_count_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:10419]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine0_cmd_buffer_first_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4894]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine0_cmd_buffer_last_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4895]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine1_cmd_buffer_first_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5062]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine1_cmd_buffer_last_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5063]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine2_cmd_buffer_first_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5230]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine2_cmd_buffer_last_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5231]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine3_cmd_buffer_first_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5398]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine3_cmd_buffer_last_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5399]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine4_cmd_buffer_first_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5566]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine4_cmd_buffer_last_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5567]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine5_cmd_buffer_first_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5734]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine5_cmd_buffer_last_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5735]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine6_cmd_buffer_first_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5902]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine6_cmd_buffer_last_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5903]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine7_cmd_buffer_first_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:6070]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_bankmachine7_cmd_buffer_last_n_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:6071]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_dfi_p0_rddata_en_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4354]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_dfi_p0_wrdata_en_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4352]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_dfi_p1_rddata_en_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4370]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_dfi_p1_wrdata_en_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4368]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_dfi_p2_wrdata_en_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4384]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_dfi_p3_rddata_en_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4402]
WARNING: [Synth 8-6014] Unused sequential element vns_rbank_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12772]
WARNING: [Synth 8-6014] Unused sequential element vns_wbank_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12775]
WARNING: [Synth 8-6014] Unused sequential element soc_leds_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12976]
WARNING: [Synth 8-6014] Unused sequential element soc_eventmanager_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12980]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_cpu_time_cmp_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13061]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_ctrl_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13106]
WARNING: [Synth 8-6014] Unused sequential element soc_a7ddrphy_half_sys8x_taps_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13139]
WARNING: [Synth 8-6014] Unused sequential element soc_a7ddrphy_dly_sel_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13143]
WARNING: [Synth 8-6014] Unused sequential element soc_writer_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13242]
WARNING: [Synth 8-6014] Unused sequential element soc_reader_slot_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13246]
WARNING: [Synth 8-6014] Unused sequential element soc_reader_length_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13253]
WARNING: [Synth 8-6014] Unused sequential element soc_reader_eventmanager_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13257]
WARNING: [Synth 8-6014] Unused sequential element soc_reset_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13275]
WARNING: [Synth 8-6014] Unused sequential element soc_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13279]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13633]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector0_command_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13637]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector0_address_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13644]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector0_baddress_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13648]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector0_wrdata_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13661]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector1_command_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13665]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector1_address_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13672]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector1_baddress_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13676]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector1_wrdata_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13689]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector2_command_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13693]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector2_address_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13700]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector2_baddress_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13704]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector2_wrdata_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13717]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector3_command_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13721]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector3_address_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13728]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector3_baddress_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13732]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_sdram_phaseinjector3_wrdata_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13745]
WARNING: [Synth 8-6014] Unused sequential element soc_spiflash_bitbang_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13763]
WARNING: [Synth 8-6014] Unused sequential element soc_spiflash_bitbang_en_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13767]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_timer0_load_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13836]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_timer0_reload_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13849]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_timer0_en_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13853]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_timer0_eventmanager_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13861]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_uart_eventmanager_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13888]
WARNING: [Synth 8-6014] Unused sequential element soc_netsoc_uart_phy_re_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:13918]
WARNING: [Synth 8-6014] Unused sequential element memdat_1_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14451]
WARNING: [Synth 8-6014] Unused sequential element memdat_3_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14468]
WARNING: [Synth 8-6014] Unused sequential element memdat_5_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16539]
WARNING: [Synth 8-6014] Unused sequential element memdat_6_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16553]
WARNING: [Synth 8-6014] Unused sequential element memdat_7_reg was removed. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16567]
INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-4471] merging register 'memadr_15_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16855]
INFO: [Synth 8-4471] merging register 'memadr_16_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16865]
INFO: [Synth 8-4471] merging register 'memadr_17_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16875]
INFO: [Synth 8-4471] merging register 'memadr_18_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16885]
INFO: [Synth 8-4471] merging register 'memadr_19_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16895]
INFO: [Synth 8-4471] merging register 'memadr_20_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16905]
INFO: [Synth 8-4471] merging register 'memadr_21_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16915]
INFO: [Synth 8-4471] merging register 'memadr_22_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16925]
INFO: [Synth 8-4471] merging register 'memadr_23_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16935]
INFO: [Synth 8-4471] merging register 'memadr_24_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16945]
INFO: [Synth 8-4471] merging register 'memadr_25_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16955]
INFO: [Synth 8-4471] merging register 'memadr_26_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16965]
INFO: [Synth 8-4471] merging register 'memadr_27_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16975]
INFO: [Synth 8-4471] merging register 'memadr_28_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16985]
INFO: [Synth 8-4471] merging register 'memadr_29_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16995]
WARNING: [Synth 8-3936] Found unconnected internal register 'soc_tx_converter_converter_source_payload_data_reg' and it is trimmed from '10' to '9' bits. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:7290]
INFO: [Synth 8-4471] merging register 'memadr_12_reg[8:0]' into 'memadr_10_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16791]
INFO: [Synth 8-4471] merging register 'memadr_13_reg[8:0]' into 'memadr_11_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16803]
INFO: [Synth 8-4471] merging register 'memadr_3_reg[8:0]' into 'memadr_14_reg[8:0]' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:16651]
INFO: [Synth 8-4471] merging register 'soc_a7ddrphy_dfi_p1_rddata_valid_reg' into 'soc_a7ddrphy_dfi_p0_rddata_valid_reg' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4308]
INFO: [Synth 8-4471] merging register 'soc_a7ddrphy_dfi_p2_rddata_valid_reg' into 'soc_a7ddrphy_dfi_p0_rddata_valid_reg' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4324]
INFO: [Synth 8-4471] merging register 'soc_a7ddrphy_dfi_p3_rddata_valid_reg' into 'soc_a7ddrphy_dfi_p0_rddata_valid_reg' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4340]
INFO: [Synth 8-4471] merging register 'soc_a7ddrphy_oe_dq_reg' into 'soc_a7ddrphy_oe_dqs_reg' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:10989]
INFO: [Synth 8-4471] merging register 'soc_netsoc_sdram_dfi_p1_cs_n_reg' into 'soc_netsoc_sdram_dfi_p0_cs_n_reg' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4360]
INFO: [Synth 8-4471] merging register 'soc_netsoc_sdram_dfi_p2_cs_n_reg' into 'soc_netsoc_sdram_dfi_p0_cs_n_reg' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4376]
INFO: [Synth 8-4471] merging register 'soc_netsoc_sdram_dfi_p3_cs_n_reg' into 'soc_netsoc_sdram_dfi_p0_cs_n_reg' [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4392]
INFO: [Synth 8-256] done synthesizing module 'top' (18#1) [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4]
WARNING: [Synth 8-3917] design top has port spiflash_1x_wp driven by constant 1
WARNING: [Synth 8-3917] design top has port spiflash_1x_hold driven by constant 1
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[31]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[30]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[29]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[28]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[27]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[26]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[25]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[24]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[23]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[22]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[21]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[20]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[19]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[18]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[17]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[16]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[15]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[14]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[13]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_execute_address[12]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_memory_mmuBus_rsp_allowExecute
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_memory_mmuBus_busy
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_isUser
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[31]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[30]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[29]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[28]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[27]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[26]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[25]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[24]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[23]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[22]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[21]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[20]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[19]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[18]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[17]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[16]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[15]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[14]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[13]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[12]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[11]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[10]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[9]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[8]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[7]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[6]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[5]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[4]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[3]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[2]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[1]
WARNING: [Synth 8-3331] design DataCache has unconnected port io_cpu_writeBack_address[0]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_isValid
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[31]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[30]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[29]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[28]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[27]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[26]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[25]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[24]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[23]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[22]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[21]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[20]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[19]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[18]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[17]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[16]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[15]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[14]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[13]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[12]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[1]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_prefetch_pc[0]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_fetch_mmuBus_rsp_isIoAccess
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_fetch_mmuBus_rsp_allowRead
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_fetch_mmuBus_rsp_allowWrite
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_isValid
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[31]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[30]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[29]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[28]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[27]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[26]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[25]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[24]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[23]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[22]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[21]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[20]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[19]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[18]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[17]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[16]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[15]
WARNING: [Synth 8-3331] design InstructionCache has unconnected port io_cpu_decode_pc[14]
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1359.766 ; gain = 213.531 ; free physical = 8751 ; free virtual = 12059
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1359.766 ; gain = 213.531 ; free physical = 8781 ; free virtual = 12083
---------------------------------------------------------------------------------
INFO: [Netlist 29-17] Analyzing 55 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.xdc]
INFO: [Timing 38-2] Deriving generated clocks [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.xdc:340]
Finished Parsing XDC File [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 20 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 16 instances
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 1 instances
OBUFTDS => OBUFTDS_DUAL_BUF (INV, OBUFTDS, OBUFTDS): 2 instances
PLLE2_BASE => PLLE2_ADV: 1 instances
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1701.492 ; gain = 0.000 ; free physical = 8507 ; free virtual = 11804
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1701.492 ; gain = 555.258 ; free physical = 8634 ; free virtual = 11914
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1701.492 ; gain = 555.258 ; free physical = 8634 ; free virtual = 11914
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:31 . Memory (MB): peak = 1701.492 ; gain = 555.258 ; free physical = 8626 ; free virtual = 11914
---------------------------------------------------------------------------------
INFO: [Synth 8-5544] ROM "lineLoader_fire" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
WARNING: [Synth 8-3936] Found unconnected internal register 'MmuPlugin_shared_pteBuffer_PPN1_reg' and it is trimmed from '12' to '10' bits. [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6959]
INFO: [Synth 8-5544] ROM "iBusWishbone_CTI" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "memory_MulDivIterativePlugin_div_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "decode_REGFILE_WRITE_VALID" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iBusWishbone_CTI" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "memory_MulDivIterativePlugin_div_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "decode_REGFILE_WRITE_VALID" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "MmuPlugin_dBusAccess_cmd_valid" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_376_" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "dBusWishbone_CTI0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "MmuPlugin_shared_state_1_" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_mstatus_MIE" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_sstatus_SIE" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_selfException_payload_code" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "IBusCachedPlugin_decodeExceptionPort_payload_code" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "DBusCachedPlugin_exceptionBus_payload_code0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "DBusCachedPlugin_exceptionBus_payload_code" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_interrupt_code" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "execute_to_memory_BRANCH_CALC" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3960]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4888]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5392]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5560]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5728]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5896]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:6064]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5224]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:5056]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:3930]
WARNING: [Synth 8-3936] Found unconnected internal register 'memdat_2_reg' and it is trimmed from '10' to '8' bits. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14456]
WARNING: [Synth 8-3936] Found unconnected internal register 'memdat_4_reg' and it is trimmed from '10' to '8' bits. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:14473]
INFO: [Synth 8-41] '+' operator could not be merged with '+' operator due to loss of accuracy [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:6352]
INFO: [Synth 8-5545] ROM "soc_writer_counter_ce" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5544] ROM "vns_liteethmacgap_next_state" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_uart_phy_sink_ready" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_uart_phy_sink_ready" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_uart_phy_source_valid" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "soc_temperature_status" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_vccint_status" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_vccaux_status" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_vccbram_status" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_spiflash_sr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_spiflash_cs_n" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_spiflash_bus_ack" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_netsoc_sdram_cmd_payload_cas" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_netsoc_sdram_cmd_payload_cas" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_netsoc_sdram_cmd_payload_we" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "soc_writer_inc" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5545] ROM "vns_liteethmacsramwriter_next_state" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5544] ROM "mem_2" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5545] ROM "soc_writer_counter_ce" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5544] ROM "vns_liteethmacgap_next_state" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_uart_phy_sink_ready" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_uart_phy_sink_ready" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_uart_phy_source_valid" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "soc_temperature_status" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_vccint_status" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_vccaux_status" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_vccbram_status" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_spiflash_sr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_spiflash_cs_n" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_spiflash_bus_ack" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_netsoc_sdram_cmd_payload_cas" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_netsoc_sdram_cmd_payload_cas" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_netsoc_sdram_cmd_payload_we" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "soc_writer_inc" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5545] ROM "vns_liteethmacsramwriter_next_state" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
INFO: [Synth 8-5544] ROM "mem_2" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "vns_liteethmacsramwriter_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_a7ddrphy_dqs_serdes_pattern" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_we" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_stb" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_reader_source_source_payload_last_be" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_reader_source_source_valid" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_writer_slot_ce" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_ic_reset" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_liteethphymiirx_converter_converter_source_payload_data" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_crc32_checker_crc_reset" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "vns_liteethmaccrc32checker_next_state" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_rx_converter_converter_source_payload_data" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_preamble_inserter_source_payload_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_preamble_inserter_clr_cnt" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "vns_liteethmacpreambleinserter_next_state" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_crc32_inserter_is_ongoing1" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_crc32_inserter_reset" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "vns_liteethmaccrc32inserter_next_state" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_padding_inserter_counter" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_padding_inserter_counter" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_uart_phy_phase_accumulator_rx" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_uart_phy_phase_accumulator_rx" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_cmd_ready" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine0_row_close" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_steerer_sel1" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_en1" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine0_twtpcon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine0_twtpcon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine0_trccon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine0_trccon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine0_trascon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine0_trascon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "vns_bankmachine0_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine1_row_close" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine1_twtpcon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine1_twtpcon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine1_trccon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine1_trccon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine1_trascon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine1_trascon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "vns_bankmachine1_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine2_row_close" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine2_twtpcon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine2_twtpcon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine2_trccon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine2_trccon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine2_trascon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine2_trascon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "vns_bankmachine2_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine3_row_close" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine3_twtpcon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine3_twtpcon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine3_trccon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine3_trccon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine3_trascon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine3_trascon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "vns_bankmachine3_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine4_row_close" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine4_twtpcon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine4_twtpcon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "soc_netsoc_sdram_bankmachine4_trccon_count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Common 17-14] Message 'Synth 8-5544' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-802] inferred FSM for state register 'vns_refresher_state_reg' in module 'top'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE2 | 00 | 00
*
iSTATE | 01 | 01
iSTATE0 | 10 | 10
iSTATE1 | 11 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'vns_refresher_state_reg' using encoding 'sequential' in module 'top'
Block RAM mem_1_reg originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
reason is address width (13) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal
address width (13) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 1701.492 ; gain = 555.258 ; free physical = 8606 ; free virtual = 11903
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 34 Bit Adders := 1
2 Input 33 Bit Adders := 3
3 Input 33 Bit Adders := 1
3 Input 32 Bit Adders := 2
2 Input 32 Bit Adders := 6
2 Input 25 Bit Adders := 1
2 Input 24 Bit Adders := 1
2 Input 16 Bit Adders := 1
2 Input 11 Bit Adders := 2
2 Input 10 Bit Adders := 1
2 Input 9 Bit Adders := 1
2 Input 8 Bit Adders := 2
2 Input 7 Bit Adders := 6
2 Input 6 Bit Adders := 3
2 Input 5 Bit Adders := 4
2 Input 4 Bit Adders := 20
2 Input 3 Bit Adders := 66
5 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 7
3 Input 2 Bit Adders := 1
2 Input 1 Bit Adders := 12
+---XORs :
2 Input 32 Bit XORs := 2
2 Input 7 Bit XORs := 4
2 Input 1 Bit XORs := 30
4 Input 1 Bit XORs := 21
3 Input 1 Bit XORs := 8
5 Input 1 Bit XORs := 16
6 Input 1 Bit XORs := 5
7 Input 1 Bit XORs := 6
+---Registers :
65 Bit Registers := 1
64 Bit Registers := 3
57 Bit Registers := 1
40 Bit Registers := 1
33 Bit Registers := 1
32 Bit Registers := 68
30 Bit Registers := 2
24 Bit Registers := 5
22 Bit Registers := 2
21 Bit Registers := 8
20 Bit Registers := 1
16 Bit Registers := 17
14 Bit Registers := 17
13 Bit Registers := 1
12 Bit Registers := 5
11 Bit Registers := 2
10 Bit Registers := 37
9 Bit Registers := 22
8 Bit Registers := 39
7 Bit Registers := 16
6 Bit Registers := 9
5 Bit Registers := 7
4 Bit Registers := 44
3 Bit Registers := 66
2 Bit Registers := 33
1 Bit Registers := 381
+---RAMs :
256K Bit RAMs := 1
128K Bit RAMs := 1
32K Bit RAMs := 1
12K Bit RAMs := 1
11K Bit RAMs := 4
8K Bit RAMs := 4
4K Bit RAMs := 16
2K Bit RAMs := 4
1024 Bit RAMs := 1
176 Bit RAMs := 8
160 Bit RAMs := 2
66 Bit RAMs := 1
40 Bit RAMs := 1
24 Bit RAMs := 1
+---ROMs :
ROMs := 1
+---Muxes :
2 Input 128 Bit Muxes := 2
2 Input 40 Bit Muxes := 1
4 Input 40 Bit Muxes := 1
2 Input 33 Bit Muxes := 4
2 Input 32 Bit Muxes := 122
4 Input 32 Bit Muxes := 10
3 Input 32 Bit Muxes := 4
29 Input 32 Bit Muxes := 1
5 Input 32 Bit Muxes := 1
2 Input 31 Bit Muxes := 1
3 Input 30 Bit Muxes := 1
2 Input 30 Bit Muxes := 1
2 Input 25 Bit Muxes := 1
2 Input 24 Bit Muxes := 2
3 Input 24 Bit Muxes := 1
3 Input 16 Bit Muxes := 1
2 Input 16 Bit Muxes := 2
2 Input 14 Bit Muxes := 14
4 Input 14 Bit Muxes := 4
4 Input 11 Bit Muxes := 1
3 Input 11 Bit Muxes := 1
2 Input 11 Bit Muxes := 1
2 Input 10 Bit Muxes := 5
4 Input 10 Bit Muxes := 4
4 Input 9 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 8 Bit Muxes := 14
3 Input 8 Bit Muxes := 2
4 Input 8 Bit Muxes := 2
10 Input 8 Bit Muxes := 1
8 Input 8 Bit Muxes := 1
31 Input 8 Bit Muxes := 1
2 Input 7 Bit Muxes := 6
2 Input 6 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
3 Input 5 Bit Muxes := 1
8 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 19
3 Input 4 Bit Muxes := 3
9 Input 4 Bit Muxes := 9
4 Input 4 Bit Muxes := 2
3 Input 3 Bit Muxes := 4
2 Input 3 Bit Muxes := 72
4 Input 3 Bit Muxes := 8
7 Input 3 Bit Muxes := 7
6 Input 3 Bit Muxes := 2
5 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 59
3 Input 2 Bit Muxes := 18
5 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 3
12 Input 2 Bit Muxes := 3
2 Input 1 Bit Muxes := 536
29 Input 1 Bit Muxes := 15
3 Input 1 Bit Muxes := 43
7 Input 1 Bit Muxes := 1
4 Input 1 Bit Muxes := 44
6 Input 1 Bit Muxes := 2
5 Input 1 Bit Muxes := 16
9 Input 1 Bit Muxes := 80
12 Input 1 Bit Muxes := 5
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module top
Detailed RTL Component Info :
+---Adders :
2 Input 33 Bit Adders := 2
2 Input 32 Bit Adders := 2
2 Input 25 Bit Adders := 1
2 Input 24 Bit Adders := 1
2 Input 16 Bit Adders := 1
2 Input 11 Bit Adders := 2
2 Input 10 Bit Adders := 1
2 Input 9 Bit Adders := 1
2 Input 8 Bit Adders := 1
2 Input 7 Bit Adders := 5
2 Input 6 Bit Adders := 1
2 Input 5 Bit Adders := 4
2 Input 4 Bit Adders := 19
2 Input 3 Bit Adders := 62
5 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 5
3 Input 2 Bit Adders := 1
2 Input 1 Bit Adders := 11
+---XORs :
2 Input 7 Bit XORs := 4
2 Input 1 Bit XORs := 28
4 Input 1 Bit XORs := 21
3 Input 1 Bit XORs := 8
5 Input 1 Bit XORs := 16
6 Input 1 Bit XORs := 5
7 Input 1 Bit XORs := 6
+---Registers :
64 Bit Registers := 3
57 Bit Registers := 1
40 Bit Registers := 1
32 Bit Registers := 23
24 Bit Registers := 5
21 Bit Registers := 8
16 Bit Registers := 17
14 Bit Registers := 17
13 Bit Registers := 1
12 Bit Registers := 5
11 Bit Registers := 2
10 Bit Registers := 1
9 Bit Registers := 22
8 Bit Registers := 34
7 Bit Registers := 16
6 Bit Registers := 7
5 Bit Registers := 6
4 Bit Registers := 36
3 Bit Registers := 57
2 Bit Registers := 13
1 Bit Registers := 184
+---RAMs :
256K Bit RAMs := 1
128K Bit RAMs := 1
12K Bit RAMs := 1
11K Bit RAMs := 4
4K Bit RAMs := 16
2K Bit RAMs := 2
176 Bit RAMs := 8
160 Bit RAMs := 2
66 Bit RAMs := 1
40 Bit RAMs := 1
24 Bit RAMs := 1
+---ROMs :
ROMs := 1
+---Muxes :
2 Input 128 Bit Muxes := 2
2 Input 40 Bit Muxes := 1
4 Input 40 Bit Muxes := 1
2 Input 32 Bit Muxes := 44
5 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 1
2 Input 31 Bit Muxes := 1
2 Input 30 Bit Muxes := 1
2 Input 24 Bit Muxes := 2
3 Input 24 Bit Muxes := 1
3 Input 16 Bit Muxes := 1
2 Input 16 Bit Muxes := 2
2 Input 14 Bit Muxes := 14
4 Input 14 Bit Muxes := 4
4 Input 11 Bit Muxes := 1
3 Input 11 Bit Muxes := 1
2 Input 11 Bit Muxes := 1
4 Input 9 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 8 Bit Muxes := 14
3 Input 8 Bit Muxes := 2
4 Input 8 Bit Muxes := 2
10 Input 8 Bit Muxes := 1
8 Input 8 Bit Muxes := 1
31 Input 8 Bit Muxes := 1
2 Input 7 Bit Muxes := 1
2 Input 6 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
3 Input 5 Bit Muxes := 1
8 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 7
4 Input 4 Bit Muxes := 2
9 Input 4 Bit Muxes := 8
3 Input 4 Bit Muxes := 2
2 Input 3 Bit Muxes := 68
4 Input 3 Bit Muxes := 6
7 Input 3 Bit Muxes := 7
6 Input 3 Bit Muxes := 2
5 Input 3 Bit Muxes := 1
3 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 40
5 Input 2 Bit Muxes := 2
3 Input 2 Bit Muxes := 15
4 Input 2 Bit Muxes := 3
12 Input 2 Bit Muxes := 3
2 Input 1 Bit Muxes := 364
3 Input 1 Bit Muxes := 30
4 Input 1 Bit Muxes := 26
5 Input 1 Bit Muxes := 16
9 Input 1 Bit Muxes := 80
12 Input 1 Bit Muxes := 5
Module InstructionCache
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
2 Input 3 Bit Adders := 1
+---Registers :
32 Bit Registers := 4
22 Bit Registers := 1
8 Bit Registers := 1
3 Bit Registers := 1
1 Bit Registers := 10
+---RAMs :
32K Bit RAMs := 1
2K Bit RAMs := 1
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 7 Bit Muxes := 1
2 Input 1 Bit Muxes := 7
Module DataCache
Detailed RTL Component Info :
+---Adders :
3 Input 32 Bit Adders := 1
2 Input 7 Bit Adders := 1
2 Input 3 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
2 Input 1 Bit XORs := 1
+---Registers :
32 Bit Registers := 5
22 Bit Registers := 1
8 Bit Registers := 4
4 Bit Registers := 2
3 Bit Registers := 3
2 Bit Registers := 2
1 Bit Registers := 24
+---RAMs :
8K Bit RAMs := 4
2K Bit RAMs := 1
+---Muxes :
2 Input 32 Bit Muxes := 10
4 Input 32 Bit Muxes := 1
2 Input 10 Bit Muxes := 1
2 Input 7 Bit Muxes := 4
2 Input 4 Bit Muxes := 3
3 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 27
Module VexRiscv
Detailed RTL Component Info :
+---Adders :
2 Input 34 Bit Adders := 1
2 Input 33 Bit Adders := 1
3 Input 33 Bit Adders := 1
3 Input 32 Bit Adders := 1
2 Input 32 Bit Adders := 4
2 Input 6 Bit Adders := 2
2 Input 4 Bit Adders := 1
2 Input 3 Bit Adders := 2
2 Input 2 Bit Adders := 2
2 Input 1 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
2 Input 1 Bit XORs := 1
+---Registers :
65 Bit Registers := 1
33 Bit Registers := 1
32 Bit Registers := 36
30 Bit Registers := 2
20 Bit Registers := 1
10 Bit Registers := 36
6 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 6
3 Bit Registers := 5
2 Bit Registers := 18
1 Bit Registers := 163
+---RAMs :
1024 Bit RAMs := 1
+---Muxes :
2 Input 33 Bit Muxes := 4
2 Input 32 Bit Muxes := 67
3 Input 32 Bit Muxes := 4
4 Input 32 Bit Muxes := 8
29 Input 32 Bit Muxes := 1
3 Input 30 Bit Muxes := 1
2 Input 25 Bit Muxes := 1
2 Input 10 Bit Muxes := 4
4 Input 10 Bit Muxes := 4
2 Input 4 Bit Muxes := 9
3 Input 4 Bit Muxes := 1
9 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 4
3 Input 3 Bit Muxes := 2
4 Input 3 Bit Muxes := 2
2 Input 2 Bit Muxes := 19
3 Input 2 Bit Muxes := 3
2 Input 1 Bit Muxes := 138
29 Input 1 Bit Muxes := 15
3 Input 1 Bit Muxes := 13
7 Input 1 Bit Muxes := 1
4 Input 1 Bit Muxes := 18
6 Input 1 Bit Muxes := 2
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-5546] ROM "soc_spiflash_cs_n" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "soc_spiflash_sr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5545] ROM "soc_writer_counter_ce" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
WARNING: [Synth 8-3917] design top has port spiflash_1x_wp driven by constant 1
WARNING: [Synth 8-3917] design top has port spiflash_1x_hold driven by constant 1
INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM ways_0_datas_reg to conserve power
INFO: [Synth 8-3971] The signal RegFilePlugin_regFile_reg was recognized as a true dual port RAM template.
INFO: [Synth 8-5784] Optimized 5 bits of RAM "storage_11_reg" due to constant propagation. Old ram width 42 bits, new ram width 37 bits.
INFO: [Synth 8-5784] Optimized 4 bits of RAM "tag_mem_reg" due to constant propagation. Old ram width 24 bits, new ram width 20 bits.
Block RAM mem_1_reg originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
reason is address width (13) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal
address width (13) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimalRAM Pipeline Warning: Read Address Register Found For RAM mem_7_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM mem_6_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM storage_11_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM storage_12_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM tag_mem_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM mem_1_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM mem_3_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain0_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain1_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain2_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain3_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain4_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain5_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain6_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain7_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain8_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain9_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain10_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain11_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain12_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain13_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain14_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM data_mem_grain15_reg. We will not be able to pipeline it. This may degrade performance.
WARNING: [Synth 8-3332] Sequential element (FDPE_4) is unused and will be removed from module top.
WARNING: [Synth 8-3332] Sequential element (FDPE_5) is unused and will be removed from module top.
WARNING: [Synth 8-3332] Sequential element (FDPE_6) is unused and will be removed from module top.
WARNING: [Synth 8-3332] Sequential element (FDPE_7) is unused and will be removed from module top.
INFO: [Synth 8-3333] propagating constant 0 across sequential element (soc_rx_converter_converter_source_first_reg)
INFO: [Synth 8-3886] merging instance 'VexRiscv/IBusCachedPlugin_fetchPc_pcReg_reg[0]' (FDE) to 'VexRiscv/IBusCachedPlugin_fetchPc_pcReg_reg[1]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (soc_netsoc_sdram_postponer_count_reg)
INFO: [Synth 8-3886] merging instance 'VexRiscv/decode_to_execute_INSTRUCTION_reg[4]' (FDE) to 'VexRiscv/decode_to_execute_BYPASSABLE_MEMORY_STAGE_reg'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\execute_to_memory_BRANCH_CALC_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\IBusCachedPlugin_fetchPc_pcReg_reg[1] )
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_112__reg[0]' (FDE) to 'VexRiscv/_zz_112__reg[1]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface0_bank_bus_dat_r_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface8_bank_bus_dat_r_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface5_bank_bus_dat_r_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface3_bank_bus_dat_r_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface0_bank_bus_dat_r_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface8_bank_bus_dat_r_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface5_bank_bus_dat_r_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface3_bank_bus_dat_r_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface0_bank_bus_dat_r_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface8_bank_bus_dat_r_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface5_bank_bus_dat_r_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface3_bank_bus_dat_r_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface0_bank_bus_dat_r_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface8_bank_bus_dat_r_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface5_bank_bus_dat_r_reg[4] )
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[0]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[0]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[1]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[1]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[2]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[2]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[3]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[3]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[4]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[4]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[5]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[5]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[6]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[6]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[7]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[7]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[8]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[8]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[9]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[9]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[10]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[10]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[11]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[11]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[12]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[12]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[13]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[13]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[14]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[14]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[15]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[15]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[16]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[16]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[17]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[17]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[18]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[18]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[19]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[19]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[20]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[20]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[21]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[21]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[22]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[22]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[23]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[23]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[24]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[24]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[25]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[25]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[26]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[26]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[27]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[27]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[28]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[28]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[29]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[29]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[30]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[30]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/iBusWishbone_DAT_MISO_regNext_reg[31]' (FD) to 'VexRiscv/dBusWishbone_DAT_MISO_regNext_reg[31]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\vns_netsoc_csrbankarray_interface5_bank_bus_dat_r_reg[3] )
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_115__reg[0]' (FDE) to 'VexRiscv/_zz_115__reg[1]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[13] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/IBusCachedPlugin_cache/lineLoader_hadError_reg)
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[22] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[23] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[24] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/dataCache_1_/loader_error_reg)
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[25] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[26] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[27] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[28] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[16] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[18] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[19] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[20] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[21] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[29] )
INFO: [Synth 8-3886] merging instance 'VexRiscv/decode_to_execute_ALU_BITWISE_CTRL_reg[1]' (FDE) to 'VexRiscv/decode_to_execute_INSTRUCTION_reg[12]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/decode_to_execute_PC_reg[0]' (FDE) to 'VexRiscv/decode_to_execute_PC_reg[1]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\externalInterruptArray_regNext_reg[17] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (VexRiscv/\CsrPlugin_interrupt_targetPrivilege_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (soc_reader_counter0_inferred/\soc_reader_counter_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (soc_reader_counter0_inferred/\soc_reader_counter_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (soc_netsoc_count_reg)
INFO: [Synth 8-3333] propagating constant 1 across sequential element (VexRiscv/dataCache_1_/\loader_waysAllocator_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/IBusCachedPlugin_s1_tightlyCoupledHit_reg)
INFO: [Synth 8-3886] merging instance 'VexRiscv/execute_to_memory_INSTRUCTION_reg[4]' (FDE) to 'VexRiscv/execute_to_memory_BYPASSABLE_MEMORY_STAGE_reg'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (soc_netsoc_sdram_sequencer_count_reg)
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_ba_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_ba_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_ba_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_cmd_payload_a_reg[13] )
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_122__reg[1]' (FDE) to 'VexRiscv/_zz_122__reg[0]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_122__reg[0]' (FDE) to 'VexRiscv/_zz_122__reg[2]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/execute_to_memory_PC_reg[1]' (FDE) to 'VexRiscv/execute_to_memory_PC_reg[0]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\_zz_112__reg[1] )
INFO: [Synth 8-3886] merging instance 'VexRiscv/memory_to_writeBack_PC_reg[1]' (FDE) to 'VexRiscv/memory_to_writeBack_PC_reg[0]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_115__reg[1]' (FDE) to 'VexRiscv/IBusCachedPlugin_s2_tightlyCoupledHit_reg'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/IBusCachedPlugin_s2_tightlyCoupledHit_reg)
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_129__reg[1]' (FDE) to 'VexRiscv/_zz_129__reg[0]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_129__reg[0]' (FDE) to 'VexRiscv/_zz_129__reg[2]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\decode_to_execute_PC_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\execute_to_memory_PC_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (VexRiscv/\memory_to_writeBack_PC_reg[0] )
WARNING: [Synth 8-3332] Sequential element (lineLoader_address_reg[4]) is unused and will be removed from module InstructionCache.
WARNING: [Synth 8-3332] Sequential element (lineLoader_address_reg[3]) is unused and will be removed from module InstructionCache.
WARNING: [Synth 8-3332] Sequential element (lineLoader_address_reg[2]) is unused and will be removed from module InstructionCache.
WARNING: [Synth 8-3332] Sequential element (lineLoader_address_reg[1]) is unused and will be removed from module InstructionCache.
WARNING: [Synth 8-3332] Sequential element (lineLoader_address_reg[0]) is unused and will be removed from module InstructionCache.
WARNING: [Synth 8-3332] Sequential element (decodeStage_mmuRsp_physicalAddress_reg[4]) is unused and will be removed from module InstructionCache.
WARNING: [Synth 8-3332] Sequential element (decodeStage_mmuRsp_physicalAddress_reg[3]) is unused and will be removed from module InstructionCache.
WARNING: [Synth 8-3332] Sequential element (decodeStage_mmuRsp_physicalAddress_reg[2]) is unused and will be removed from module InstructionCache.
WARNING: [Synth 8-3332] Sequential element (decodeStage_mmuRsp_physicalAddress_reg[1]) is unused and will be removed from module InstructionCache.
WARNING: [Synth 8-3332] Sequential element (decodeStage_mmuRsp_physicalAddress_reg[0]) is unused and will be removed from module InstructionCache.
WARNING: [Synth 8-3332] Sequential element (lineLoader_hadError_reg) is unused and will be removed from module InstructionCache.
WARNING: [Synth 8-3332] Sequential element (loader_waysAllocator_reg[0]) is unused and will be removed from module DataCache.
WARNING: [Synth 8-3332] Sequential element (loader_error_reg) is unused and will be removed from module DataCache.
WARNING: [Synth 8-3332] Sequential element (_zz_119__reg[1]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (_zz_119__reg[0]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (_zz_126__reg[1]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (_zz_126__reg[0]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (IBusCachedPlugin_s1_tightlyCoupledHit_reg) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (IBusCachedPlugin_s2_tightlyCoupledHit_reg) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[31]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[30]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[27]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[26]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[25]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[24]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[23]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[22]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[21]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[20]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[19]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[18]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[17]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[16]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[15]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[6]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[5]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[3]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[2]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[1]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_INSTRUCTION_reg[0]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[31]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[30]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[27]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[26]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[25]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[24]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[23]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[22]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[21]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[20]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[19]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[18]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[17]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[16]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[15]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[6]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[5]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[4]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[3]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[2]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[1]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_INSTRUCTION_reg[0]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_BRANCH_CALC_reg[0]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (IBusCachedPlugin_fetchPc_pcReg_reg[1]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (_zz_112__reg[1]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (decode_to_execute_PC_reg[1]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (execute_to_memory_PC_reg[0]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (memory_to_writeBack_PC_reg[0]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[31]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[30]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[29]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[28]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[27]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[26]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[25]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[24]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[23]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[22]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[21]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[20]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[19]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[18]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[17]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[16]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[15]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[14]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[13]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[12]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[11]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[10]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[9]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[8]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[7]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[6]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[5]) is unused and will be removed from module VexRiscv.
WARNING: [Synth 8-3332] Sequential element (externalInterruptArray_regNext_reg[4]) is unused and will be removed from module VexRiscv.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3333] propagating constant 1 across sequential element (VexRiscv/\CsrPlugin_interrupt_code_reg[0] )
INFO: [Synth 8-3886] merging instance 'soc_netsoc_sdram_dfi_p3_wrdata_en_reg' (FDR) to 'vns_new_master_wdata_ready0_reg'
INFO: [Synth 8-3886] merging instance 'soc_netsoc_sdram_dfi_p3_we_n_reg' (FDS) to 'soc_netsoc_sdram_dfi_p3_cas_n_reg'
INFO: [Synth 8-3333] propagating constant 1 across sequential element (soc_netsoc_sdram_dfi_p1_cas_n_reg)
INFO: [Synth 8-3333] propagating constant 1 across sequential element (soc_netsoc_sdram_dfi_p3_ras_n_reg)
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_bank_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_bank_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_bank_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\soc_netsoc_sdram_dfi_p0_address_reg[13] )
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:49 ; elapsed = 00:01:58 . Memory (MB): peak = 1732.359 ; gain = 586.125 ; free physical = 7441 ; free virtual = 11369
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
ROM:
+------------+------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+------------+---------------+----------------+
|top | memdat_reg | 8192x32 | Block RAM |
|top | memdat_reg | 8192x32 | Block RAM |
+------------+------------+---------------+----------------+
Block RAM: Preliminary Mapping Report (see note below)
+------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|InstructionCache: | ways_0_datas_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|InstructionCache: | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|DataCache: | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|DataCache: | ways_0_data_symbol0_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|DataCache: | ways_0_data_symbol1_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|DataCache: | ways_0_data_symbol2_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|DataCache: | ways_0_data_symbol3_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|top | mem_7_reg | 512 x 32(WRITE_FIRST) | | R | 512 x 32(WRITE_FIRST) | W | R | Port A and B | 4 | 0 |
|top | mem_6_reg | 512 x 32(WRITE_FIRST) | | R | 512 x 32(WRITE_FIRST) | W | R | Port A and B | 4 | 0 |
|top | storage_11_reg | 64 x 42(NO_CHANGE) | W | | 64 x 42(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|top | storage_12_reg | 64 x 42(NO_CHANGE) | W | | 64 x 42(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|top | tag_mem_reg | 512 x 24(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | mem_1_reg | 8 K x 32(WRITE_FIRST) | W | R | | | | Port A | 0 | 8 |
|top | mem_3_reg | 4 K x 32(WRITE_FIRST) | W | R | | | | Port A | 0 | 4 |
|top | data_mem_grain0_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain1_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain2_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain3_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain4_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain5_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain6_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain7_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain8_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain9_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain10_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain11_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain12_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain13_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain14_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain15_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | mem_5_reg | 512 x 32(READ_FIRST) | W | | 512 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|top | mem_4_reg | 512 x 32(READ_FIRST) | W | | 512 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
+------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Note: The tale above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+----------------+-----------+----------------------+--------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+----------------+-----------+----------------------+--------------+
|top | storage_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | storage_14_reg | Implied | 2 x 12 | RAM32M x 2 |
|top | storage_10_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | storage_3_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_9_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_8_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_7_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_6_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_4_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_5_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_2_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_13_reg | Implied | 2 x 33 | RAM32M x 6 |
|top | storage_1_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+----------------+-----------+----------------------+--------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:55 ; elapsed = 00:02:05 . Memory (MB): peak = 1732.359 ; gain = 586.125 ; free physical = 7297 ; free virtual = 11231
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:02:19 ; elapsed = 00:02:30 . Memory (MB): peak = 1969.578 ; gain = 823.344 ; free physical = 7044 ; free virtual = 11018
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
+------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|InstructionCache: | ways_0_datas_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|InstructionCache: | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|DataCache: | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|DataCache: | ways_0_data_symbol0_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|DataCache: | ways_0_data_symbol1_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|DataCache: | ways_0_data_symbol2_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|DataCache: | ways_0_data_symbol3_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|top | mem_7_reg | 512 x 32(WRITE_FIRST) | | R | 512 x 32(WRITE_FIRST) | W | R | Port A and B | 4 | 0 |
|top | mem_6_reg | 512 x 32(WRITE_FIRST) | | R | 512 x 32(WRITE_FIRST) | W | R | Port A and B | 4 | 0 |
|top | storage_11_reg | 64 x 42(NO_CHANGE) | W | | 64 x 42(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|top | storage_12_reg | 64 x 42(NO_CHANGE) | W | | 64 x 42(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|top | tag_mem_reg | 512 x 24(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | mem_1_reg | 8 K x 32(WRITE_FIRST) | W | R | | | | Port A | 0 | 8 |
|top | mem_3_reg | 4 K x 32(WRITE_FIRST) | W | R | | | | Port A | 0 | 4 |
|top | data_mem_grain0_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain1_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain2_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain3_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain4_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain5_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain6_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain7_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain8_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain9_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain10_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain11_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain12_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain13_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain14_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | data_mem_grain15_reg | 512 x 8(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|top | mem_5_reg | 512 x 32(READ_FIRST) | W | | 512 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|top | mem_4_reg | 512 x 32(READ_FIRST) | W | | 512 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
+------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Distributed RAM: Final Mapping Report
+------------+----------------+-----------+----------------------+--------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+----------------+-----------+----------------------+--------------+
|top | storage_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | storage_14_reg | Implied | 2 x 12 | RAM32M x 2 |
|top | storage_10_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | storage_3_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_9_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_8_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_7_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_6_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_4_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_5_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_2_reg | Implied | 8 x 22 | RAM32M x 4 |
|top | storage_13_reg | Implied | 2 x 33 | RAM32M x 6 |
|top | storage_1_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+----------------+-----------+----------------------+--------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-3886] merging instance 'soc_netsoc_uart_rx_fifo_consume_reg_rep[3]' (FDRE) to 'soc_netsoc_uart_rx_fifo_consume_reg[3]'
INFO: [Synth 8-3886] merging instance 'soc_netsoc_uart_rx_fifo_consume_reg_rep[2]' (FDRE) to 'soc_netsoc_uart_rx_fifo_consume_reg[2]'
INFO: [Synth 8-3886] merging instance 'soc_netsoc_uart_rx_fifo_consume_reg_rep[0]' (FDRE) to 'soc_netsoc_uart_rx_fifo_consume_reg[0]'
INFO: [Synth 8-3886] merging instance 'soc_netsoc_uart_rx_fifo_consume_reg_rep[1]' (FDRE) to 'soc_netsoc_uart_rx_fifo_consume_reg[1]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_115__reg[5]' (FDE) to 'VexRiscv/IBusCachedPlugin_cache/decodeStage_mmuRsp_physicalAddress_reg[5]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_115__reg[6]' (FDE) to 'VexRiscv/IBusCachedPlugin_cache/decodeStage_mmuRsp_physicalAddress_reg[6]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_115__reg[7]' (FDE) to 'VexRiscv/IBusCachedPlugin_cache/decodeStage_mmuRsp_physicalAddress_reg[7]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_115__reg[8]' (FDE) to 'VexRiscv/IBusCachedPlugin_cache/decodeStage_mmuRsp_physicalAddress_reg[8]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_115__reg[9]' (FDE) to 'VexRiscv/IBusCachedPlugin_cache/decodeStage_mmuRsp_physicalAddress_reg[9]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_115__reg[10]' (FDE) to 'VexRiscv/IBusCachedPlugin_cache/decodeStage_mmuRsp_physicalAddress_reg[10]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/_zz_115__reg[11]' (FDE) to 'VexRiscv/IBusCachedPlugin_cache/decodeStage_mmuRsp_physicalAddress_reg[11]'
INFO: [Synth 8-3886] merging instance 'VexRiscv/execute_to_memory_INSTRUCTION_reg[29]' (FDE) to 'VexRiscv/dataCache_1_/stageA_request_amoCtrl_alu_reg[0]'
INFO: [Synth 8-3886] merging instance 'soc_netsoc_uart_tx_fifo_consume_reg_rep[3]' (FDRE) to 'soc_netsoc_uart_tx_fifo_consume_reg[3]'
INFO: [Synth 8-3886] merging instance 'soc_netsoc_uart_tx_fifo_consume_reg_rep[2]' (FDRE) to 'soc_netsoc_uart_tx_fifo_consume_reg[2]'
INFO: [Synth 8-3886] merging instance 'soc_netsoc_uart_tx_fifo_consume_reg_rep[0]' (FDRE) to 'soc_netsoc_uart_tx_fifo_consume_reg[0]'
INFO: [Synth 8-3886] merging instance 'soc_netsoc_uart_tx_fifo_consume_reg_rep[1]' (FDRE) to 'soc_netsoc_uart_tx_fifo_consume_reg[1]'
INFO: [Synth 8-4480] The timing for the instance VexRiscv/IBusCachedPlugin_cache/ways_0_datas_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance VexRiscv/IBusCachedPlugin_cache/ways_0_tags_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance VexRiscv/dataCache_1_/ways_0_tags_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance VexRiscv/RegFilePlugin_regFile_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance VexRiscv/RegFilePlugin_regFile_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_7_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_7_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_7_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_7_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_7_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_7_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_7_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_7_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_6_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_6_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_6_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_6_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_6_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_6_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_6_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_6_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance storage_11_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance storage_12_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance tag_mem_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance tag_mem_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_1_reg_0_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_1_reg_0_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_1_reg_1_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_1_reg_1_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_1_reg_2_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_1_reg_2_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_1_reg_3_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_1_reg_3_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_3_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_3_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_3_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_3_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain0_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain1_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain2_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain3_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain4_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain5_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain6_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain7_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain8_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain9_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain10_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain11_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain12_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain13_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain14_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance data_mem_grain15_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_5_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance mem_4_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance memdat_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance memdat_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance memdat_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance memdat_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance memdat_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance memdat_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance memdat_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance memdat_reg_7 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:02:25 ; elapsed = 00:02:36 . Memory (MB): peak = 2024.242 ; gain = 878.008 ; free physical = 7027 ; free virtual = 11019
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:6800]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12929]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12929]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4610]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4610]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:10982]
WARNING: [Synth 8-5396] Clock pin CLK has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:10981]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:4]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12830]
WARNING: [Synth 8-5396] Clock pin CLK has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12829]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12830]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12829]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12828]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12827]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12826]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12825]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12824]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12823]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.v:12822]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7098]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4608]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4607]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4606]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4605]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6350]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4076]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1069]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6377]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7030]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7028]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7027]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7029]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7026]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7026]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7026]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7026]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7026]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7026]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7026]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7026]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7026]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7026]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7025]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7025]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7025]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7025]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7025]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7025]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7025]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7025]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7025]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7025]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7016]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7015]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7017]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7014]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7014]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7014]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7014]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7014]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7014]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7014]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7014]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7014]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7014]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7013]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7013]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7013]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7013]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7013]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7013]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7013]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7013]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7013]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7013]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7006]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7004]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7003]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7005]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7002]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7002]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7002]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7002]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7002]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7002]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7002]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7002]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7002]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7002]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7001]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7001]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7001]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7001]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7001]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7001]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7001]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7001]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/pdp7/dev/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7001]
INFO: [Common 17-14] Message 'Synth 8-5396' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:02:26 ; elapsed = 00:02:37 . Memory (MB): peak = 2024.242 ; gain = 878.008 ; free physical = 7025 ; free virtual = 11018
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:02:26 ; elapsed = 00:02:37 . Memory (MB): peak = 2024.242 ; gain = 878.008 ; free physical = 7025 ; free virtual = 11018
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:27 ; elapsed = 00:02:38 . Memory (MB): peak = 2024.242 ; gain = 878.008 ; free physical = 7025 ; free virtual = 11018
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:02:27 ; elapsed = 00:02:38 . Memory (MB): peak = 2024.242 ; gain = 878.008 ; free physical = 7025 ; free virtual = 11018
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:02:27 ; elapsed = 00:02:38 . Memory (MB): peak = 2024.242 ; gain = 878.008 ; free physical = 7025 ; free virtual = 11018
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:02:27 ; elapsed = 00:02:38 . Memory (MB): peak = 2024.242 ; gain = 878.008 ; free physical = 7025 ; free virtual = 11018
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+------------+--------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+------------+--------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|top | vns_new_master_rdata_valid9_reg | 10 | 1 | YES | NO | YES | 1 | 0 |
|top | soc_a7ddrphy_dfi_p0_rddata_valid_reg | 9 | 1 | YES | NO | YES | 1 | 0 |
+------------+--------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+------------+------+
| |Cell |Count |
+------+------------+------+
|1 |BUFG | 9|
|2 |BUFR | 1|
|3 |CARRY4 | 280|
|4 |DNA_PORT | 1|
|5 |IDELAYCTRL | 1|
|6 |IDELAYE2 | 16|
|7 |ISERDESE2 | 16|
|8 |LUT1 | 246|
|9 |LUT2 | 520|
|10 |LUT3 | 940|
|11 |LUT4 | 1090|
|12 |LUT5 | 1287|
|13 |LUT6 | 2434|
|14 |MUXF7 | 62|
|15 |MUXF8 | 1|
|16 |OSERDESE2 | 45|
|17 |PLLE2_BASE | 1|
|18 |RAM32M | 46|
|19 |RAMB18E1 | 6|
|20 |RAMB18E1_2 | 9|
|21 |RAMB18E1_3 | 16|
|22 |RAMB18E1_5 | 4|
|23 |RAMB36E1 | 1|
|24 |RAMB36E1_1 | 2|
|25 |RAMB36E1_10 | 1|
|26 |RAMB36E1_11 | 1|
|27 |RAMB36E1_2 | 8|
|28 |RAMB36E1_3 | 4|
|29 |RAMB36E1_4 | 1|
|30 |RAMB36E1_5 | 1|
|31 |RAMB36E1_6 | 1|
|32 |RAMB36E1_7 | 1|
|33 |RAMB36E1_8 | 1|
|34 |RAMB36E1_9 | 1|
|35 |SRL16E | 2|
|36 |STARTUPE2 | 1|
|37 |XADC | 1|
|38 |FDPE | 8|
|39 |FDRE | 4856|
|40 |FDSE | 331|
|41 |IBUF | 19|
|42 |IOBUF | 17|
|43 |OBUF | 43|
|44 |OBUFDS | 1|
|45 |OBUFTDS | 2|
+------+------------+------+
Report Instance Areas:
+------+---------------------------+-----------------+------+
| |Instance |Module |Cells |
+------+---------------------------+-----------------+------+
|1 |top | | 12335|
|2 | VexRiscv |VexRiscv | 6207|
|3 | IBusCachedPlugin_cache |InstructionCache | 1694|
|4 | dataCache_1_ |DataCache | 1208|
+------+---------------------------+-----------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:02:27 ; elapsed = 00:02:38 . Memory (MB): peak = 2024.242 ; gain = 878.008 ; free physical = 7025 ; free virtual = 11018
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 5527 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:02:20 ; elapsed = 00:02:26 . Memory (MB): peak = 2024.242 ; gain = 536.281 ; free physical = 7080 ; free virtual = 11073
Synthesis Optimization Complete : Time (s): cpu = 00:02:27 ; elapsed = 00:02:38 . Memory (MB): peak = 2024.250 ; gain = 878.008 ; free physical = 7086 ; free virtual = 11079
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 522 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.xdc:340]
INFO: [Timing 38-2] Deriving generated clocks [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.xdc:340]
get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 2406.430 ; gain = 350.172 ; free physical = 6640 ; free virtual = 10664
Finished Parsing XDC File [/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top.xdc]
INFO: [Opt 31-138] Pushed 2 inverter(s) to 34 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 67 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 17 instances
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 1 instances
OBUFTDS => OBUFTDS_DUAL_BUF (INV, OBUFTDS, OBUFTDS): 2 instances
PLLE2_BASE => PLLE2_ADV: 1 instances
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 46 instances
INFO: [Common 17-83] Releasing license: Synthesis
549 Infos, 492 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:02:37 ; elapsed = 00:02:53 . Memory (MB): peak = 2406.430 ; gain = 1273.566 ; free physical = 6913 ; free virtual = 10934
# report_timing_summary -file top_timing_synth.rpt
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
report_utilization: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2413.457 ; gain = 0.000 ; free physical = 6920 ; free virtual = 10926
# report_utilization -file top_utilization_synth.rpt
report_utilization: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2413.457 ; gain = 0.000 ; free physical = 6919 ; free virtual = 10926
# opt_design -directive default
Command: opt_design -directive default
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: default
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.80 . Memory (MB): peak = 2477.488 ; gain = 64.031 ; free physical = 6920 ; free virtual = 10922
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 2 inverter(s) to 3 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: e6985ee1
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2477.488 ; gain = 0.000 ; free physical = 6932 ; free virtual = 10934
INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 26 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1981c6d60
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.85 . Memory (MB): peak = 2477.488 ; gain = 0.000 ; free physical = 6930 ; free virtual = 10934
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 18c150c06
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2477.488 ; gain = 0.000 ; free physical = 6930 ; free virtual = 10934
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 2 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 18c150c06
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2477.488 ; gain = 0.000 ; free physical = 6930 ; free virtual = 10933
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 18c150c06
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2477.488 ; gain = 0.000 ; free physical = 6927 ; free virtual = 10933
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2477.488 ; gain = 0.000 ; free physical = 6924 ; free virtual = 10933
Ending Logic Optimization Task | Checksum: 18c150c06
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2477.488 ; gain = 0.000 ; free physical = 6903 ; free virtual = 10934
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.902 | TNS=0.000 |
INFO: [Power 33-23] Power model is not available for DNA_PORT
INFO: [Power 33-23] Power model is not available for STARTUPE2
Running Vector-less Activity Propagation...
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 58 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 2 Total Ports: 116
Ending PowerOpt Patch Enables Task | Checksum: 137815f06
Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6917 ; free virtual = 10935
Ending Power Optimization Task | Checksum: 137815f06
Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 2854.941 ; gain = 377.453 ; free physical = 6925 ; free virtual = 10943
INFO: [Common 17-83] Releasing license: Implementation
23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:11 . Memory (MB): peak = 2854.941 ; gain = 441.484 ; free physical = 6925 ; free virtual = 10943
# place_design -directive default
Command: place_design -directive default
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 tag_mem_reg has an input control pin tag_mem_reg/ENBWREN (net: tag_mem_reg_ENBWREN_cooolgate_en_sig_1) which is driven by a register (FDPE_1) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'default' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6928 ; free virtual = 10946
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12be5eccb
Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6928 ; free virtual = 10946
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6937 ; free virtual = 10951
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 16fe548d2
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6926 ; free virtual = 10940
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1f80684bb
Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6941 ; free virtual = 10935
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1f80684bb
Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6934 ; free virtual = 10936
Phase 1 Placer Initialization | Checksum: 1f80684bb
Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6935 ; free virtual = 10936
Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 19a9009a9
Time (s): cpu = 00:00:32 ; elapsed = 00:00:12 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6920 ; free virtual = 10922
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 19a9009a9
Time (s): cpu = 00:00:32 ; elapsed = 00:00:12 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6906 ; free virtual = 10923
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 13132e6c4
Time (s): cpu = 00:00:36 ; elapsed = 00:00:13 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6901 ; free virtual = 10923
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: cc6364ee
Time (s): cpu = 00:00:36 ; elapsed = 00:00:13 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6901 ; free virtual = 10922
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 14e39cbf9
Time (s): cpu = 00:00:36 ; elapsed = 00:00:13 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6901 ; free virtual = 10922
Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 14e39cbf9
Time (s): cpu = 00:00:36 ; elapsed = 00:00:14 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6901 ; free virtual = 10922
Phase 3.6 Fast Optimization
Phase 3.6 Fast Optimization | Checksum: 13577be00
Time (s): cpu = 00:00:36 ; elapsed = 00:00:14 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6900 ; free virtual = 10920
Phase 3.7 Small Shape Detail Placement
Phase 3.7 Small Shape Detail Placement | Checksum: 1d1d520d2
Time (s): cpu = 00:00:39 ; elapsed = 00:00:16 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6910 ; free virtual = 10914
Phase 3.8 Re-assign LUT pins
Phase 3.8 Re-assign LUT pins | Checksum: 27d1c7cce
Time (s): cpu = 00:00:39 ; elapsed = 00:00:16 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6902 ; free virtual = 10915
Phase 3.9 Pipeline Register Optimization
Phase 3.9 Pipeline Register Optimization | Checksum: 24984b822
Time (s): cpu = 00:00:39 ; elapsed = 00:00:16 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6900 ; free virtual = 10918
Phase 3 Detail Placement | Checksum: 24984b822
Time (s): cpu = 00:00:39 ; elapsed = 00:00:16 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6899 ; free virtual = 10917
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 22be8c68b
Phase 4.1.1.1 BUFG Insertion
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Place 46-33] Processed net sys_rst, BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-31] BUFG insertion identified 1 candidate nets, 0 success, 1 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: 22be8c68b
Time (s): cpu = 00:00:44 ; elapsed = 00:00:18 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6893 ; free virtual = 10909
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.546. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: a87df472
Time (s): cpu = 00:00:45 ; elapsed = 00:00:19 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6892 ; free virtual = 10909
Phase 4.1 Post Commit Optimization | Checksum: a87df472
Time (s): cpu = 00:00:45 ; elapsed = 00:00:19 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6892 ; free virtual = 10909
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: a87df472
Time (s): cpu = 00:00:45 ; elapsed = 00:00:19 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6893 ; free virtual = 10910
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: a87df472
Time (s): cpu = 00:00:45 ; elapsed = 00:00:19 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6893 ; free virtual = 10910
Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: f73d2266
Time (s): cpu = 00:00:45 ; elapsed = 00:00:19 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6893 ; free virtual = 10910
Phase 4 Post Placement Optimization and Clean-Up | Checksum: f73d2266
Time (s): cpu = 00:00:45 ; elapsed = 00:00:19 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6893 ; free virtual = 10911
Ending Placer Task | Checksum: b49cb517
Time (s): cpu = 00:00:45 ; elapsed = 00:00:19 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6904 ; free virtual = 10920
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:20 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6904 ; free virtual = 10921
# report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
report_utilization: Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6888 ; free virtual = 10922
# report_utilization -file top_utilization_place.rpt
report_utilization: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6886 ; free virtual = 10921
# report_io -file top_io.rpt
report_io: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6882 ; free virtual = 10916
# report_control_sets -verbose -file top_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6888 ; free virtual = 10923
# report_clock_utilization -file top_clock_utilization.rpt
# route_design -directive default
Command: route_design -directive default
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-270] Using Router directive 'default'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Checksum: PlaceDB: 13334752 ConstDB: 0 ShapeSum: a1696dc5 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 794a5ad7
Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6760 ; free virtual = 10811
Post Restoration Checksum: NetGraph: 79ddfbf NumContArr: 71ac7b18 Constraints: 0 Timing: 0
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 794a5ad7
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6748 ; free virtual = 10811
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 794a5ad7
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6719 ; free virtual = 10782
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 794a5ad7
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6719 ; free virtual = 10782
Number of Nodes with overlaps = 0
Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 18596df8f
Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6728 ; free virtual = 10786
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.483 | TNS=0.000 | WHS=-0.471 | THS=-176.993|
Phase 2 Router Initialization | Checksum: 1a2c3d488
Time (s): cpu = 00:00:24 ; elapsed = 00:00:14 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6721 ; free virtual = 10776
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 17597f54f
Time (s): cpu = 00:00:35 ; elapsed = 00:00:15 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 6714 ; free virtual = 10771
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 2438
Number of Nodes with overlaps = 545
Number of Nodes with overlaps = 137
Number of Nodes with overlaps = 34
Number of Nodes with overlaps = 17
Number of Nodes with overlaps = 37
Number of Nodes with overlaps = 15
Number of Nodes with overlaps = 7
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.210 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: edd92cce
Time (s): cpu = 00:02:00 ; elapsed = 00:00:30 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7140 ; free virtual = 11179
Phase 4 Rip-up And Reroute | Checksum: edd92cce
Time (s): cpu = 00:02:00 ; elapsed = 00:00:30 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7140 ; free virtual = 11179
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 115ceb09b
Time (s): cpu = 00:02:01 ; elapsed = 00:00:30 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7141 ; free virtual = 11179
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.289 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 5.1 Delay CleanUp | Checksum: 115ceb09b
Time (s): cpu = 00:02:01 ; elapsed = 00:00:30 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7141 ; free virtual = 11179
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 115ceb09b
Time (s): cpu = 00:02:01 ; elapsed = 00:00:30 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7141 ; free virtual = 11179
Phase 5 Delay and Skew Optimization | Checksum: 115ceb09b
Time (s): cpu = 00:02:01 ; elapsed = 00:00:30 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7141 ; free virtual = 11179
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 199379534
Time (s): cpu = 00:02:02 ; elapsed = 00:00:31 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7140 ; free virtual = 11179
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.289 | TNS=0.000 | WHS=0.014 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: e13a2ef0
Time (s): cpu = 00:02:02 ; elapsed = 00:00:31 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7140 ; free virtual = 11179
Phase 6 Post Hold Fix | Checksum: e13a2ef0
Time (s): cpu = 00:02:02 ; elapsed = 00:00:31 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7140 ; free virtual = 11179
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 5.32703 %
Global Horizontal Routing Utilization = 5.77382 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 10e5f9609
Time (s): cpu = 00:02:03 ; elapsed = 00:00:31 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7142 ; free virtual = 11179
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 10e5f9609
Time (s): cpu = 00:02:03 ; elapsed = 00:00:31 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7142 ; free virtual = 11179
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: cbd59aeb
Time (s): cpu = 00:02:03 ; elapsed = 00:00:32 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7144 ; free virtual = 11181
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.289 | TNS=0.000 | WHS=0.014 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: cbd59aeb
Time (s): cpu = 00:02:03 ; elapsed = 00:00:32 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7144 ; free virtual = 11181
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:02:03 ; elapsed = 00:00:32 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7180 ; free virtual = 11217
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:02:07 ; elapsed = 00:00:33 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7180 ; free virtual = 11217
# phys_opt_design -directive default
Command: phys_opt_design -directive default
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed)
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: default
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There is 1 register/latch pin with no clock driven by root clock pin: soc_dna_cnt_reg[0]/Q (HIGH)
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 2 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There are 33 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 60 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
0.296 0.000 0 15998 0.016 0.000 0 15994 0.264 0.000 0 5814
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
clk100 {0.000 5.000} 10.000 100.000
soc_eth_clk {0.000 20.000} 40.000 25.000
soc_pll_clk200 {0.000 2.500} 5.000 200.000
soc_pll_fb {0.000 5.000} 10.000 100.000
soc_pll_sys {0.000 5.000} 10.000 100.000
soc_pll_sys4x {0.000 1.250} 2.500 400.000
soc_pll_sys4x_dqs {0.625 1.875} 2.500 400.000
eth_rx_clk {0.000 20.000} 40.000 25.000
eth_tx_clk {0.000 20.000} 40.000 25.000
sys_clk {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
clk100 3.000 0.000 0 2
soc_eth_clk 37.845 0.000 0 1
soc_pll_clk200 3.020 0.000 0 13 0.221 0.000 0 13 0.264 0.000 0 10
soc_pll_fb 8.751 0.000 0 2
soc_pll_sys 7.845 0.000 0 2
soc_pll_sys4x 0.345 0.000 0 77
soc_pll_sys4x_dqs 0.345 0.000 0 4
eth_rx_clk 32.180 0.000 0 443 0.101 0.000 0 443 18.750 0.000 0 154
eth_tx_clk 28.256 0.000 0 224 0.124 0.000 0 224 19.500 0.000 0 103
sys_clk 0.296 0.000 0 15314 0.016 0.000 0 15314 3.750 0.000 0 5459
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
soc_pll_clk200 3.665 0.000 0 1
eth_rx_clk 2.448 0.000 0 1
eth_tx_clk 2.457 0.000 0 1
sys_clk 2.388 0.000 0 1
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# write_checkpoint -force top_route.dcp
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.60 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7171 ; free virtual = 11220
INFO: [Common 17-1381] The checkpoint '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top_route.dcp' has been generated.
# report_route_status -file top_route_status.rpt
# report_drc -file top_drc.rpt
Command: report_drc -file top_drc.rpt
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/top_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file top_power.rpt
Command: report_power -file top_power.rpt
INFO: [Power 33-23] Power model is not available for DNA_PORT
INFO: [Power 33-23] Power model is not available for STARTUPE2
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
2 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
# write_bitstream -force top.bit
Command: write_bitstream -force top.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 tag_mem_reg has an input control pin tag_mem_reg/ENBWREN (net: tag_mem_reg_ENBWREN_cooolgate_en_sig_1) which is driven by a register (FDPE_1) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Project 1-821] Please set project.enableDesignId to be 'true'.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./top.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/gateware/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Wed Feb 19 23:32:30 2020. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.3/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 2854.941 ; gain = 0.000 ; free physical = 7174 ; free virtual = 11216
# write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
Command: write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit {up 0x0 top.bit} -file top.bin
Creating config memory files...
Creating bitstream load up from address 0x00000000
Loading bitfile top.bit
Writing file ./top.bin
Writing log file ./top.prm
===================================
Configuration Memory information
===================================
File Format BIN
Interface SPIX4
Size 16M
Start Address 0x00000000
End Address 0x00FFFFFF
Addr1 Addr2 Date File(s)
0x00000000 0x0021728B Feb 19 23:32:27 2020 top.bit
0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_cfgmem completed successfully
# quit
INFO: [Common 17-206] Exiting Vivado at Wed Feb 19 23:32:31 2020...
real 4m39.477s
user 7m0.079s
sys 0m28.045s
(LX P=arty C=vexriscv.linux F=linux) pdp7@x1:~/dev/litex-buildenv$
(LX P=arty C=vexriscv.linux F=linux) pdp7@x1:~/dev/litex-buildenv$ ./scripts/build-linux.sh
Platform: arty
Target: net (default: net)
CPU: vexriscv.linux (default: lm32)
Firmare: linux (default: firmware)
Architecture: riscv32
HEAD is now at 1c163f4c7b3f Linux 5.0
rm -f build/emulator.elf
rm -f build/emulator.hex
rm -f build/emulator.map
rm -f build/emulator.v
rm -f build/emulator.bin
rm -f build/emulator.asm
find build -type f -name '*.o' -print0 | xargs -0 -r rm
mkdir -p build/src/
riscv32-elf-newlib-gcc -c -DDTB=3238002688 -Wl,--defsym,__ram_origin=0x50000000 -march=rv32i -mabi=ilp32 -DUSE_GP -I../include -O3 -DLITEX -I/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux//software/include -o build/src/main.o src/main.c
mkdir -p build/src/
riscv32-elf-newlib-gcc -c -DDTB=3238002688 -Wl,--defsym,__ram_origin=0x50000000 -march=rv32i -mabi=ilp32 -DUSE_GP -I../include -O3 -DLITEX -I/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux//software/include -o build/src/hal.o src/hal.c
mkdir -p build/src/
riscv32-elf-newlib-gcc -c -DDTB=3238002688 -Wl,--defsym,__ram_origin=0x50000000 -march=rv32i -mabi=ilp32 -DUSE_GP -I../include -O3 -DLITEX -I/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux//software/include -o build/src/start.o src/start.S -D__ASSEMBLY__=1
mkdir -p build/src/
riscv32-elf-newlib-gcc -c -DDTB=3238002688 -Wl,--defsym,__ram_origin=0x50000000 -march=rv32i -mabi=ilp32 -DUSE_GP -I../include -O3 -DLITEX -I/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux//software/include -o build/src/utils.o src/utils.S -D__ASSEMBLY__=1
mkdir -p build/src/
riscv32-elf-newlib-gcc -c -DDTB=3238002688 -Wl,--defsym,__ram_origin=0x50000000 -march=rv32i -mabi=ilp32 -DUSE_GP -I../include -O3 -DLITEX -I/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux//software/include -o build/src/trap.o src/trap.S -D__ASSEMBLY__=1
riscv32-elf-newlib-gcc -DDTB=3238002688 -Wl,--defsym,__ram_origin=0x50000000 -march=rv32i -mabi=ilp32 -DUSE_GP -I../include -O3 -DLITEX -I/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux//software/include -o build/emulator.elf build/src/main.o build/src/hal.o build/src/start.o build/src/utils.o build/src/trap.o -march=rv32i -mabi=ilp32 -lc -nostdlib -lgcc -nostartfiles -ffreestanding -Wl,-Bstatic,-T,../common/ram.ld,-Map,build/emulator.map,--print-memory-usage
Memory region Used Size Region Size %age Used
ram: 5040 B 64 KB 7.69%
riscv32-elf-newlib-objcopy -O ihex build/emulator.elf build/emulator.hex
riscv32-elf-newlib-objdump -S -d build/emulator.elf > build/emulator.asm
riscv32-elf-newlib-objdump: DWARF error: mangled line number section
riscv32-elf-newlib-objcopy -O binary build/emulator.elf build/emulator.bin
./scripts/build-linux.sh: line 192: [: =: unary operator expected
Building Linux in /home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux//software/linux
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/linux'
GEN Makefile
scripts/kconfig/conf --olddefconfig Kconfig
#
# configuration written to .config
#
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/linux'
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/linux'
GEN Makefile
scripts/kconfig/conf --syncconfig Kconfig
GEN Makefile
Using /home/pdp7/dev/litex-buildenv/third_party/linux as source for kernel
CALL /home/pdp7/dev/litex-buildenv/third_party/linux/scripts/checksyscalls.sh
<stdin>:781:2: warning: #warning syscall fstat64 not implemented [-Wcpp]
<stdin>:1078:2: warning: #warning syscall fstatat64 not implemented [-Wcpp]
CHK include/generated/compile.h
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/linux'
real 0m1.939s
user 0m3.400s
sys 0m0.955s
-rwxr-xr-x 1 pdp7 pdp7 2717924 Feb 2 17:06 /home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux//software/linux/arch/riscv/boot/Image
(LX P=arty C=vexriscv.linux F=linux)
@pdp7
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pdp7 commented Feb 19, 2020

https://github.com/timvideos/litex-buildenv/wiki/HowTo-LCA2018-FPGA-Miniconf-VexRiscv-Renode#boot-linux-via-tftp

@pdp7
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pdp7 commented Feb 19, 2020 

(LX P=arty C=vexriscv.linux F=linux) pdp7@x1:~/dev/litex-buildenv$ make tftpd_stop
# FIXME: This is dangerous...
(LX P=arty C=vexriscv.linux F=linux) pdp7@x1:~/dev/litex-buildenv$ make tftpd_start
mkdir -p build/tftpd/
Starting atftpd
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]: Advanced Trivial FTP server started (0.7)
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   running in daemon mode on port 6069
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   bound to IP address 192.168.100.100 only
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   logging level: 6
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   directory: build/tftpd//
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   user: pdp7.pdp7
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   log file: /dev/stdout
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   not forcing to listen on local interfaces.
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   server timeout: Not used
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   tftp retry timeout: 5
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   maximum number of thread: 100
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   option timeout:   enabled
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   option tzise:     enabled
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   option blksize:   enabled
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:   option multicast: enabled
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:      address range: 239.255.0.0-255
Feb 19 23:35:16 x1 atftpd[16880.139858938175552]:      port range:    1758
(LX P=arty C=vexriscv.linux F=linux) pdp7@x1:~/dev/litex-buildenv$ make tftp
mkdir -p build/arty_net_vexriscv.linux/
time python -u ./make.py --platform=arty --target=net --cpu-type=vexriscv --iprange=192.168.100 -Ob toolchain_path /home/pdp7/dev/litex-buildenv/build/Xilinx/opt/Xilinx/  --cpu-variant=linux --cpu-variant=linux  --no-compile-gateware \
	2>&1 | tee -a /home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux//output.20200219-233522.log; (exit ${PIPESTATUS[0]})
[WARNING] Deprecated, please update : shadow_base replaced by IO regions.
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/libcompiler_rt'
make[1]: Nothing to be done for 'all'.
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/libcompiler_rt'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/libbase'
 CC       exception.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       spiflash.o
 CC       mdio.o
 AR       libbase.a
 AR       libbase-nofloat.a
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/libbase'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/libnet'
 CC       microudp.o
 AR       libnet.a
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/libnet'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/bios'
 CC       isr.o
 CC       sdram.o
 CC       main.o
 CC       boot.o
 LD       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python -m litex.soc.software.mkmscimg bios.bin --little
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/bios'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/uip'
 CC       clock-arch.o
 CC       liteethmac-drv.o
 AR       libuip.a
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/uip'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/firmware'
 CC       bist.o
 CC       ci.o
/home/pdp7/dev/litex-buildenv/firmware/ci.c: In function 'status_short_print':
/home/pdp7/dev/litex-buildenv/firmware/ci.c:368:15: warning: unused variable 'underflows' [-Wunused-variable]
  unsigned int underflows;
               ^~~~~~~~~~
/home/pdp7/dev/litex-buildenv/firmware/ci.c: In function 'status_print':
/home/pdp7/dev/litex-buildenv/firmware/ci.c:467:15: warning: unused variable 'underflows' [-Wunused-variable]
  unsigned int underflows;
               ^~~~~~~~~~
At top level:
/home/pdp7/dev/litex-buildenv/firmware/ci.c:1002:21: warning: 'log2' defined but not used [-Wunused-function]
 static unsigned int log2(unsigned int v)
                     ^~~~
 CC       config.o
 CC       encoder.o
 CC       etherbone.o
 CC       ethernet.o
 CC       fx2.o
 CC       hdmi_in0.o
 CC       hdmi_out0.o
 CC       hdmi_out1.o
 CC       heartbeat.o
 CC       isr.o
 CC       main.o
 CC       mdio.o
 CC       mmcm.o
/home/pdp7/dev/litex-buildenv/firmware/mmcm.c: In function 'mmcm_dump_all':
/home/pdp7/dev/litex-buildenv/firmware/mmcm.c:110:6: warning: unused variable 'i' [-Wunused-variable]
  int i;
      ^
 CC       oled.o
 CC       opsis_eeprom.o
bash /home/pdp7/dev/litex-buildenv/firmware/version_data.sh
# Check the version files exist
[ -e /home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/include/../..//software/firmware/version_data.h ]
[ -e /home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/include/../..//software/firmware/version_data.c ]
 CC       pattern.o
 CC       pll.o
 CC       processor.o
/home/pdp7/dev/litex-buildenv/firmware/processor.c: In function 'fb_set_mode':
/home/pdp7/dev/litex-buildenv/firmware/processor.c:532:15: warning: unused variable 'hdmi_out1_enabled' [-Wunused-variable]
  unsigned int hdmi_out1_enabled;
               ^~~~~~~~~~~~~~~~~
/home/pdp7/dev/litex-buildenv/firmware/processor.c:531:15: warning: unused variable 'hdmi_out0_enabled' [-Wunused-variable]
  unsigned int hdmi_out0_enabled;
               ^~~~~~~~~~~~~~~~~
/home/pdp7/dev/litex-buildenv/firmware/processor.c: In function 'processor_service':
/home/pdp7/dev/litex-buildenv/firmware/processor.c:793:29: warning: unused variable 'm' [-Wunused-variable]
  const struct video_timing *m = &video_modes[processor_mode];
                             ^
At top level:
/home/pdp7/dev/litex-buildenv/firmware/processor.c:449:13: warning: 'fb_clkgen_write' defined but not used [-Wunused-function]
 static void fb_clkgen_write(int m, int d)
             ^~~~~~~~~~~~~~~
 CC       reboot.o
 CC       stdio_wrap.o
 CC       tofe_eeprom.o
 CC       uptime.o
 CC       version.o
 CC       pcie.o
 CC       /home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/include/../..//software/firmware/hdmi_in1.o
 LD       firmware.elf
chmod -x firmware.elf
 OBJCOPY  firmware.bin
chmod -x firmware.bin
python -m litex.soc.software.mkmscimg -f --little firmware.bin -o firmware.fbi
make[1]: Leaving directory '/home/pdp7/dev/litex-buildenv/build/arty_net_vexriscv.linux/software/firmware'

real	0m5.673s
user	0m3.277s
sys	0m0.425s
rm -rf build/tftpd/
mkdir -p build/tftpd/
cp build/arty_net_vexriscv.linux//software/linux/firmware.bin build/tftpd//Image
cp build/arty_net_vexriscv.linux//software/linux/riscv32-rootfs.cpio build/tftpd//rootfs.cpio
cp build/arty_net_vexriscv.linux//software/linux/rv32.dtb build/tftpd/
cp build/arty_net_vexriscv.linux//emulator/emulator.bin build/tftpd/

@pdp7
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pdp7 commented Feb 19, 2020 

openocd -f board/digilent_arty.cfg -c "init; pld load 0 build/arty_net_vexriscv.linux//gateware/top.bit; exit"
Open On-Chip Debugger 0.10.0+dev-01012-ged8fa09cf-dirty (2020-01-15-04:14)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
jtagspi_program
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)

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