Using OpenSBI 33f1722 (May 15th), output from: dtc -I fs /sys/firmware/devicetree/base/

opensbi-33f1722.dts

# dtc /sys/firmware/devicetree/base/
<stdout>: Warning (clocks_property): /soc/mmc@18080000:clocks: cell 0 is not a phandle reference
<stdout>: Warning (interrupts_extended_property): /soc/clint@2000000:interrupts-extended: cell 0 is not a phandle reference
<stdout>: Warning (interrupts_extended_property): /soc/clint@2000000:interrupts-extended: cell 2 is not a phandle reference
<stdout>: Warning (interrupts_extended_property): /soc/interrupt-controller@10000000:interrupts-extended: cell 0 is not a phandle reference
<stdout>: Warning (interrupts_extended_property): /soc/interrupt-controller@10000000:interrupts-extended: cell 2 is not a phandle reference
<stdout>: Warning (interrupt_provider): /cpus/cpu@0/interrupt-controller: Missing #address-cells in interrupt provider
/dts-v1/;
/ {
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	memory@8000000000 {
		device_type = "memory";
		reg = <0x80 0x00 0x00 0x80000000>;
	};
	soc {
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		compatible = "mycorp,mysoc1-dwcmshc\0simple-bus";
		ranges;
		clint@2000000 {
			interrupts-extended = <0x01 0x03 0x01 0x07>;
			compatible = "sifive,clint0";
			reg = <0x00 0x2000000 0x00 0xc0000>;
		};
		interrupt-controller@10000000 {
			#address-cells = <0x00>;
			interrupts-extended = <0x01 0x09 0x01 0xffffffff>;
			compatible = "sifive,plic-1.0.0";
			#interrupt-cells = <0x01>;
			reg = <0x00 0x10000000 0x00 0x2000000>;
			phandle = <0x02>;
			riscv,ndev = <0x1f>;
			interrupt-controller;
		};
		serial@12002000 {
			reg-io-width = <0x04>;
			interrupts = <0x03>;
			interrupt-parent = <0x02>;
			clock-frequency = <0x170b0c4>;
			current-speed = <0x1c200>;
			compatible = "ns16550a";
			reg = <0x00 0x12002000 0x00 0x1000>;
			reg-shift = <0x02>;
		};
		mmc@18080000 {
			clock-names = "core";
			bus-width = <0x08>;
			non-removable;
			no-sdio;
			interrupts = <0x1c>;
			clocks = <0x03>;
			interrupt-parent = <0x02>;
			no-sd;
			mmc-ddr-1_8v;
			compatible = "mycorp,mysoc1-dwcmshc";
			reg = <0x00 0x18080000 0x00 0x1000>;
		};
		serial@12007000 {
			reg-io-width = <0x04>;
			interrupts = <0x0f>;
			interrupt-parent = <0x02>;
			clock-frequency = <0x170b0c4>;
			current-speed = <0x1c200>;
			compatible = "ns16550a";
			reg = <0x00 0x12007000 0x00 0x1000>;
			reg-shift = <0x02>;
		};
	};
	clocks {
		clock {
			#clock-cells = <0x00>;
			clock-frequency = <0xbebc200>;
			compatible = "fixed-clock";
			phandle = <0x03>;
		};
	};
	chosen {
		linux,initrd-end = <0x80 0x80000000>;
		bootargs = "root=/dev/ram rw earlycon=sbi console=ttyS0,115200";
		linux,initrd-start = <0x80 0x7e62a410>;
	};
	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		timebase-frequency = <0x8e5d50>;
		cpu@0 {
			clock-frequency = "Yh/";
			device_type = "cpu";
			compatible = "riscv";
			mmu-type = "riscv,sv48";
			status = "okay";
			reg = <0x00>;
			riscv,isa = "rv64imafdc";
			interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <0x01>;
				phandle = <0x01>;
				interrupt-controller;
			};
		};
	};
	reserved-memory {
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		mmode_resv0@80,0 {
			reg = <0x80 0x00 0x00 0x20000>;
		};
		mmode_resv1@80,20000 {
			reg = <0x80 0x20000 0x00 0x20000>;
		};
	};
};
#