pdp7/make flash hadbadge greg.txt

## make flash hadbadge greg.txt
pdp7@x1:~/dev/greg/linux-on-litex-vexriscv$ cp ~/dev/enjoy/linux-on-litex-vexriscv/buildroot/rootfs.cpio ~/dev/enjoy/linux-on-litex-vexriscv/buildroot/Image buildroot/
pdp7@x1:~/dev/greg/linux-on-litex-vexriscv$ ls buildroot/
board  Config.in  configs  external.desc  external.mk  Image  rootfs.cpio  rv32.dtb
pdp7@x1:~/dev/greg/linux-on-litex-vexriscv$ python3 ./make.py --board=hadbadge --flash
INFO:SoC:        __   _ __      _  __
INFO:SoC:       / /  (_) /____ | |/_/
INFO:SoC:      / /__/ / __/ -_)>  <
INFO:SoC:     /____/_/\__/\__/_/|_|
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2020-02-20 14:08:37)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:ctrl CSR added at Location 0.
INFO:SoCCSRHandler:uart CSR added at Location 2.
INFO:SoCCSRHandler:timer0 CSR added at Location 3.
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging (Up to 32 Locations).
CSR Locations: (3)
- ctrl                : 0
- uart                : 2
- timer0              : 3
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR added at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoCCSRHandler:Alignment updated from 32-bit to 32-bit.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCCSRHandler:cpu CSR allocated at Location 1.
INFO:SoCIRQHandler:uart IRQ added at Location 0.
INFO:SoCIRQHandler:timer0 IRQ added at Location 1.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCCSRHandler:uart_phy CSR allocated at Location 4.
INFO:SoCCSRHandler:uart CSR added at Location 2.
INFO:SoCIRQHandler:uart IRQ added at Location 0.
INFO:SoCCSRHandler:timer0 CSR added at Location 3.
INFO:SoCIRQHandler:timer0 IRQ added at Location 1.
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCCSRHandler:sdram CSR allocated at Location 5.
INFO:SoCBusHandler:main_ram Region added at Origin: 0xc0000000, Size: 0x02000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoCBusHandler:emulator_ram Region added at Origin: 0x20000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:emulator_ram added as Bus Slave.
INFO:SoCBusHandler:spiflash Region added at Origin: 0xd0000000, Size: 0x01000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:spiflash added as Bus Slave.
INFO:SoCCSRHandler:spiflash CSR allocated at Location 6.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (6)
rom                 : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram                : Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False
emulator_ram        : Origin: 0x20000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False
main_ram            : Origin: 0xc0000000, Size: 0x02000000, Mode: RW, Cached: True Linker: False
spiflash            : Origin: 0xd0000000, Size: 0x01000000, Mode: RW, Cached: True Linker: False
csr                 : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (6)
- rom
- sram
- csr
- main_ram
- emulator_ram
- spiflash
INFO:SoC:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging (Up to 32 Locations).
CSR Locations: (7)
- ctrl                : 0
- cpu                 : 1
- uart                : 2
- timer0              : 3
- uart_phy            : 4
- sdram               : 5
- spiflash            : 6
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart                : 0
- timer0              : 1
INFO:SoC:--------------------------------------------------------------------------------
make: Entering directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/libcompiler_rt'
make: Entering directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/libbase'
 CC       exception.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       spiflash.o
 CC       mdio.o
 AR       libbase.a
 AR       libbase-nofloat.a
make: Leaving directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/libbase'
make: Entering directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/libnet'
 CC       microudp.o
 AR       libnet.a
make: Leaving directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/libnet'
make: Entering directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/bios'
 CC       isr.o
 CC       sdram.o
/usr/local/lib/python3.7/dist-packages/litex-0.2.dev0-py3.7.egg/litex/soc/software/bios/sdram.c: In function 'sdrrderr':
/usr/local/lib/python3.7/dist-packages/litex-0.2.dev0-py3.7.egg/litex/soc/software/bios/sdram.c:211:49: warning: division by zero [-Wdiv-by-zero]
    printf("%2x", DFII_PIX_DATA_BYTES/2 - 1 - (i % (DFII_PIX_DATA_BYTES/2)));
                                                 ^
 CC       main.o
 CC       boot.o
 LD       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
make: Leaving directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/bios'
buildroot/rv32.dtb: Warning (reg_format): /soc/spiflash@f0003000/flash@0:reg: property has invalid length (16 bytes) (#address-cells == 2, #size-cells == 1)
buildroot/rv32.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format'
buildroot/rv32.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
buildroot/rv32.dtb: Warning (simple_bus_reg): Failed prerequisite 'reg_format'
buildroot/rv32.dtb: Warning (avoid_default_addr_size): /soc/spiflash@f0003000/flash@0: Relying on default #address-cells value
buildroot/rv32.dtb: Warning (avoid_default_addr_size): /soc/spiflash@f0003000/flash@0: Relying on default #size-cells value
buildroot/rv32.dtb: Warning (avoid_unnecessary_addr_size): Failed prerequisite 'avoid_default_addr_size'
buildroot/rv32.dtb: Warning (unique_unit_address): Failed prerequisite 'avoid_default_addr_size'
 CC       isr.o
 CC       main.o
 LD       emulator.elf
chmod -x emulator.elf
 OBJCOPY  emulator.bin
chmod -x emulator.bin

Inserting: buildroot/Image
  Start address: 0x00200000
  Length       : 0x004d8da4 bytes
  crc32        : 0xd7eea437
           data: a4 8d 4d 00 37 a4 ee d7 73 10 40 10 97 01 4a 00

Inserting: buildroot/rootfs.cpio
  Start address: 0x00680000
  Length       : 0x003e0000 bytes
  crc32        : 0x983b3a85
           data: 00 00 3e 00 85 3a 3b 98 30 37 30 37 30 31 30 30

Inserting: buildroot/rv32.dtb
  Start address: 0x00d00000
  Length       : 0x00000784 bytes
  crc32        : 0xe284ac99
           data: 84 07 00 00 99 ac 84 e2 d0 0d fe ed 00 00 07 84

Inserting: emulator/emulator.bin
  Start address: 0x00d01000
  Length       : 0x00002570 bytes
  crc32        : 0x0cd7126b
           data: 70 25 00 00 6b 12 d7 0c 6f 00 00 0b 13 00 00 00
----------------------------------------
      Total Image Size:    9157304 bytes (69 Megabits, 8.73 Megabytes)
----------------------------------------
       Remaining space:    5522760 bytes (42 Megabits, 5.27 Megabytes)
           Total space:   14680064 bytes (112 Megabits, 14.00 Megabytes)
Error: unrecognised option '--compress'

Project Trellis - Open Source Tools for ECP5 FPGAs
Version v1.5.3
ecppack: ECP5 bitstream packer

Copyright (C) 2018 David Shah <david@symbioticeda.com>

Usage: ecppack input.config [output.bit] [options]
Allowed options:
  -h [ --help ]         show help
  -v [ --verbose ]      verbose output
  --db arg              Trellis database folder location
  --usercode arg        USERCODE to set in bitstream
  --idcode arg          IDCODE to override in bitstream
  --freq arg            config frequency in MHz
  --svf arg             output SVF file
  --svf-rowsize arg     SVF row size in bits (default 8000)
  --spimode arg         SPI Mode to use (fast-read, dual-spi, qspi)
  --background          enable background reconfiguration in bitstream
  --delta arg           create a delta partial bitstream given a reference
                        config
  --bootaddr arg        set next BOOTADDR in bitstream and enable multi-boot
  --input arg           input textual configuration
  --bit arg             output bitstream file

dfu-util 0.9

Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
Copyright 2010-2016 Tormod Volden and Stefan Schmidt
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to http://sourceforge.net/p/dfu-util/tickets/

dfu-util: Could not open file build/hadbadge/gateware/ecp5_bitstream.bit for reading: No such file or directory
dfu-util 0.9

Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
Copyright 2010-2016 Tormod Volden and Stefan Schmidt
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to http://sourceforge.net/p/dfu-util/tickets/

dfu-util: Invalid DFU suffix signature
dfu-util: A valid DFU suffix will be required in a future dfu-util release!!!
Opening DFU capable USB device...
ID 1d50:614b
Run-time device DFU version 0101
Claiming USB DFU Interface...
Setting Alternate Setting #4 ...
Determining device status: state = dfuIDLE, status = 0
dfuIDLE, continuing
DFU mode device DFU version 0101
Device returned transfer size 4096
Copying data from PC to DFU device
Download	[=========================] 100%     13645176 bytes
Download done.
state(2) = dfuIDLE, status(0) = No error condition is present
Done!
Resetting USB to switch back to runtime mode
	pdp7@x1:~/dev/greg/linux-on-litex-vexriscv$ cp ~/dev/enjoy/linux-on-litex-vexriscv/buildroot/rootfs.cpio ~/dev/enjoy/linux-on-litex-vexriscv/buildroot/Image buildroot/
	pdp7@x1:~/dev/greg/linux-on-litex-vexriscv$ ls buildroot/
	board Config.in configs external.desc external.mk Image rootfs.cpio rv32.dtb
	pdp7@x1:~/dev/greg/linux-on-litex-vexriscv$ python3 ./make.py --board=hadbadge --flash
	INFO:SoC: __ _ __ _ __
	INFO:SoC: / / (_) /____ \| \|/_/
	INFO:SoC: / /__/ / __/ -_)> <
	INFO:SoC: /____/_/\__/\__/_/\|_\|
	INFO:SoC: Build your hardware, easily!
	INFO:SoC:--------------------------------------------------------------------------------
	INFO:SoC:Creating SoC... (2020-02-20 14:08:37)
	INFO:SoC:--------------------------------------------------------------------------------
	INFO:SoCBusHandler:Creating Bus Handler...
	INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
	INFO:SoCBusHandler:Adding reserved Bus Regions...
	INFO:SoCBusHandler:Bus Handler created.
	INFO:SoCCSRHandler:Creating CSR Handler...
	INFO:SoCCSRHandler:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging (Up to 32 Locations).
	INFO:SoCCSRHandler:Adding reserved CSRs...
	INFO:SoCCSRHandler:ctrl CSR added at Location 0.
	INFO:SoCCSRHandler:uart CSR added at Location 2.
	INFO:SoCCSRHandler:timer0 CSR added at Location 3.
	INFO:SoCCSRHandler:CSR Handler created.
	INFO:SoCIRQHandler:Creating IRQ Handler...
	INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
	INFO:SoCIRQHandler:Adding reserved IRQs...
	INFO:SoCIRQHandler:IRQ Handler created.
	INFO:SoC:--------------------------------------------------------------------------------
	INFO:SoC:Initial SoC:
	INFO:SoC:--------------------------------------------------------------------------------
	INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
	INFO:SoC:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging (Up to 32 Locations).
	CSR Locations: (3)
	- ctrl : 0
	- uart : 2
	- timer0 : 3
	INFO:SoC:IRQ Handler (up to 32 Locations).
	INFO:SoC:--------------------------------------------------------------------------------
	INFO:SoCCSRHandler:ctrl CSR added at Location 0.
	INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
	INFO:SoCCSRHandler:Alignment updated from 32-bit to 32-bit.
	INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
	INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
	INFO:SoCCSRHandler:cpu CSR allocated at Location 1.
	INFO:SoCIRQHandler:uart IRQ added at Location 0.
	INFO:SoCIRQHandler:timer0 IRQ added at Location 1.
	INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
	INFO:SoCBusHandler:rom added as Bus Slave.
	INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
	INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
	INFO:SoCBusHandler:sram added as Bus Slave.
	INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
	INFO:SoCCSRHandler:uart_phy CSR allocated at Location 4.
	INFO:SoCCSRHandler:uart CSR added at Location 2.
	INFO:SoCIRQHandler:uart IRQ added at Location 0.
	INFO:SoCCSRHandler:timer0 CSR added at Location 3.
	INFO:SoCIRQHandler:timer0 IRQ added at Location 1.
	INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
	INFO:SoCBusHandler:csr added as Bus Slave.
	INFO:SoCCSRHandler:bridge added as CSR Master.
	INFO:SoCCSRHandler:sdram CSR allocated at Location 5.
	INFO:SoCBusHandler:main_ram Region added at Origin: 0xc0000000, Size: 0x02000000, Mode: RW, Cached: True Linker: False.
	INFO:SoCBusHandler:main_ram added as Bus Slave.
	INFO:SoCBusHandler:emulator_ram Region added at Origin: 0x20000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
	INFO:SoCBusHandler:emulator_ram added as Bus Slave.
	INFO:SoCBusHandler:spiflash Region added at Origin: 0xd0000000, Size: 0x01000000, Mode: RW, Cached: True Linker: False.
	INFO:SoCBusHandler:spiflash added as Bus Slave.
	INFO:SoCCSRHandler:spiflash CSR allocated at Location 6.
	INFO:SoC:--------------------------------------------------------------------------------
	INFO:SoC:Finalized SoC:
	INFO:SoC:--------------------------------------------------------------------------------
	INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
	IO Regions: (1)
	io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
	Bus Regions: (6)
	rom : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
	sram : Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False
	emulator_ram : Origin: 0x20000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False
	main_ram : Origin: 0xc0000000, Size: 0x02000000, Mode: RW, Cached: True Linker: False
	spiflash : Origin: 0xd0000000, Size: 0x01000000, Mode: RW, Cached: True Linker: False
	csr : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
	Bus Masters: (2)
	- cpu_bus0
	- cpu_bus1
	Bus Slaves: (6)
	- rom
	- sram
	- csr
	- main_ram
	- emulator_ram
	- spiflash
	INFO:SoC:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging (Up to 32 Locations).
	CSR Locations: (7)
	- ctrl : 0
	- cpu : 1
	- uart : 2
	- timer0 : 3
	- uart_phy : 4
	- sdram : 5
	- spiflash : 6
	INFO:SoC:IRQ Handler (up to 32 Locations).
	IRQ Locations: (2)
	- uart : 0
	- timer0 : 1
	INFO:SoC:--------------------------------------------------------------------------------
	make: Entering directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/libcompiler_rt'
	make: Nothing to be done for 'all'.
	make: Leaving directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/libcompiler_rt'
	make: Entering directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/libbase'
	CC exception.o
	CC system.o
	CC id.o
	CC uart.o
	CC time.o
	CC spiflash.o
	CC mdio.o
	AR libbase.a
	AR libbase-nofloat.a
	make: Leaving directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/libbase'
	make: Entering directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/libnet'
	CC microudp.o
	AR libnet.a
	make: Leaving directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/libnet'
	make: Entering directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/bios'
	CC isr.o
	CC sdram.o
	/usr/local/lib/python3.7/dist-packages/litex-0.2.dev0-py3.7.egg/litex/soc/software/bios/sdram.c: In function 'sdrrderr':
	/usr/local/lib/python3.7/dist-packages/litex-0.2.dev0-py3.7.egg/litex/soc/software/bios/sdram.c:211:49: warning: division by zero [-Wdiv-by-zero]
	printf("%2x", DFII_PIX_DATA_BYTES/2 - 1 - (i % (DFII_PIX_DATA_BYTES/2)));
	^
	CC main.o
	CC boot.o
	LD bios.elf
	chmod -x bios.elf
	OBJCOPY bios.bin
	chmod -x bios.bin
	python3 -m litex.soc.software.mkmscimg bios.bin --little
	make: Leaving directory '/home/pdp7/dev/greg/linux-on-litex-vexriscv/build/hadbadge/software/bios'
	buildroot/rv32.dtb: Warning (reg_format): /soc/spiflash@f0003000/flash@0:reg: property has invalid length (16 bytes) (#address-cells == 2, #size-cells == 1)
	buildroot/rv32.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format'
	buildroot/rv32.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
	buildroot/rv32.dtb: Warning (simple_bus_reg): Failed prerequisite 'reg_format'
	buildroot/rv32.dtb: Warning (avoid_default_addr_size): /soc/spiflash@f0003000/flash@0: Relying on default #address-cells value
	buildroot/rv32.dtb: Warning (avoid_default_addr_size): /soc/spiflash@f0003000/flash@0: Relying on default #size-cells value
	buildroot/rv32.dtb: Warning (avoid_unnecessary_addr_size): Failed prerequisite 'avoid_default_addr_size'
	buildroot/rv32.dtb: Warning (unique_unit_address): Failed prerequisite 'avoid_default_addr_size'
	CC isr.o
	CC main.o
	LD emulator.elf
	chmod -x emulator.elf
	OBJCOPY emulator.bin
	chmod -x emulator.bin

	Inserting: buildroot/Image
	Start address: 0x00200000
	Length : 0x004d8da4 bytes
	crc32 : 0xd7eea437
	data: a4 8d 4d 00 37 a4 ee d7 73 10 40 10 97 01 4a 00

	Inserting: buildroot/rootfs.cpio
	Start address: 0x00680000
	Length : 0x003e0000 bytes
	crc32 : 0x983b3a85
	data: 00 00 3e 00 85 3a 3b 98 30 37 30 37 30 31 30 30

	Inserting: buildroot/rv32.dtb
	Start address: 0x00d00000
	Length : 0x00000784 bytes
	crc32 : 0xe284ac99
	data: 84 07 00 00 99 ac 84 e2 d0 0d fe ed 00 00 07 84

	Inserting: emulator/emulator.bin
	Start address: 0x00d01000
	Length : 0x00002570 bytes
	crc32 : 0x0cd7126b
	data: 70 25 00 00 6b 12 d7 0c 6f 00 00 0b 13 00 00 00
	----------------------------------------
	Total Image Size: 9157304 bytes (69 Megabits, 8.73 Megabytes)
	----------------------------------------
	Remaining space: 5522760 bytes (42 Megabits, 5.27 Megabytes)
	Total space: 14680064 bytes (112 Megabits, 14.00 Megabytes)
	Error: unrecognised option '--compress'

	Project Trellis - Open Source Tools for ECP5 FPGAs
	Version v1.5.3
	ecppack: ECP5 bitstream packer

	Copyright (C) 2018 David Shah <david@symbioticeda.com>

	Usage: ecppack input.config [output.bit] [options]
	Allowed options:
	-h [ --help ] show help
	-v [ --verbose ] verbose output
	--db arg Trellis database folder location
	--usercode arg USERCODE to set in bitstream
	--idcode arg IDCODE to override in bitstream
	--freq arg config frequency in MHz
	--svf arg output SVF file
	--svf-rowsize arg SVF row size in bits (default 8000)
	--spimode arg SPI Mode to use (fast-read, dual-spi, qspi)
	--background enable background reconfiguration in bitstream
	--delta arg create a delta partial bitstream given a reference
	config
	--bootaddr arg set next BOOTADDR in bitstream and enable multi-boot
	--input arg input textual configuration
	--bit arg output bitstream file

	dfu-util 0.9

	Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
	Copyright 2010-2016 Tormod Volden and Stefan Schmidt
	This program is Free Software and has ABSOLUTELY NO WARRANTY
	Please report bugs to http://sourceforge.net/p/dfu-util/tickets/

	dfu-util: Could not open file build/hadbadge/gateware/ecp5_bitstream.bit for reading: No such file or directory
	dfu-util 0.9

	Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
	Copyright 2010-2016 Tormod Volden and Stefan Schmidt
	This program is Free Software and has ABSOLUTELY NO WARRANTY
	Please report bugs to http://sourceforge.net/p/dfu-util/tickets/

	dfu-util: Invalid DFU suffix signature
	dfu-util: A valid DFU suffix will be required in a future dfu-util release!!!
	Opening DFU capable USB device...
	ID 1d50:614b
	Run-time device DFU version 0101
	Claiming USB DFU Interface...
	Setting Alternate Setting #4 ...
	Determining device status: state = dfuIDLE, status = 0
	dfuIDLE, continuing
	DFU mode device DFU version 0101
	Device returned transfer size 4096
	Copying data from PC to DFU device
	Download [=========================] 100% 13645176 bytes
	Download done.
	state(2) = dfuIDLE, status(0) = No error condition is present
	Done!
	Resetting USB to switch back to runtime mode