gistfile1.txt

pdp7@x1:~/dev/enjoy/greg-linux-on-litex-vexriscv$ git log -1
commit 9cd9ff8b75f2e577252b89fc361f336398089a72 (HEAD -> hadbadge-flash, origin/hadbadge-flash)
Author: Greg Davill <greg.davill@gmail.com>
Date:   Sat Feb 22 19:28:01 2020 +1030

    hadbadge: WIP framebuffer support
pdp7@x1:~/dev/enjoy/greg-linux-on-litex-vexriscv$ python3 ./make.py --board=hadbadge --build --flash
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2020-02-22 15:11:51)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:ctrl CSR added at Location 0.
INFO:SoCCSRHandler:uart CSR added at Location 2.
INFO:SoCCSRHandler:timer0 CSR added at Location 3.
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging (Up to 32 Locations).
CSR Locations: (3)
- ctrl                : 0
- uart                : 2
- timer0              : 3
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR added at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoCCSRHandler:Alignment updated from 32-bit to 32-bit.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCCSRHandler:cpu CSR allocated at Location 1.
INFO:SoCIRQHandler:uart IRQ added at Location 0.
INFO:SoCIRQHandler:timer0 IRQ added at Location 1.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCCSRHandler:uart_phy CSR allocated at Location 4.
INFO:SoCCSRHandler:uart CSR added at Location 2.
INFO:SoCIRQHandler:uart IRQ added at Location 0.
INFO:SoCCSRHandler:timer0 CSR added at Location 3.
INFO:SoCIRQHandler:timer0 IRQ added at Location 1.
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCCSRHandler:sdram CSR allocated at Location 5.
INFO:SoCBusHandler:main_ram Region added at Origin: 0xc0000000, Size: 0x02000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoCBusHandler:emulator_ram Region added at Origin: 0x20000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:emulator_ram added as Bus Slave.
INFO:SoCBusHandler:spiflash Region added at Origin: 0xd0000000, Size: 0x01000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:spiflash added as Bus Slave.
INFO:SoCCSRHandler:spiflash CSR allocated at Location 6.
Traceback (most recent call last):
  File "./make.py", line 452, in <module>
    main()
  File "./make.py", line 413, in main
    soc.add_framebuffer(video_settings)
  File "/home/pdp7/dev/enjoy/greg-linux-on-litex-vexriscv/soc_linux.py", line 218, in add_framebuffer
    from dma import StreamReader, StreamWriter
ModuleNotFoundError: No module named 'dma'