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@pdp7
Last active May 20, 2023 18:49
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linux-riscv reference: mysoc.dts
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <9330000>;
cpu@0 {
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
clock-frequency = <1500000000>;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
memory@8000000000 {
device_type = "memory";
reg = <0x80 0 0x00000000 0x80000000>;
};
clocks {
clk_200mhz: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "mycorp,mysoc1-dwcmshc", "simple-bus";
ranges;
clint@2000000 {
compatible = "sifive,clint0";
reg = <0 0x2000000 0 0xc0000>;
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7>;
};
plic0: interrupt-controller@10000000 {
#address-cells = <0>;
#interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0";
reg = <0 0x10000000 0 0x2000000>;
riscv,ndev = <31>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 9 &cpu0_intc 11>;
};
uart0: serial@12007000 {
interrupt-parent = <&plic0>;
compatible = "ns16550a";
reg = <0 0x12007000 0 0x1000>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24162500>;
current-speed = <115200>;
interrupts = <15>;
};
uart1: serial@12002000 {
interrupt-parent = <&plic0>;
compatible = "ns16550a";
reg = <0 0x12002000 0 0x1000>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24162500>;
current-speed = <115200>;
interrupts = <3>;
};
mmc0: mmc@18080000 {
compatible = "mycorp,mysoc1-dwcmshc";
reg = <0 0x18080000 0 0x1000>;
clocks = <&clk_200mhz>;
clock-names = "core";
bus-width = <8>;
interrupt-parent = <&plic0>;
interrupts = <28>;
non-removable;
mmc-ddr-1_8v;
no-sdio;
no-sd;
};
};
chosen {
linux,initrd-start = <0x00000080 0x7e6372b4>;
linux,initrd-end = <0x00000080 0x80000000>;
bootargs = "root=/dev/ram rw earlycon=sbi console=ttyS0,115200";
};
};
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